104 Electronics Engineering Electromagnetic Theory

40. Sol. R2 1.01 l 2

= = 1.0201
f = 5 GHz, G = 150, R = 1 km R1 l
Pt = 100 kW, = 3 m2 Percentage change in radiation resistance
8 2 R2 R1
3 × 10 × 100
150 × 3 =
(G )2 5 × 10 9 R1
Pr = 3 4
× Pt = × 10 5
(4 ) R (4 )3 1012 = 0.0201 × 100 = 2.01%

81 × 3 × 10 5 8 44. (b)
= = 1.224 × 10
(4 )3 × 1012
z
= 0.012 µW

41. (c) Idl

Idl
As per Friis free space propagation equation,
Image
Wt Aer Aet h theory
Wr = h
( d )2
y
when Aer and Aet are doubled and d also doubled,
Infinite conduction plate
Wr is same. Hence capacity is also same. h

42. (a)
Idl
XY plane means Z = 0 with Z = r cos (spherical
coordinates) = 90°.
With null points along the axis of the dipole it Total E = (Esingle element ) (A.F.)
is = 45° and 225°.
y
sin N sin 2
2 2
z (A.F.) = =
null
sin sin
2 2
–
2 sin cos
2 2
= 45° = = 2 cos
x 2
/2 sin
Dipole 2
+

2 cos
A.F 2
A.FN = = = cos
null
A.Fmax 2 2

where, 2
d cos = (2 h ) cos
43. Sol.
Radiation resistance of a small dipole current 2
A.FN = 60° = cos h cos 60°
element of length ‘l’ is

l 2 h
R rad = 80 2 R l2 = cos

2
cos is maximum, whenever = n , n = 0, 1, 2....
R2 l2
= h
R1 l1 =n h = nl
If length is changed by 1% then percentage For n = 1, hmin =
change in the radiation resistance,
 GATE Previous Years Solved Paper 105

45. (0.244) Prad × D × 2

E=
Given: Directive gain, 4 r2
10 log D = 6
D = 100.6 = 3.98 16 × 10 3 × 3.98 × 2 × 120
=
Prad = 16 kW 4 × (8 × 10 3 )2
r = 8 km
= 2
Directivity (or) Directive gain is given by 5.97 × 10 = 0.244 V/m
Amplitude of electric field intensity
Umax r 2 Wrad
D= 4 =4 E = 0.244 V/m
Prad Prad

E2
4 r2 ×
2
=
Prad
 GATE-2023
Electronics Engineering

Digital Electronics
Chapterwise & Topicwise

Contents
S.No. Topic Page No.

1. Number Systems ................................................................................................................................... 1-4

2. Boolean Algebra .................................................................................................................................. 5-14

3. Logic Gates ......................................................................................................................................... 15-27

4. Combinational Circuits ................................................................................................................... 28-44

5. Sequential Circuits ........................................................................................................................... 45-69

6. Finite State Machine and Miscellaneous .................................................................................. 70-75

7. Logic Families .................................................................................................................................... 76-88

8. Memories ............................................................................................................................................ 89-92

9. ADC and DAC .................................................................................................................................... 93-98

 1 Number Systems

ELECTRO NICS EN GINEERIN G (a) 110100 (b) 001101

(c) 110111 (d) 111101
(GATE Previous Years Solved Papers)
[EC-1998 : 1 Mark]
Q.1 The subtraction of a binary number Y from
Q.5 The 2’s complement representation of –17 is
another binary number X, done by adding the
2’s complement of Y to X, results in a binary (a) 101110 (b) 101111
number without overflow. This implies that the (c) 111110 (d) 110001
result is [EC-2001 : 1 Mark]
(a) negative and is in normal form. Q.6 4-bit 2’s complement representation of a decimal
(b) negative and is in 2’s complement form. number is 1000. The number is
(c) positive and is in normal form. (a) +8 (b) 0
(d) positive and is in 2’s complement form. (c) –7 (d) –8
[EC-1987 : 1 Mark] [EC-2002 : 1 Mark]
Q.2 2’s complement representation of a 16-bit Q.7 The range of signed decimal numbers that can
number (one sign bit and 15 magnitude bits) if be represented by 6-bit 1’s complement number
FFFF. Its magnitude in decimal representation is
is
(a) –31 to +31 (b) –63 to +63
(a) 0 (b) 1
(c) –64 to +63 (d) –32 to +31
(c) 32, 767 (d) 65, 535
[EC-2004 : 1 Mark]
[EC-1993 : 1 Mark]
Q.8 11001, 1001 and 111001 correspond to the 2’s
Q.3 A signed integer has been stored in a byte using
complement representation of which one of the
the 2’s complement format. We wish to store the
following sets of number?
same integer in a 16-bit word. We should
(a) 25, 9 and 57 respectively
(a) copy the original byte to the less significant
(b) –6, –6 and –6 respectively
byte of the word and fill the more significant
byte with zeros. (c) –7, –7 and –7 respectively

(b) copy the original byte to the more significant (d) –25, –9 and –57 respectively
byte of the word and fill the less significant [EC-2004 : 1 Mark]
byte with zeros. Q.9 Decimal 43 in Hexadecimal and BCD number
(c) copy the original byte to the less significant system is respectively
byte of the word and make each bit of the (a) B2, 0100 0011 (b) 2B, 0100 0011
more significant byte equal to the most
(c) 2B, 0011 0100 (d) B2, 0100, 0100
significant bit of the original byte.
[EC-2005 : 1 Mark]
(d) copy the original byte to the less significant
bytes well as the more significant byte of Q.10 A new Binary Coded Pentary (BCP) number
the word. system is proposed in which every digit of a
[EC-1997 : 1 Mark] base-5 number is represented by its
corresponding 3-bit binary code. For example,
Q.4 An equivalent 2’s complement representation
the base-5 number 24 will be represented by its
of the 2’s complement number 1101 is
 2 Electronics Engineering Digital Electronics

BCP code 010100. In this numbering system, the Q.14 P, Q and R are the decimal integers
BCP code 100010011001 corresponding to the corresponding to the 4-bit binary number 1100
following number in base-5 system. considered in signed magnitude, 1’s
(a) 423 (b) 1324 complement, and 2’s complement
(c) 2201 (d) 4231 representations, respectively. The 6-bit 2’s
[EC-2006 : 2 Marks] complement representation of (P + Q + R) is
(a) 111101 (b) 110101
Q.11 X = 01110 and Y = 11001 are two 5-bit binary
(c) 110010 (d) 111001
numbers represented in two’s complement
[EC-2020 : 2 Marks]
format. The sum of X and Y represented in 2’s
complement format using 6-bits is Q.15 If (1235)x = (3033)y, where ‘x’ and ‘y’ indicate
(a) 100111 (b) 001000 the bases of the corresponding numbers, then
(c) 000111 (d) 101001 (a) x = 9 and y = 7 (b) x = 8 and y = 6
[EC-2007 : 1 Mark] (c) x = 6 and y = 4 (d) x = 7 and y = 5

Q.12 The two numbers represented in signed 2’s [EC-2021 : 1 Mark]

complement form are: Q.16 Select the Boolean function(s) equivalent to
P = 11101101 and Q = 11100110 x + yz, where x, y and z are Boolean variables,
If Q is subtracted from P, the value obtained in and +denotes logical OR operation.
signed 2’s complement form is
(a) x + z + xy (b) (x + y) (x + z)
(a) 100000111 (b) 00000111
(c) x + xy + yz (d) x + xz + xy
(c) 111111001 (d) 11111001
[EC-2022]
[EC-2008 : 2 Marks]

Q.13 The number of bytes required to represent the

decimal number 1856357 in packed BCD
(Binary Coded Decimal) form is ______ .
[EC-2014 : 1 Mark]
 GATE Previous Years Solved Paper 3

Electronics & Electrical Engineering

GATE Previous Years Solved Paper

A n swe rs & Expl a n a t i o n s

Answers
EC Number Systems

1. (b, c) 2. (b) 3. (c) 4. (d) 5. (b) 6. (d) 7. (a) 8. (c)

9. (b) 10. (d) 11. (c) 12. (b) 13. (4) 14. (b) 15. (b) 16. (b, c)

Solutions
EC Number Systems

1. (b, c) Take 2’s complement for magnitude

Negative and is in 2’s complement form. 0111
Positive and is in normal form. 1
+ =8
1000
2. (b)
1
7. (a)
FFFF
1111 1111 1111 1111 Range = – (2n – 1 – 1) to + (2n – 1 – 1)
2’s complement = – (26 – 1 – 1) to + (26 – 1 – 1)
0000 0000 0000 0001 = – 31 to +31
=0001
=1 8. (c)
11001 00111(+7)
3. (c) 1001 0111(+7)
The MSB of the integer in 8-bit formal should be 111001 000111(+7)
repeated to expand the representation of 2’s Number given in question in 2’s
complement form of 16-bit. complement correspond to –7.
4. (b)
9. (b)
According to sign bit extension the sign bit can
be extended towards left. 16 43
(43)10 16 2 B
5. (b) 0 2
17 = 010001
–17 = 101111 (2’s complement) (2B)H (43)10 = (01000011)BCD

6. (d) 10. (d)

100 100010011001 4231
MSB is 1 so, –ve number
4 Electronics Engineering Digital Electronics

11. (c) 14. (b)

X = 01110 Given, binary number 1100

1’s complement of 1100 = –3
Y = 11001
Sign magnitude of 1100 = –4
X+Y =100111
2’s complement of 1100 = –4
Carry is discarded in the addition of numbers
P + Q + R = –4 – 3 – 4
represented in 2’s complement form. X + Y in
= –11
6-bits is 000111.
The 6 digit 2’s complement of (–11) = 110101
12. (b)
415. (b)
Q Signed 2’s complement of
(1235)x = (3033)y
P = 11101101
Convert LHS, RHS into decimal,
No. P = 00010011
1 × x3 + 2 × x2 + 3 × x1 + 5 × x0 = 3 × y3 + 0 + 3 ×
Q Signed 2’s complement of
y1 + 3 × y0
Q = 11100110
(x3 + 2x2 + 3x + 5)10 = (3y3 + 3y + 3)10
P – Q = P + (2’s complement of Q)
Substituting the given options, we find x = 8,
= 00010011 y=6
11100110 i.e. 83 + 2(8)2 + 3(8) + 5 = 3(63) + 3(6) + 3
+
11111001 LHS: 512 + 128 + 24 + 5 = 669 10
2’s complement of RHS: 3(216) + 18 + 3 = 669 10
(P – Q) = 00000111 16. (b, c)
13. Sol. Given, f = x + yz
To represent decimal number into BCD number (a) x + xy + xz = x(1 + y) + xz = x + xz = x
each decimal number is represented in 4-bits (b) (x + y) (x + z) = x + yz
while converting in BCD numbers, as (c) x + xy + yz = x(1 + y) + yz = x + yz
1 0001 6 0110 (d) xy + yz = y(x + z)
8 1000 3 0011 So, option (b, c) are correct.
5 0101 5 0101
7 0111
(1 8 5 6 3 5 7) 0000 0001 1000 0101
1 byte 1 byte

0110 0011 0101 0111

1 byte 1 byte
So, total bytes are required.
 2 Boolean Algebra

ELECTRO NICS EN GINEERIN G Q.5 The minimized form of the logical expression

(GATE Previous Years Solved Papers) ( ABC + ABC + ABC + ABC ) is

Q.1 The number of Boolean functions that can be (a) AC + BC + AB
generated by n-variables is equal to
(b) AC + BC + AB
2n 1 2n
(a) 2 (b) 2 (c) AC + BC + AB
(c) 2n – 1 (d) 2n
(d) AC + BC + AB
[EC-1990 : 1 Mark]
[EC-1999 : 2 Marks]
Q.2 Two 2’s complement numbers having sign bits
Q.6 The number of distinct Boolean expressions of
x and y are added and the sign bit of the result
4 variables is
is z. Then, the occurrence of overflow is indicated
by the Boolean function. (a) 16 (b) 256
(c) 1024 (d) 65536
(a) xyz (b) x y z
[EC-2003 : 1 Mark]
(c) x y z + x y z (d) xy + yz + zx
Q.7 If the functions W, X, Y and Z are as follows:
[EC-1998 : 1 Mark]
W = R + PQ + RS
Q.3 The K-map for a Boolean function is shown in
X = PQRS + PQRS + PQRS
figure. The number of essential prime implicants
for this function is Y = RS + PR + PQ + PQ

AB Z = R + S + PQ + PQR + PQS
CD 00 01 11 10
Then,
00 1 1 0 1
(a) W = Z , X = Z (b) W = Z, X = Y
01 0 0 0 1
(c) W = Y (d) W = Y = Z
11 1 0 0 0 [EC-2003 : 2 Marks]
10 1 0 0 1
Q.8 The Boolean expression AC + BC is equivalent
to
(a) 4 (b) 5
(c) 6 (d) 8 (a) AC + BC + AC
[EC-1998 : 1 Mark] (b) BC + AC + BC + ACB
(c) AC + BC + BC + ABC
Q.4 The logical expression y = A + AB is
(d) ABC + ABC + ABC + ABC
equivalent to
[EC-2004 : 2 Marks]
(a) y = AB (b) y = AB
Q.9 The Boolean expression for the truth table
(c) y = A + B (d) y = A + B
shown is
[EC-1998 : 1 Mark]
 6 Electronics Engineering Digital Electronics

A B C f Q.14 The Boolean expression:

0 0 0 0
( X + Y ) ( X + Y ) + ( XY ) + X simplifies to
0 0 1 0
0 1 0 0 (a) X (b) Y
0 1 1 1 (c) XY (d) X + Y
1 0 0 0 [EC-2014 : 1 Mark]
1 0 1 0
1 1 0 1 Q.15 Consider the Boolean function:
1 1 1 0 F( w , x , y , z) = wy + xy + wxyz + w xy + xz + x y z

(a) B( A + C ) ( A + C ) (b) B( A + C ) ( A + C ) Which of the following is the complete set of

essential prime implicants?
(c) B( A + C ) ( A + C ) (d) B( A + C ) ( A + C )
(a) w, y , xz, x z (b) w, y, xz
[EC-2005 : 2 Marks]
(c) y , x y z (d) y , xz , x z
Q.10 The Boolean function Y = AB + CD to be realized
using only 2-input NAND gates. The minimum [EC-2014 : 2 Marks]
number of gates required is Q.16 For an n-variables Boolean function, the
(a) 2 (b) 3 maximum number of prime implicants is
(c) 4 (d) 5
n
[EC-2007 : 1 Mark] (a) 2(n – 1) (b)
2
Q.11 The Boolean expression: (c) 2n (d) 2(n – 1)
Y = ABCD + ABCD + ABCD + ABCD [EC-2014 : 1 Mark]
can be minimized to Q.17 The Boolean expression:
(a) Y = ABCD + ABC + ACD
F( X , Y , Z) = X Y Z + X Y Z + XY Z + XYZ
(b) Y = ABCD + BCD + ABCD
converted into Canonical Product of Sum (POS)
(c) Y = ABCD + BCD + ABCD form is
(d) Y = ABCD + BCD + ABCD
(a) (X + Y + Z) (X + Y + Z) ( X + Y + Z) ( X + Y + Z)
[EC-2007 : 2 Marks]
(b) (X + Y + Z) (X + Y + Z) ( X + Y + Z) ( X + Y + Z)
Q.12 If X = 1 in the logic equation,
[ X + Z {Y + (Z + XY }] { X + Z( X + Y )} = 1, then (c) (X + Y + Z) (X + Y + Z) ( X + Y + Z) ( X + Y + Z)

(a) Y = Z (b) Y = Z (d) (X + Y + Z) (X + Y + Z) ( X + Y + Z) ( X + Y + Z)

(c) Z = 1 (d) Z = 0 [EC-2015 : 2 Marks]
[EC-2009 : 2 Marks]
Q.18 A function of Boolean variables, X, Y and Z is
Q.13 In the sum of products function f (X, Y, Z) = expressed in terms of the min-terms as:
(2, 3 , 4, 5), the prime implicants are F(X, Y, Z) = (1, 2, 5, 6, 7)
(a) XY , XY Which one of the product of sums given below
is equal to the function F(X, Y, Z)?
(b) XY , XYZ, XYZ
(a) ( X + Y + Z ) ( X + Y + Z) ( X + Y + Z)
(c) XYZ, XYZ , XY
(d) XYZ , XYZ, XYZ, XYZ (b) ( X + Y + Z ) ( X + Y + Z) ( X + Y + Z)
[EC-2012 : 1 Mark]
 GATE Previous Years Solved Paper 7

(c) ( X + Y + Z ) ( X + Y + Z) ( X + Y + Z) (a) A B + A BC + A BC

(X + Y + Z) (X + Y + Z) (b) AC + A B + A BC
(c) AC + A B + A BC
(d) ( X + Y + Z ) ( X + Y + Z ) ( X + Y + Z )
(d) A BC + AC + A BC
(X + Y + Z) (X + Y + Z)
[EC-2017 : 2 Marks]
[EC-2015 : 2 Marks]
Q.21 A function F(A, B, C) defined by three Boolean
Q.19 Following is the K-map of a Boolean function of variables A, B and C when expressed as sum of
5 variables P, Q, R, S and X. The minimum sum products is given by
of product (SOP) expression for the function is
F= A B C+A B C+A B C
PQ
RS 00 01 11 10 where, AB and C are the complements of the
00 0 0 0 0 respective variables. The product of sums (POS)
form of the function F is
01 1 0 0 1
(a) F = ( A + B + C ) ( A + B + C ) ( A + B + C )
11 1 0 0 1
(b) F = ( A + B + C ) ( A + B + C ) ( A + B + C )
10 1 0 0 1 (c) F = ( A + B + C ) ( A + B + C ) ( A + B + C )
X=0
( A + B + C) (A + B + C)

PQ (d) F = ( A + B + C ) ( A + B + C ) ( A + B + C )
RS 00 01 11 10
(A + B + C) (A + B + C)
00 0 1 1 0
[EC-2018 : 1 Mark]
01 0 0 0 0
ELECTRICAL EN GINEERIN G
11 0 0 0 0
(GATE Previous Years Solved Papers)
10 0 1 1 0

X=1 Q.1 The logic function, f = ( x y ) + ( x y ) is the

same as,
(a) PQ S X + PQS X + Q RS X + Q RS X
(a) f = (x + y ) (x + y )
(b) Q S X + QS X (b) f = (x + y ) ( x + y )
(c) Q S X + QS X (c) f = ( x y ) (x y )
(d) Q S + QS (d) none of the above

[EC-2016 : 2 Marks] [EE-1992 : 2 Marks]

Q.20 Which one of the following gives the simplified Q.2 The minimal product of sums function
sum of products expression for the Boolean described by the K-map given in figure, is
AB
function, F = m0 + m2 + m3 + m5, where m0, m2, m3 00 01 11 10
C
and m5 are minterms corresponding to the
0 1 1 0 0
inputs A, B and C with A as the MSB and C as
the LSB? 1 0 0 0 0
 8 Electronics Engineering Digital Electronics

(a) A C (b) A + C
(c) X
(c) A + C (d) AC
F
[EE-2000 : 2 Marks] Y
Z
Q.3 The Boolean expression:
X Y Z + X Y Z + X Y Z + X Y Z + XYZ (d) X
F
can be simplified to Y
Z
(a) XZ + XZ + YZ (b) XY + YZ + YZ

(c) XY + YZ + XZ (d) XY + YZ + XZ [EE-2010 : 2 Marks]

[EE-2003 : 2 Marks] Q.7 In the sum of products function:

f(X, Y, Z) = (2, 3, 4, 5)
Q.4 The simplified form of the Boolean expression
The prime implicants are
Y = ( ABC + D) ( AD + BC ) can be written as,
(a) X Y + X Y
(a) AD + BCD (b) AD + BCD (b) X Y + X Y Z + X Y Z

(c) ( A + D) ( BC + D) (d) AD + BCD (c) X Y Z + X Y Z + X Y

[EE-2004 : 2 Marks] (d) X Y Z + X Y Z + X Y Z + X Y Z
Statement for Linked Answer Questions (5 and 6): [EE-2012 : 1 Mark]
The following Karnaugh map represents a function F. Q.8 Which of the following is an invalid state in
F YZ 8-4-2-1 binary code decimal counter?
00 01 11 10
(a) 1 0 0 0 (b) 1 0 0 1
0 1 1 1 0 (c) 0 0 1 1 (d) 1 1 0 0
X
[EE-2014 : 1 Mark]
1 0 0 1 0
Q.9 The SOP (Sum of Products) form of a Boolean
function is (0, 1, 3, 7, 11), where inputs are A,
Q.5 A minimized form of the function F is
B, C, D(A is MSB and D is LSB). The equivalent
(a) F = X Y + YZ (b) F = X Y + YZ minimized expression of the function is

(c) F = X Y + Y Z (d) F = X Y + Y Z (a) ( B + C ) ( A + C ) ( A + B) (C + D)

[EE-2010 : 2 Marks] (b) ( B + C ) ( A + C ) ( A + C ) (C + D)

Q.6 Which of the following circuits is a realization
(c) ( B + C ) ( A + C ) ( A + C ) (C + D)
of the above function F ?
(d) ( B + C ) ( A + B) ( A + B) (C + D)
(a) X
[EE-2014 : 2 Marks]
F
Y
Z Q.10 f(A, B, C, D) = M(0, 1, 3, 4, 5, 7, 9, 11, 12, 13, 14, 15)
is a maxterm representation of Boolean function
(b) X
f(A, B, C, D) where A is the MSB and D is the
F LSB. The equivalent minimized representation
Y
Z of this function is
 GATE Previous Years Solved Paper 9

Q.15 The output expression for the Karnaugh map

(a) ( A + C + D) ( A + B + D)
shown below is
(b) AC D + A BD CD
AB 00 01 11 10
(c) ACD + ABCD + ABCD
00 0 0 0 0
(d) ( B + C + D) ( A + B + C + D) ( A + B + C + D)
01 1 0 0 1
[EE-2015 : 2 Marks]
11 1 0 1 1
Q.11 Consider the following sum of products
expression, F : 10 0 0 0 0

F = ABC + A BC + A BC + A BC + A BC
(a) BD + BCD (b) BD + AB
The equivalent product of sums expression is
(c) BD + ABC (d) BD + ABC
(a) F = ( A + B + C ) ( A + B + C ) ( A + B + C )
[EE-2017 : 2 Marks]
(b) F = ( A + B + C ) ( A + B + C ) ( A + B + C )
Q.16 Digital input signals A, B, C with A as the MSB
(c) F = ( A + B + C ) ( A + B + C ) ( A + B + C )
and C as the LSB are used to realize the Boolean
(d) F = ( A + B + C ) ( A + B + C ) ( A + B + C ) function F = m0 + m2 + m3 + m5 + m7, where mi
[EE-2015 : 1 Mark] denotes the Ith minterm. In addition, F has a
don’t care for m1. The simplified expression for
Q.12 The output expression for the Karnaugh map
F is given by
shown below is
BC (a) AC + BC + AC (b) A + C
A 00 01 11 10
(c) C + A (d) AC + BC + AC
0 1 0 0 1
[EE-2018 : 2 Marks]
1 1 1 1 1
Q.17 The output expression for the Karnaugh map
shown below is
(a) A + B (b) A + C
PQ
(c) A + C (d) A + C RS 00 01 11 10
[EE-2016 : 1 Mark] 00 0 1 1 0

Q.13 The Boolean expression: 01 1 1 1 1

( a + b + c + d ) + (b + c )
11 1 1 1 1
simplifies is
10 0 0 0 0
(a) 1 (b) a b
(c) a, b (d) 0
(a) QR + S (b) QR + S
[EE-2016 : 2 Marks]
(c) QR + S (d) QR + S
Q.14 The Boolean expression, AB + AC + BC
simplifies to [EE-2019 : 2 Marks]

(a) BC + AC (b) AB + AC + B
(c) AB + AC (d) AB + BC
[EE-2017 : 1 Mark]
10 Electronics Engineering Digital Electronics

Electronics & Electrical Engineering

GATE Previous Years Solved Paper

A n swe rs & Expl a n a t i o n s

Answers
EC Boolean Algebra

1. (b) 2. (c) 3. (a) 4. (d) 5. (a) 6. (d) 7. (a) 8. (d)

9. (a) 10. (b) 11. (d) 12. (d) 13. (a) 14. (a) 15. (d) 16. (d)

17. (a) 18. (b) 19. (b) 20. (b) 21. (c)

Solutions
EC Boolean Algebra

1. (b) 5. (a)
n Y = A BC + A BC + A BC + A BC
Boolean functions possible are 2 2 .
= AC ( B + B) + A BC + A BC
2. (c)
The condition for overflow to occur is = A (C + BC ) + A BC

x y z + x y z. = A (C + C ) (C + B) + A BC

= AC + A B + A BC
3. (a)
= AC + B ( A + AC )
AB
00 01 11 10 = AC + B ( A + A) ( A + C )
CD
00 1 1 1 = AC + A B + BC

01 1 6. (d)
n 4
11 1 22 = 2 2 = 2 16 = 65536
10 1 1 7. (a)

RS
Number of essential prime implicants = 4. 1. W = PQ 00 01 10 11

00 1 1 1
4. (d)
01 1 1 1 1
y = A + AB
11 1 1 1
= ( A + A) ( A + B) 10 1 1 1
= A+B
W = R + PQ + RS
 GATE Previous Years Solved Paper 11

9. (a)
2. X= RS
PQ 00 01 11 10
f = A BC + A BC
00 1
= B ( AC + AC )
01 = B( A + C) ( A + C)
11 1
10. (b)
10 1 y = AB + CD = A B + C D
A
We can see that, X = B
AB + CD
RS
3. Y= 00 01 11 10
PQ
C
00 1 D

01 1 1 1 1 11. (d)
11 1 1 1 K-map corresponding to given Boolean
expression,
10 1
CD
AB 00 01 11 10
RS 00 1
4. Z= 00 01 11 10
PQ
00 1 1 1 01 1

11 1
01 1 1 1 1
10 1
11 1 1 1

10 1 1 1 Simplified expression from the K-map,

Y = A BC D + A BC D + BC D
K-map(1) = K-map(4)
W=Z 12. (d)
From map (2) and (4),
[ X + Z {Y + (Z + XY )}] [ X + Z( X + Y )] = 1
X= Z
Since, X = 1 so we get
8. (d) Z (1 + Y ) = 1

AC + BC Z =1
Writing the SOP form of the above expression Z=0
and filling the K-map, we get, 13. (a)
BC
00 01 11 10 f (X, Y, Z) = (2, 3, 4, 5)
A
YZ YZ YZ YZ
0 1
X 1 1
1 1 1 1
X 1 1
Now, comparing it which the expression given
in the question, we find option (d) satisfies the f (X, Y, Z) = X Y + X Y
given condition. So, prime implicants are X Y and X Y .
12 Electronics Engineering Digital Electronics

14. (a) 19. (b)

Let, F = (X + Y ) (X + Y ) + (X Y + X ) PQ
RS
F = X + X Y + XY + ( X Y X )
= X + (X + Y ) X 1 1
= X + XY
1 1
=X

15. (d)
X=0
f ( w , x , y , z ) = wy + xy + w xyz + w x y + xz + x y z QSX

PQ
f (wxyz)
RS
yz yz yz yz
1 1
wx 1 1 1 1

wx 1 1 1 1

wx 1 1 1
1 1

wx 1 1 1 X=1
QSX

minimum sum of product expression of the

y , xz , x z
function is
From the above K-map, it can be seen that, the
set of essential prime-implicants is = Q S X + QS X

y , xz , x z 20. (b)

16. (d) Given Boolean function is,

F = m0 + m2 + m3 + m5
For a variable Boolean function the maximum
It can be minimized by using K-map as given
number of prime implicants is 2(n – 1).
below.
17. (a) BC
A BC BC BC BC
F(X, Y, Z) = X Y Z + X YZ + XY Z + XYZ 0 1 3 2
A 1 1 1 AB
YZ AC
00 01 11 10 4 5 7 6
X A 1
0 0 0 0 1
ABC
1 1 1 0 1
F = AC + A B + A BC
F= ( X + Y + Z ) (X + Y + Z) ( X + Y + Z) (X + Y + Z)
21. (c)
18. (b)
F(A, B, C, D) = A BC + A BC + A BC
F(X, Y, Z) = (1, 2, 5, 6, 7)
= m(0, 2, 4) = M(1, 3, 5, 6, 7)
= [0, 3, 4]
= (A + B + C) (A + B + C) (A + B + C)
= ( X + Y + Z ) ( X + Y + Z) ( X + Y + Z)
( A + B + C) (A + B + C)
 GATE Previous Years Solved Paper 13

Answers
EE Boolean Algebra

1. (b) 2. (a) 3. (b) 4. (a) 5. (b) 6. (d) 7. (a) 8. (d)

9. (a) 10. (c) 11. (a) 12. (b) 13. (d) 14. (a) 15. (d) 16. (b)

17. (b)

Solutions
EE Boolean Algebra

1. (b) 5. (b)
Given, XY
f = ( x y ) + (x y ) = (x y ) (x y ) YZ
X 00 01 11 10
= ( x + y ) ( x + y ) = xy + x y
0 1 1 1 0
Option (b):
( x + y ) (x + y ) = ( x + y ) + (x + y ) 1 0 0 1 0

= xy + x y = f YZ

2. (a) F = XY +Y Z
AB
C 00 01 11 10 6. (d)
A From the figure it is clear that, two NAND gates
0 1 1 0 0
generate the X and Y and now two AND gates
1 0 0 0 0
with inputs X and Y and inputs Y and Z is
C used to generate two terms of SOP form and now
OR gate is used to sum them and generate the F.
3. (b)
By K-map: 7. (a)

XY f(X, Y, Z) = (2, 3, 4, 5)
Z 00 01 11 10
YZ
X 00 01 11 10
0 1 1
0 1 1 XY
1 1 1 1
1 1 1

The simplified form is XY + Y Z + Y Z .

XY
4. (a)
f(X, Y, Z) = X Y + X Y
Y = ( A BC + D) ( A D + BC )

= A BCD + AD + BC D 8. (d)
Binary coded decimal counter counts from 0 to 9.
= ( AD + BC D)
So, 1100 is an invalid state i.e. 12.
14 Electronics Engineering Digital Electronics

9. (a) = ( a + b + c + d ) (b + c )
The 4 variable Boolean function is given in
= a b c d b c
canonical sum of products form as, F=0
f (A, B, C, D) = (0, 1, 3, 7, 11)
As the options are given in the simplified 14. (a)
product of sums form, we first convert the given BC BC BC BC
function in canonical product of sums form, as
A 1
under: 0 1 3 2

f (A, B, C, D) = (2, 4, 5, 6, 8, 9, 10, 12, 13, 14, 15) A 1 1 1

4 5 7 6
Now by plotting the above function on a 4
variable K-map (maxterms map), we obtain the AC + BC
simplified expression of the function,
BC + AC
CD
AB C+D C+D C+D C+D 15. (d)
0 1 3 2
A+B 0 C+D CD CD CD CD
4 5 7 6
AB
A+B 0 0 0
B+C
12 13 15 14 AB 1 1
A+B 0 0 0 0 A+B
AB 1 1 1
8 9 11 10
A+C
A+B 0 0 0
AB

f = ( B + C ) ( A + C ) ( A + B) (C + D) ABC + BD

11. (a) 16. (b)

The SOP form of F is (shown in K-map), Given, f = m0 + m2 + m3 + m5 + m7
BC and m1 = don’t care
A 00 01 11 10
BC BC BC BC
0 1 1 1 0
A 1 X 1 1
1 0 1 1 0 0 1 3 2

A 1 1
So, POS form can be formed using ‘0’ from the 4 5 7 6

K-map. f = A +C
POS = ( A + B + C ) ( A + B + C ) ( A + B + C )
17. (b)
12. (b) PQ
RS 00 01 11 10
BC
A 00 01 11 10 00 0 1 1 0

0 1 0 0 1 01 1 1 1 1

1 1 1 1 1 11 1 1 1 1

10 0 0 0 0
F = A +C

13. (d) Output = QR + S

Option (b) is correct.
F = ( a + b + c + d ) + (b + c )
 3 Logic G ates

ELECTRO NICS EN GINEERIN G Q.5 For the logic circuit shown in figure, the output
is equal to
(GATE Previous Years Solved Papers)

Q.1 For the circuit shown below the output F is given

by A

X
B Y
F

(a) F = 1 (b) F = 0 (a) ABC (b) A + B + C

(c) F = X (d) F = X
(c) AB + BC + A + C (d) AB + BC
[EC-1988 : 1 Mark]
[EC-1993 : 1 Mark]
Q.2 Minimum number of 2-input NAND gates
Q.6 The output of a logic gate is ‘1’ when all its a
required to implement the function,
inputs are at logic ‘0’. The gate is either
F = ( X + Y ) (Z + W ) is (a) a NAND or an EX-OR gate
(a) 3 (b) 4 (b) a NOR or an EX-NOR gate
(c) 5 (d) 6 (c) an OR or an EX-NOR gate
[EC-1988 : 1 Mark] (d) an AND or an EX-OR gate
[EC-1994 : 1 Mark]
Q.3 Indicate which of the following logic gates can
be used to realized all possible combinational Q.7 A ring oscillator consisting of 5 inverters is
logic functions: running at a frequency of 1.0 MHz. The
(a) OR gates only propagation delay per gate is ______ n-sec.
(b) NAND gates only [EC-1994 : 1 Mark]
(c) EX-OR gates only
Q.8 The output of the circuit shown in figure is equal
(d) NOR gates only to
[EC-1989 : 1 Mark]
A
Q.4 Boolean expression for the output of XNOR B
(equivalence) logic gate with inputs A and B is
(a) A B + A B
A
(b) A B + A B B

(c) ( A + B) ( A + B) (a) 0 (b) 1

(d) ( A + B) ( A + B) (c) A B + A B (d) ( A B) (A B)
[EC-1993 : 1 Mark] [EC-1995 : 1 Mark]
 16 Electronics Engineering Digital Electronics

Q.9 The minimum number of NAND gates required

A
to implement the Boolean function B
A + A B + A BC is equal to
(a) zero (b) 1 X
C
(c) 4 (d) 7
[EC-1995 : 1 Mark]
(a) 1, 0, 1 (b) 0, 0, 1
Q.10 The output of the logic gate in figure is (c) 1, 1, 1 (d) 0, 1, 1
A [EC-2000 : 1 Mark]
F
Q.15 For the logic circuit shown in the figure, the
simplified Boolean expression for theoutput Y is
(a) 0 (b) 1
A
(c) A (d) A B

[EC-1997 : 1 Mark]
Y
Q.11 The Boolean function A + BC is a reduced form
of C

(a) AB + BC (b) (A + B) (A + C) (a) A + B + C (b) A

(c) A B + A BC (d) (A + C) B (c) B (d) C

[EC-1997 : 1 Mark] [EC-2000 : 2 Marks]

Q.12 The minimum number of 2-input NAND gates Q.16 In the figure, the LED
required to implement the Boolean function
VCC = 5 V
Z = ABC , assuming that A, B and C are
available, is 1k 1k 1k LED
(a) two (b) three
(c) five (d) six 1k

[EC-1998 : 1 Mark]
S1 S2
Q.13 For the identity AB + AC + BC = AB + AC , the
dual form is
(a) ( A + B) ( A + C ) ( B + C ) = ( A + B) ( A + C )
(a) emits light when both S1 and S2 are closed.
(b) ( A + B) ( A + C ) ( B + C ) = ( A + B) ( A + C ) (b) emits light when both S1 and S2 are open.
(c) emits light when only of S1 and S2 is closed.
(c) ( A + B) ( A + C ) ( B + C ) = ( A + B) ( A + C )
(d) does not emit light, irrespective of the switch
(d) A B + AC + BC = A B + AC positions.
[EC-1998 : 1 Mark] [EC-2001 : 2 Marks]

Q.14 For the logic circuit shown in the figure, the Q.17 If the input to the digital circuit (in the figure)
required input condition (A, B, C) to make the consisting of a cascade of 20 XOR-gates is X,
output (X) = 1 is then the output Y is equal to
 GATE Previous Years Solved Paper 17

1 Q.20 The number of product terms in the minimized

sum-of-product expression obtained through
Y
the following K-map is (where, “d” denotes
X don’t care states)
(a) 0 (b) 1
1 0 0 1
(c) X (d) X
0 d 0 0
[EC-2002 : 1 Mark]
0 0 d 1
Q.18 The gates G 1 and G 2 in the figure have
propagation delays of 10 n-sec and 20 n-sec 1 0 0 1
respectively. If the input Vi makes an abrupt
(a) 2 (b) 3
change from logic 0 to 1 at time t = t0, then the
output waveform Vo is (c) 4 (d) 5
[EC-2005 : 2 Marks]
G1
0 G2
Vo
Q.21 Which of the following Boolean expressions
1
1
correctly represents the relation between P, Q, R
vi vi
and M1?
0 Vi
t0
P
X
1 Q
Z
(a)
0 M1
t0 t1 t2 t3 Y

1 R
(b)
0 (a) M1 = (P OR Q) XOR R
t0 t1 t2 t3
(b) M2 = (P AND Q) XOR R
1 (c) M1 = (P NOR Q) XOR R
(c)
0 (d) M1 = (P XOR Q) XOR R
t0 t1 t2 t3
[EC-2008 : 2 Marks]
1
(d) Q.22 Match the logic gates in Column-A with their
0
t0 t1 t2 t3 equivalent in Column-B:
Column-A Column-B
[EC-2002 : 2 Marks]
P. 1.
Q.19 A Boolean function ‘f ’ of two variables x and y
is defined as follows:
Q. 2.
f(0, 0) = f(0, 1) = f(1, 1) = 1; f(1, 0) = 0
Assuming complements of x and y are not
R. 3.
available, a minimum cost solution of realizing
‘f ’ using only 2-input NOR gates and 2-input
S. 4.
OR gates (each having unit cost) would have a
total cost of (a) P-2, Q-4, R-1, S-3
(a) 1 unit (b) 4 unit (b) P-4, Q-2, R-1, S-3
(c) 3 unit (d) 2 unit (c) P-2, Q-4, R-3, S-1
[EC-2004 : 2 Marks] (d) P-4, Q-2, R-3, S-1 [EC-2010 : 1 Mark]
 18 Electronics Engineering Digital Electronics

Q.23 For the output ‘F ’ to be 1 is the logic circuit XOR

shown, the input combination should be X
Y
A AND
B F

F Z
XNOR
C
(a) F = X Y Z + X Y Z
(a) A = 1, B = 1, C = 0
(b) A = 1, B = 0, C = 0 (b) F = X Y Z + X Y Z

(c) A = 0, B = 1, C = 0 (c) F = X Y Z + X Y Z
(d) A = 0, B = 0, C = 1
(d) F = X Y Z + X Y Z
[EC-2010 : 1 Mark]
[EC-2014 : 2 Marks]
Q.24 The output Y in the circuit below is always ‘1’
when Q.27 In the circuit shown in the figure, if C = 0, the
expression for Y is
P
C
A
Q
Y B

Y
R
A
(a) two or more of the inputs P, Q, R are ‘0’. B

(b) two or more of the inputs P, Q, R are ‘1’.

(a) Y = AB + AB (b) Y = A + B
(c) any odd number of the inputs P, Q, R is ‘0’.
(c) Y = A + B (d) Y = AB
(d) any odd number of the inputs P, Q, R is ‘1’.
[EC-2014 : 1 Mark]
[EC-2011 : 1 Mark]
Q.28 A 3-input majority gate is defined by the logic
Q.25 A bulb in a stair case has two switches, one
function M(a, b, c) = ab + bc + ca. Which one of
switch being at the ground floor and the other
the following gate is represented by the function,
one at the first floor. The bulb can be turned-ON
and also can be turned-OFF by any one of the M ( M ( a, b , c ), M( a , b , c ), c ) ?
switches irrespective of the state of the other (a) 3-input NAND gate
switch. The logic of switching of the bulb
(b) 3-input XOR gate
resembles
(c) 3-input NOR gate
(a) an AND gate
(d) 3-input XNOR gate
(b) an OR gate
[EC-2015 : 2 Marks]
(c) an XOR gate
(d) a NAND gate Q.29 All the logic gates shown in the figure have a
[EC-2013 : 1 Mark] propagation delay of 20 ns. Let A = C = 0 and
B = 1 unit time t = 0. At t = 0, all the inputs flip
Q.26 The output F in the digital logic circuit shown (i.e. A = C = 1 and B = 0) and remain in that state.
in the figure is For t > 0, output Z = 1 for a duration (in ns) of
 GATE Previous Years Solved Paper 19

A Q.33 The minimum number of 2-input NAND gates

B Z required to implement a 2-input XOR gate is
C (a) 4 (b) 5
[EC-2015 : 2 Marks] (c) 6 (d) 7
[EC-2016 : 1 Mark]
Q.30 In the figure shown, the output Y is required to
Q.34 Consider a Boolean gate (D) where the output Y
be Y = AB + C D. The gates G1 and G2 must be
is related to the inputs A and B as, Y = A + B ,
A where + denotes logical OR operation. The
G1
B Boolean inputs ‘0’ and ‘1’ are also available
G2 Y
C
separately. Using instances of only D gates and
D inputs ‘0’ and ‘1’, ______ (select the correct
(a) NOR, OR (b) OR, NAND option(s)).
(c) NAND, OR (d) AND, NAND (a) NAND logic can be implemented
[EC-2015 : 1 Mark] (b) OR logic cannot be implemented
(c) NOR logic can be implemented
Q.31 A universal logic gate can implement any
(d) AND logic cannot be implemented
Boolean function by connecting sufficient
[EC-2022]
number of them appropriately. Three gates are
shown.
ELECTRICAL EN GINEERIN G
F1 = X + Y X F2 = X Y
X (GATE Previous Years Solved Papers)
Y Y
Gate 1 Gate 2
Q.1 The Boolean expression of the output of the
F3 = X + Y logic circuit shown in figure is
X
Y A
Gate 3
B
Which one of the following statements is true?
(a) Gate 1 is a universal gate. Y
(b) Gate 2 is a universal gate. C

(c) Gate 3 is a universal gate. (a) Y = A B + AB + C

(d) None of the gates shown is a universal gate.
(b) Y = A B + AB + C
[EC-2015 : 2 Marks]
(c) Y = A B + A B + C
Q.32 The output of the combinational circuit given
below is (d) Y = A B + A B + C

A [EE-1996 : 1 Mark]

Q.2 The output of a logic gate is “1” when all its

B
C inputs are at logic “0”. The gate is either
Y
(a) a NAND or an EX-OR gate
(b) a NOR or an EX-OR gate
(a) A + B + C (b) A(B + C) (c) an AND or an EX-NOR gate
(c) B(C + A) (d) C(A + B) (d) a NOR or an EX-NOR gate
[EC-2016 : 1 Mark] [EE-2001 : 1 Mark]
 20 Electronics Engineering Digital Electronics

Q.3 For the circuit shown in figure the Boolean Q.6 The output Y of the logic circuit given below is
expression for the output Y in terms of inputs P,
Y
Q, R and S.

P (a) 1 (b) 0
(c) x (d) x
Q [EE-2011 : 1 Mark]
Y Q.7 A bulb in a staircase has two switches, one
R
switch being at the ground floor and the other
one at the first floor. The bulb can be turned ON
S
and also can be turned OFF by one of the
switches irrespective of the state of the other
(a) P + Q + R + S (b) P + Q + R + S switch. The logic of switching of the bulb
resembles
(c) ( P + Q) + ( R + S ) (d) (P + Q) + (R + S) (a) and AND gate (b) an OR gate

[EE-2002 : 2 Marks] (c) an XOR gate (d) a NAND gate

[EE-2013 : 1 Mark]
Q.4 A, B, C and D are input, and Y is the output bit
in the XOR gate circuit of the figure below. Which Q.8 Which of the following logic circuits is a
of the following statements about the sum S of realization of the function F whose Karnaugh
A, B, C, D and Y is correct? map is shown in figure?
AB
A C 00 01 11 10
XOR
B 0 1 1

XOR Y
1 1 1
C
XOR
D
A
(a) S is always either zero or odd.
(a)
(b) S is always either zero or even.
B
(c) S = 1 only if the sum of A, B, C and D is C
even.
(d) S = 1 only if the sum of A, B, C and D is odd. A
[EE-2007 : 1 Mark]
(b)
Q.5 The complete set of only those logic gates B
designated as universal gates is C
(a) NOT, OR and AND gates
(b) XNOR, NOR and AND gates A
(c) NOR and NAND gates
(d) XOR, NOR and NAND gates (c) C

[EE-2009 : 1 Mark]
B
 GATE Previous Years Solved Paper 21

(a) Y = ABCD
A
C (b) Y = (A + B) (C + D)

(d) (c) Y = A + B + C + D
(d) Y = AB + CD

B
[EE-2018 : 1 Mark]

[EE-2014 : 2 Marks] Q.11 In the circuit shown below, X and Y are digital
inputs, and Z is a digital output. The equivalent
Q.9 For a 3 input logic circuit shown below, the
circuit is
output Z can be expressed as
P X

Y
Q Z
Z

(a) Q + R (b) PQ + R

(c) Q + R (d) P + Q + R
(a) XNOR gate (b) NOR gate
[EE-2017 : 1 Mark] (c) NAND gate (d) XOR gate
Q.10 In the logic circuit shown in the figure, Y is [EE-2019 : 2 Marks]
given by
A
B
Y
C
D

Electronics & Electrical Engineering

GATE Previous Years Solved Paper

A n swe rs & Expl a n a t i o n s

Answers
EC Logic G ates

1. (b) 2. (b) 3. (b, d) 4. (b, c) 5. (b) 6. (b) 7. (100) 8. (b)

9. (a) 10. (c) 11. (b) 12. (c) 13. (a) 14. (d) 15. ( ) 16. (d)

17. (b) 18. (b) 19. (d) 20. (a) 21. (d) 22. (d) 23. (d) 24. (b)

25. (c) 26. (a) 27. (a) 28. (b) 29. (40) 30. (a) 31. (c) 32. (c)

33. (a) 34. (a, c)

22 Electronics Engineering Digital Electronics

Solutions
EC Logic G ates

1. (b) 7. Sol.
Output of 1st EX-OR gate, 1
F1 = X X = 0 fclk =
2 Nt pdFF
nd
Output of 2 EX-OR gate,
F2 = X 0 = X 1 1
tpdFF = =
Output of 3rd EX-OR gate, 2 Ntclk 2 × 5 × 106
F = X X=0 = 100 nsec

2. (b) 8. (b)

W XY W Y = (A B) ( A B)
F = XYZ + XYW
= (X + Y) (Z + W) Y= A B A B
X XY
Y Y = (A A) ( B B)
XY Z
Y=0 0=1
Z
9. (a)
3. (b, d)
NAND and NOR gates can be used to realize F = A + A B + A BC
all possible combinational logic functions. = A (1 + B + BC ) = A
4. (b, c) So to implement A, zero NAND gates are
required.
A B + AB and ( A + B) ( A + B)
10. (c)
5. (b) F=A 0

A = A 0 + A 0 = A 1+0

F= A
A AB
11. (b)
AB + BC
B Y (A + B) (A + C) = A A + A C + A B + BC
= A + AC + AB + BC
C BC = A (1 + C + B) + BC
= A + BC

12. (c)
Y = A + AB + BC + C
A
Y = A + ( A + B) + ( B + C ) + C AC AC
C
Y = A+ B +C AC B ABC

6. (b)
B
B
NOR gate F = A + B = AB

EX-NOR gate F=A B = A B + AB

 GATE Previous Years Solved Paper 23

13. (a) 18. (b)

AND OR
OR AND
t0 t1 t2 t3 t4 t5
14. (d)
For X = 1
Output
A B=1 i.e. A = 0, B = 1
or NOR t0 t1 t2 t3
B C=1 i.e. B = 1, C = 1
Vo
15. ( )
t2 t3
A P
B
Z 19. (d)

X x y f y
x 0 1
Y 0 0 1
0 1 1 0 1 1
C D =x+y
1 0 0
1 1
Y = X+D 1 1 1

Y = X+D Since complements are not available.

y
D = (Z + C ) = ZC
f
X = (Z B ) = Z + B x
x

Y = Z + B + ZC 2 units.

Y = Z+B 20. (a)

Z = P B= P+B
Y = ( P + B) + B 1 0 0 1

P = AB 0 d 0 0
Y = P B+ B = B+ P
0 0 d 1
= B + AB = B + A + B = 1
Y=0 1 0 0 1

16. (d)
For LED to be ON, output of NAND gate = 0 21. (d)
No condition of S1 and S2 gives output of NAND M1 = [ PQ ( P + Q] R
gate zero. So LED will never glow.
= [( P + Q) ( P + Q] R
17. (b)
= (P Q) R
Output of 1st XOR gate = X
22. (d)
Output of 2nd XOR gate = X X
NOR gate is equivalent to INVERT – AND gate.
= (X ) X + X X = X + X = 1 NOR gate is equivalent to INVERT – OR gate.
Output of 20 XOR gates is 1.
24 Electronics Engineering Digital Electronics

X 26. (a)
R: Y F F = XY + XY
XOR
X X
3: F F = XY + XY Y
Y
A AND
F = XY + XY F
X
S: Y F F = XY + X Y
B
Z
X
1: Y F F = XY + XY XNOR

A=X Y
F = XY + X Y
B=A Z = A Z + AZ
23. (d) = Z (X Y ) + (X Y) Z
A X F = AB
B
= (X Y )[Z ( X Y ) + Z (X Y )]
Y
F = Z [( X Y ) (X Y ) + A (X Y ) (X Y )]

As we know,
C
A A=A
If, A = 0, B = 0 then
A A =0
X = AB+ AB = 0
= Z [(X Y) + 0]
Y = AB + A B = 1
= X YZ + X Y Z
F will be ‘1’ if even number of inputs to XNOR
gate is ‘1’, hence option (d) is the correct answer. 27. (a)
24. (b)
1
P PQ
C

PQ RQ PQ RQ A
PQ RQ PR 2
B
Q Y
RQ 3 6 Y

R PR A 5
4
B

Y = PQ + PR + RQ
Output of gate 1 : C
25. (c)
Output of gate 2 : ( A + B)
Truth table of XOR gate:
Output of gate 3 : (A + B + C)
A B Y
0 0 0 Output of gate 4 : AB
0 1 1 Output of gate 5 : ( A + B + C ) + AB
1 0 1
1 1 0 Output of gate 6 is output Y i.e.,

So, from the XOR gate truth table it is clear that Y = C ( A + B + C ) + AB

the bulb can be turned-ON and also can be
= C + ( A + B + C + AB)
turned-OFF by any one of the switches
irrespective of the state of the other switch.
 GATE Previous Years Solved Paper 25

Using Demorgon’s theorem

Y = AB + C D
= C + ( A + B) C ( AB)
G1 = NOR Gate A NOR B = AB
= C + ( A + B) C ( AB) G2 = OR Gate AB + C D
Given in question C = 0.
31. (c)
So, Y = 0 + ( A + B) 0 ( A + B)
Universal gate is a gate by which every other
= AB+ AB
gate can be realized.
28. (b) Gate 1 and Gate 2 are basic gates and can not be
used as universal gates.
M(a, b, c) = ab + bc + ca
M ( a , b , c ) = ab + bc + ca 32. (c)
y = ABC AB BC
= ab bc ca
= [ ABC AB + ABC AB] BC
= ( a + b ) (b + c ) ( c + a )
M ( a , b , c ) = ab + b c + c a = [( A + B + C ) AB + ABC ( A + B)] BC

= ( A BC ) ( BC )
M ( M ( a , b , c ), M( a, b , c ) c ) =
( ab bc ca ) ( ab + bc + ca ) + ( ab + bc + ca ) (c ) + ( ab bc ca ) c = ABC BC + ABC BC

F = ab c + b c a + c a b + abc = ( A + B + C ) BC + ABC ( B + C )
F=A B C = A BC + BC + ABC

29. Sol. = BC ( A + 1) + ABC = BC + ABC

= B (C + AC ) = B (C + A)
A
B Z
33. (a)
C

A
t=0
B x
f
y

B
20 ns

Y 34. (a, c)
40 ns
F(A, B) = A + B
C As ‘0’ and ‘1’ are available,
Z
20 ns 60 ns F(0, B) = A + B = 0 + B
= B (NOT)
Z is ‘1’ for 40 n-sec.
F( A + B) = A + B = A + B
30. (a)
F( A + B ) = A + B (OR)
A with the combination of OR and NOT, NOR gate
A
G1 can be implemented. Since NOR gate is
B
B
G2 Y universal logic gate, so all the functions can be
C CD implemented. So, correct option is (a, c).
D
26 Electronics Engineering Digital Electronics

Answers
EE Logic G ates

1. (a) 2. (d) 3. (b) 4. (b) 5. (c) 6. (a) 7. (c) 8. (c)

9. (c) 10. (d) 11. (d)

Solutions
EE Logic G ates

1. (a) 6. (a)

Y = (A B) C = A B+C x x y

= A B + C = AB + A B + C 1 0 1

2. (d) 0 1 1

A B Y
B
Y = x x+x x =1
0 0 1 A 0 1

0 1 X 0 1 1 7. (c)
1 0 X 1 1 Truth table XOR gate is,
1 1 X A B Y
0 0 0
Y = AB = A+ B NOR GATE 0 1 1
1 0 1
Y = AB + A B EX-NOR GATE
1 1 0

3. (b) So, from the XOR gate truth table it is clear that
the bulb can be turned ON and also can be
Y = (P Q) ( R S )
turned OFF by any one of the switches
Q ( A B ) = (A + B) irrespective of the state of the other switch.

Y = P Q+R S 8. (c)
AB
C 00 01 11 10
4. (b)
0 1 1
Y = A B C D from the given diagram. We
know that sum of any number of bits is XOR of
1 1 1
all bits.
So, S=A B C D Y
F = AC + BC
S=Y Y
So, option (c) is correct.
S = either zero even because LSB is zero (always)
9. (c)
5. (c)
P
NOR and NAND are designated as universal
logic gates because using any one of them we Q Z
can implement all the logic gates.
R
 GATE Previous Years Solved Paper 27

11. (d)
Z = PQ Q Q R = P Q + Q + Q R
The Boolean expression for the output of the
= PQ + Q + QR = Q ( P + 1) + QR digital circuit is shown below.
= Q + QR X

= (Q + Q) (Q + R) = Q + R Y

10. (d) Z = XY + XY

A AB
B
Y
The above expression is a XOR gate.
C
D CD

AB
Y = AB + CD
CD
 4 Combinational Circuits

ELECTRO NICS EN GINEERIN G Q.5 Without any additional circuitry, an 8 : 1 MUX

can be used to obtain
(GATE Previous Years Solved Papers)
(a) some but not all Boolean functions of
Q.1 The minimal function that can detect a 3 variables.
‘divisible by 3’ 8421 BCD code digit (b) all functions of 3 variables but none of
(representation is D7 D4 D2 D1) is given by 4 variables.
(a) D8 D1 + D4 D2 + D8 D2 D1 (c) all functions of 3 variables and some but
(b) D8 D1 + D4 D2 D1 + D4 D2 D1 + D8 D4 D2 D1 not all of 4 variables.
(c) D8 D1 + D4 D2 + D8 D4 D2 D1 (d) all functions of 4 variables.
(d) D4 D2 D1 + D4 D2 D1 + D8 D4 D2 D1 [EC-2003 : 1 Mark]

[EC-1990 : 1 Mark] Q.6 The circuit shown in the figure converts.

Inputs
Q.2 The logic realized by the circuit shown in figure
MBS
is

C I0
I1
4×1
I2 MUX F

C I3
S1 S 2

A B MBS
(a) F = A C (b) F = A C Output

(c) F = B C (d) F = B C (a) BCD to Binary code

[EC-1992 : 1 Mark] (b) Binary to Excess-3 code
Q.3 A 2-bit binary multiplier can be implemented (c) Excess-3 to Gray code
using (d) Gray to Binary code
(a) 2-input ANDs only [EC-2003 : 2 Marks]
(b) 2-input X-ORs and 4-input AND gates only
Q.7 The circuit shown in the figure has 4 boxes each
(c) Two (2) input NORs and one XNOR gate
described by inputs P, Q, R and outputs Y, Z
(d) XOR gates and shift registers
[EC-1997 : 1 Mark] with Y = P Q R, Z = R Q + P R + Q P .
Q
Q.4 For a binary half-subtractor having two inputs A
and B, the correct set of logical expressions for
the outputs D (= A minus B) and X(= borrow) are
P
(a) D = AB + A B, X = A B
P Q P Q P Q P Q
(b) D = A B + A B + A B , X = A B Z R Z R Z R Z R
Y Y Y Y
(c) D = A B + A B, X = A B
(d) D = A B + A B, X = A B Output
[EC-1999 : 2 Marks]
 GATE Previous Years Solved Paper 29

The circuit acts as a

P I3
(a) 4-bit adder giving P + Q.
P
(b) 4-bit adder giving P – Q. I2
Q 4-to-1
(c) 4-bit adder giving Q – P. Z
P I1 MUX
(d) 4-bit adder giving P + Q + R. P
I0
[EC-2003 : 2 Marks] Q

Q.8 The minimum number of 2-to-1 multiplexers

R S
required to realize a 4-to-1 multiplexer is
(a) 1 (b) 2 The output Z can be represented by
(c) 3 (d) 4 (a) PQ + PQ S + Q R S
[EC-2004 : 2 Marks] (b) PQ + PQ R + PQ S
Q.9 The Boolean function ‘f ’ implemented in the (c) PQ R + PQ R + PQRS + Q RS
figure using two input multiplexers is
(d) PQ R + PQ RS + PQ RS + Q RS
C 0 0 0
[EC-2008 : 2 Marks]
f
Statement for Linked Answer Questions (12 and 13):
C 1 A 1
Two products are sold from a vending machine, which
has two push buttons P1 and P2. When a button is
B E
pressed, the price of the corresponding product is
(a) A BC + A BC (b) ABC + A BC displayed in a 7-segment display.
If no buttons are pressed, ‘0’ is displayed,
(c) A BC + A BC (d) ABC + ABC
signifying ‘Rs. 0’.
[EC-2005 : 1 Mark] If only P1 is pressed, ‘2’ is displayed, signifying
Q.10 In the following circuit, X is given by ‘Rs. 2’.
If only P2 is pressed, ‘5’ is displayed, signifying
0 I0 0 I0 ‘Rs. 5’.
1 I1 1 I1 If both P1 and P2 are pressed, ‘E’ is displayed,
4-to-1 4-to-1
1 I2 MUX 1 I2 MUX X signifying ‘error’.
0 I3 0 I3 The names of the segments in the 7-segment display,
S1 S0 S1 S0 and the glow of the display for ‘0’, ‘2’, ‘5’, and ‘E’, are
shown below.
A B C
a 0 2 5 E
f g b
(a) X = A BC + A BC + A BC + ABC
e c
(b) X = A BC + A BC + A BC + A BC d

(c) X = AB + BC + AC Consider :

(d) X = A B + BC + AC (i) push button pressed/not pressed in

equivalent to logic 1/0 respectively.
[EC-2007 : 2 Marks]
(ii) a segment glowing/not glowing in the
Q.11 For the circuit shown in the following figure, display is equivalent to logic 1/0
I0 – I3 are inputs to the 4 : 1 multiplexer. R(MSB) respectively.
and S are control bits.
 30 Electronics Engineering Digital Electronics

Q.12 If segments a to ‘g’ are considered as functions

I0
of P1 and P2, then which of the following is
I1
correct? 4×1
I2 MUX Y F
(a) g = P1 + P2 , d = c + e
I3
(b) g = P1 + P2, d = c + e S1 S0

(c) g = P1 + P2 , e = b + c P Q
(d) g = P1 + P2, e = b + c (a) F = AND (P, Q) (b) F = OR (P, Q)
[EC-2009 : 2 Marks] (c) F = XNOR (P, Q) (d) F = XOR (P, Q)
Q.13 What are the minimum numbers of NOT gates [EC-2011 : 1 Mark]
and 2-input OR gates required to design the Q.17 The output Y of a 2-bit comparator is logic 1
logic of the driver for this 7-segment display? whenever the 2-bit input A is greater than the
(a) 3 NOT and 4 OR (b) 2 NOT and 4 OR 2-bit input B. The number of combination for
(c) 1 NOT and 3 OR (d) 2 NOT and 3 OR which the output is logic 1, is
[EC-2009 : 2 Marks] (a) 4 (b) 6
(c) 8 (d) 10
Q.14 What are the minimum number of 2-to-1 [EC-2012 : 1 Mark]
multiplexers required to generate a 2-input AND
gate and a 2-input EX-OR gate? Q.18 In a half-subtractor circuit with X and Y as
inputs, the Borrow (M) and Difference (N = X – Y)
(a) 1 and 2 (b) 1 and 3
are given by
(c) 1 and 1 (d) 2 and 2
(a) M = X Y, N = XY
[EC-2009 : 2 Marks]
(b) M = XY, N = X Y
Q.15 The Boolean function realized by the logic (c) M = X Y , N = X Y
circuit shown is
(d) M = X Y , N = X Y

C I0 [EC-2014 : 1 Mark]

D
I1
Q.19 Consider the multiplexer based logic circuit
4×1
F(A, B, C, D) shown in the figure.
I2 MUX
W 0
I3
S1 S0 MUX 0

1 MUX F
A B
1
S1
(a) F = m(0, 1, 3, 5, 9, 10, 14)
(b) F = m(2, 3, 5, 7, 8, 12, 13) S2

(c) F = m(1, 2, 4, 5, 11, 14, 15) Which one of the following Boolean functions
(d) F = m(2, 3, 5, 7, 8, 9, 12) is realized by the circuit?
[EC-2010 : 2 Marks] (a) F = W S1 S2
(b) F = WS1 + WS2 + S1S2
Q.16 The logic function implemented by the circuit
below is (ground implies a logic ‘0’) (c) F = W + S1 + S2
(d) F = W S1 S2 [EC-2014 : 1 Mark]
 GATE Previous Years Solved Paper 31

Q.20 If X and Y are inputs and the Difference

(d) X I0
(D = X – Y) and the Borrow (B) are the outputs,
2:1
which one of the following diagrams B
MUX
implements a half subtractor?
I1

(a) Y I0 S
Y
2:1 S
D
MUX X I0

I1 2:1
D
S MUX
X I1
S
Y I0
[EC-2014 : 2 Marks]
2:1
B
MUX Q.21 In the circuit shown, W and Y are MSBs of the
I1 control inputs. The output MSBs is given by
4 : 1 MUX 4 : 1 MUX
I0 I0

(b) X I0 I1 I1
2:1 V CC Q Q F
D I2 I2
MUX

I1 I3 I3
S
Y W X Y Z
S
(a) F = W X + W X + Y Z
X I0

2:1
(b) F = W X + W X + Y Z
B
MUX
(c) F = W X Y + W X Y
I1
(d) F = ( W + X ) Y Z [EC-2014 : 2 Marks]

Q.22 An 8-to-1 multiplexer is used to implement a

(c) Y I0
logical function Y as shown in the figure. The
output
2:1
B
MUX 0 I0

I1 D I1

S 0 I2
X D I3
S 0 I4 Y
Y I0 0 I5

2:1 1 I6
D
MUX 0 I7
S2 S1 S0
I1

A B C
 32 Electronics Engineering Digital Electronics

(a) Y = A BC + AC D Q.25 Identify the circuit below,

(b) Y = A BC + A B D O P0 IP0

X2 OP1 IP1 Y2
(c) Y = A BC + AC D
OP2 IP2

(d) Y = A B D + A BC X1
3:8 OP3 IP3 8:3
Y1
Decoder OP4 IP4 Decoder
[EC-2014 : 2 Marks] OP5 IP5
X0 OP6 IP6 Y0
Q.23 A 16-bit ripple carry adder is realized using 16
OP7 IP7
identical full adders (FA) as shown in the figure.
The carry-propagation delay of each FA is 12 ns (a) Binary to Gray code converter
and the sum-propagation delay of each FA is
(b) Binary to XS3 converter
15 ns. The worst case delay (in ns) of this 16-bit
(c) Gray to Binary converter
adder will be _______ .
(d) XS3 to Binary converter
A0 B0 A 1 B1 A14 B14 A 15 B15
[EC-2016 : 2 Marks]
C0 C1 C14 C15
FA0 FA1 FA14 FA 15 Q.26 A 4 : 1 multiplexer is to be used for generating
the output carry of a full adder. A and B are the
S0 S1 S14 S15 bits to be added while Cin is the input carry and
[EC-2014 : 2 Marks] Cout is the output carry. A and B are to be used
as the select bits with A being the more
Q.24 A 1-to-8 demultiplexer with data input Din,
significant select bit.
address inputs S0, S1, S2 (with S0 as the LSB)
I0
and Y0 to Y7 as the eight demultiplexed output,
I1
is to be designed using two 2-to-4 decoders (with 4:1
I2 Cout
MUX
enable input E and address inputs A0 and A1)
I3
as shown in the figure Din, S0, S1 and S2 are to be
S1 S0
connected to P, Q, R and S, but not necessarily
in this order. The respective input connections
A B
to P, Q, R and S terminals should be
Which one of the following statements correctly
P
1 Y0 Y0
describes the choice of signals to be connected
1E
Q to the inputs I0, I1, I2 and I3 so that the output is
2-to-4 1 Y
1 Y1
Decoder Cout?
R 1 A0 1 Y 2 Y2
(a) I0 = 0, I1 = Cin, I2 = Cin and I3 = 1
S 1 A1 1 Y3 Y3
(b) I0 = 1, I1 = Cin, I2 = Cin and I3 = 1
(c) I0 = Cin, I1 = 0, I2 = 1 and I3 = Cin
2E 2 Y0 Y4
2-to-4
(d) I0 = 0, I1 = Cin, I2 = 1 and I3 = Cin
2 Y1 Y5
Decoder [EC-2016 : 1 Mark]
2 A0 2 Y2 Y6

2 A1 2 Y3 Y7 Q.27 For the circuit shown in the figure, the delays of

NOR gates, multiplexers and inverters are 2 ns,
(a) S2, Din, S0, S1 (b) S1, Din, S0, S2 1.5 ns and 1 ns, respectively. If all the inputs P,
(c) Din, S0, S1, S2 (d) Din, S2, S0, S1 Q, R, S and T are applied at the same time instant,
the maximum propagation delay (in ns) of the
[EC-2015 : 2 Marks]
circuit is _______ .
 GATE Previous Years Solved Paper 33

P The Boolean function ‘F’ implemented is

(a) PQ R + PQ R + PQ R
Q
0 0
(b) ( P + Q + R ) ( P + Q + R ) ( P + Q + R )
R
MUX MUX Y (c) PQ R + PQ R + PQ R

S 1 1 (d) ( P + Q + R ) ( P + Q + R ) ( P + Q + R )
S0 S0
[EC-2017 : 2 Marks]
T
Q.30 Figure I shows a 4-bit ripple carry adder realized
[EC-2016 : 2 Marks]
using full adders and Figure II shows the circuit
Q.28 Consider the circuit shown in the figure. of a full-adder (FA). The propagation delay of
the XOR, AND and OR gates in Figure II are
Y 0 20 ns, 15 ns and 10 ns, respectively. Assume all
the inputs to the 4-bit adder are initially
MUX 0
reset to 0.
0 1 MUX F Y3 X3 Y2 X 2 Y1 X1 Y 0 X0

1
Z3 Z2 Z1 Z0
X Z4 FA FA FA FA

Z
S3 S2 S1 S0
The Boolean expression F implemented by the Fig. (I)

circuit is At t = 0, the inputs to the 4-bit adder are changed

(a) X Y Z + X Y + Y Z to X3 X2 X1 X0 = 1100, Y3 Y2 Y1 Y0 = 0100 and
Z0 = 1. The output of the ripple carry adder will
(b) X Y Z + X Z + Y Z
be stable at t (in ns) = _______ .
(c) X Y Z + X Y + Y Z Xn

(d) X Y Z + X Z + Y Z Yn Sn
[EC-2017 : 1 Mark]

Q.29 A Propagation Logic Array (PLA) is shown in

Zn + 1
the figure.

P P Q Q R R
Zn
Fig. (II)

[EC-2017 : 2 Marks]
F
Q.31 A 4-variable Boolean function is realized using
4 × 1 multiplexers as shown in the figure.

I0 I0 F(U, V, W, X)

P I1 I1
V CC 4×1 4×1
I2 MUX I2 MUX
Q
I3 I3
S1 S0 S1 S0

R
U V W X
 34 Electronics Engineering Digital Electronics

The minimized expression for F(U, V, W, X) is

A0 0
(a) (UV + UV ) W
A1 1

Input
(b) (UV + UV ) ( W X + W X )
A2 2 Output
(c) (UV + UV ) W A3 3 Select
S1 S0
(d) (UV + UV ) ( W X + W X )
[EC-2018 : 2 Marks] C D

Q.32 The figure below shows a mulitplexer where S1 (a) A0 = 0, A1 = 0, A2 = 1, A3 = 1

and S0 are the select lines. I0 to I3 are the input
(b) A0 = 1, A1 = 0, A2 = 1, A3 = 0
data lines, EN is the enable line, and F(P, Q, R)
(c) A0 = 0, A1 = 1, A2 = 1, A3 = 0
is the output. F is,
(d) A0 = 1, A1 = 1, A2 = 0, A3 = 0
0 EN
[EC-2022]
R I0
0 I1 MUX F ELECTRICAL EN GINEERIN G
R I2
1 I3 (GATE Previous Years Solved Papers)
S1 S0
Q.1 Match the following:
P Q Logic Function

(a) Q + PR (b) P + Q R A. X + Y P. Sum

B. XY Q. NAND
(c) PQ + Q R (d) PQ R + PQ
C. XY R. Carry
[EC-2020 : 1 Mark]
S. NOR
Q.33 The propagation delays of the XOR gate, AND [EE-1998 : 2 Marks]
gate and multiplexer (MUX) in the circuit shown
Q.2 The logic function F = AC + ABD + ACD is to be
in the figure are 4 ns, 2 ns and 1 ns, respectively.
realized using an 8 to 1 multiplexer shown in
P the figure, using A, C and D as control inputs.
0

Q 0
1
0 MUX Y 2
R MUX 1 3
4 MUX F
1 5
S S0 S0
6
T 7
D C A
If all the inputs P, Q, R, S and T are applied LSB
simultaneously and held constant, the
maximum propagation delay of the circuit is (a) Indicate the inputs to the applied at the
terminals 0 to 7.
(a) 6 ns (b) 3 ns
(b) Can be function be realize using a 4 to 1
(c) 7 ns (d) 5 ns
multiplexer?
[EC-2021 : 2 Marks]
[EE-1999 : 2 Marks]
Q.34 Consider the 2-bit multiplexer (MUX) shown in
Q.3 The output F of the 4-to-1 MUX shown in
the figure. For output to be the XOR of C and D,
figure is
the values for A0, A1, A2 and A3 are ______ .
 GATE Previous Years Solved Paper 35

(a) F(A, B, C) = (1, 2, 4, 6)

3
(b) F(A, B, C) = (1, 2, 6)
2
+5 V F
(c) F(A, B, C) = (2, 4, 5, 6)
MUX
1
(d) F(A, B, C) = (1, 5, 6) [EE-2006 : 2 Marks]
0
S1 S0 Q.6 A 3 line to 8 line decoder, with active low
outputs, is used to implement a 3-variable
X Y Boolean function as shown in the figure.

(a) xy + x (b) x + y 0
1
(c) x + y (d) xy + x 2
Z A0
[EE-2001 : 1 Mark] 3 F
Y A1
4
X A2
Q.4 Figure shows a 4 to 1 MUX to be used to 5
implement the sum S of a 1-bit full adder with 6
7
input bits P and Q and the carry input Cin. Which
of the following combinations of inputs to I0, I1, The simplified form of Boolean function
I2 and I3 of the MUX will realize the sum S ? F(X, Y, Z) implemented in ‘Product of Boolean’
form will be
I0 (a) ( X + Z ) ( X + Y + Z ) (Y + Z)
I1
4 to 1 (b) ( X + Z ) ( X + Y + Z ) (Y + Z)
F S
I2 MUX
(c) ( X + Y + Z) ( X + Y + Z ) ( X + Y + Z ) ( X + Y + Z )
I3
S1 S0 (d) ( X + Y + Z) ( X + Y + Z ) ( X + Y + Z ) ( X + Y + Z )
[EE-2008 : 2 Marks]

P Q Q.7 The output Y of a 2-bit comparator is logic 1

whenever the 2-bit input A is greater than the
(a) I0 = I1 = Cin ; I 2 = I 3 = Cin 2-bit input B. The number of combinations for
which the output is logic 1, is
(b) I0 = I1 = Cin ; I 2 = I 3 = Cin
(a) 4 (b) 6
(c) I0 = I 3 = Cin ; I1 = I 2 = Cin (c) 8 (d) 10
[EE-2012 : 1 Mark]
(d) I0 = I 3 = Cin ; I1 = I 2 = Cin
Q.8 A 3-bit gray counter is used to control the output
[EE-2003 : 1 Mark]
of the multiplexer as shown in the figure. The
Q.5 A (4 × 1) MUX is used to implement a 3-input initial state of the counter is 0002. The output is
Boolean function as shown in figure. The pulled high. The output of the circuit follows
Boolean function F(A, B, C) implemented is the sequence
A2 +5 V
A I0 3-bit gray A 1
counter A 0
I1 S0 S1 R
4 to 1 E
‘1’ I2 MUX F(A, B, C) 0
I0
‘0’ I3 1 4×1
S1 S0 I1 Output
2 MUX
I2
B C CLK 3
I3
 36 Electronics Engineering Digital Electronics

(a) I0, 1, 1, I1, I3, 1, 1, I2 Which one of the following options gives the
(b) I0, 1, I1, 1, I2, 1, I2, 1 correct inputs to pins 0, 1, 2, 3, 4, 5, 6, 7 in order?
(c) 1, I0, 1, I1, I2, 1, I3, 1 (a) D , 0, D, 0, 0, 0, D , D
(d) I0, I1, I2, I3, I0, I1, I2, I3 (b) D , 1, D, 1, 1, 1, D , D
[EE-2014 : 2 Marks]
(c) D , 1, D, 1, 1, 1, D , D
Q.9 In the 4 × 1 multiplexer, the output F is given by
(d) D , 0, D, 0, 0, 0, D , D
F = A B. Find the required input ‘I3, I2, I1, I0’.
[EE-2015 : 2 Marks]
I0
Q.11 Consider the following circuit which uses a
I1 2-to-1 multiplexer as shown in the figure below.
4×1
F The Boolean expression for output F in terms of
I2 MUX

I3 A and B is
S1 S0
0

A B Y F
(a) 1010 (b) 0110
S
(c) 1000 (d) 1110 1

[EE-2015 : 1 Mark]
A
B
Q.10 A Boolean function f(A, B, C, D) = (1, 5, 12, 15)
(a) A B (b) A + B
is to be implemented using an 8 × 1 multiplexer
(A is MSB). The input ABC are connected to the (c) A + B (d) A B
select input S 2 S 1 S 0 of the multiplexer [EE-2016 : 1 Mark]
respectively.

0
1
2
3
4
f (A , B, C, D)
5
6
7
S2 S1 S0

A B C
 GATE Previous Years Solved Paper 37

Electronics & Electrical Engineering

GATE Previous Years Solved Paper

A n swe rs & Expl a n a t i o n s

Answers
EC Combinational Circuits

1. (b) 2. (b) 3. (b) 4. (c) 5. (c) 6. (d) 7. (b) 8. (c)

9. (a) 10. (a) 11. (a) 12. (b) 13. (d) 14. (a) 15. (d) 16. (d)

17. (b) 18. (c) 19. (d) 20. (a) 21. (c) 22. (c) 23. (195) 24. (d)

25. ( ) 26. (a) 27. (6) 28. (b) 29. (c) 30. (50) 31. (c) 32. (c)

33. (a) 34. (c)

Solutions
EC Combinational Circuits

1. (b) 2. (b)
Truth table: F = A BC + A BC + A BC + ABC
D8 D4 D2 D1 Y
F = AC ( B + B) + AC ( B + B)
0 0 0 0 0 1
1 0 0 0 1 0 F = AC + AC = A C
2 0 0 1 0 0
3 0 0 1 1 1 3. (b)
4 0 1 0 0 0 Two bit binary multiplier,
5 0 1 0 1 0
Y0
6 0 1 1 0 1 X0
Y1
7 0 1 1 1 0 X1 Y0
8 1 0 0 0 0 Y1
9 1 0 0 1 1
K-map:
D8D4
C0
D2D1 00 01 11 10 H.A. H.A.

00 1 0 1 0
C3 C2 C1
01 0 0 0 1
X1 X0
11 X X 1 X
Y1 Y0
10 0 1 X X X1Y0 X0Y0

X1Y1 Y1X0
Y = D8 D1 + D4 D2 D1 + D4 D2 D1 + D8 D4 D2 D1
C3 C2 C1 C0
38 Electronics Engineering Digital Electronics

4. (c) E = BC + BC
A B D (Difference) X (Borrow) f = A BC + ABC
0 0 0 0
A B C f
0 1 1 1
1 0 1 1
1 0 1 0
1 1 0 1
1 1 0 0
D= A B = AB+ AB 10. (a)
X = AB Let the output of first MUX is Y.
So, Y = AB+ AB = A B
6. (d)
X = YC +YC = Y C
1 0 1 0
a b c d So, X=A B C
1 1
1
= A BC + A BC + A BC + ABC
1
0
0 1 1 1 11. (a)
1
1 0
1 Z = PRS + PQ RS + P RS + ( P + Q) R S
0
Mapping above terms in Karnaugh map
0 RS
w x y z 00 01 11 10
PQ
1 1 0 0
00 1
w=a
x =a b 01
y = c x(a + b)
11 1 1 1 1
z = d y(a + b + c)
By substituting given option in the Boolean 10 1 1 1

equations of two circuit. It shows Gray to binary

code converter. Z = PQ + PQ S + Q R S
The input = 1010 and output = 1100
12. (b)
The circuit is converting Gray code number to
Binary code number. P1 P2 a b c d e f g
0 0 1 1 1 1 1 1 0
7. (b)
0 1 1 0 1 1 0 1 1
Y = D=P Q R
1 0 1 1 0 1 1 0 1
Z = Borrow = RQ + P R + Q P 1 1 1 0 0 1 1 1 1

a=1
8. (c)
b = P2 ...1 (NOT)
4
No. of MUX = = 2 c = P1 ...1 (NOT)
2
2 d = 1=c+e
=1
2 e = P1 + P2 ...1 (OR)
Total = 2 + 1 = 3 f = P1 + P2 ...1 (OR)

9. (a) g = P1 + P2 ...1 (OR)

g = P1 + P2
f=E A
d = 1=c+e
 GATE Previous Years Solved Paper 39

13. (d) P Q F
2-NOT gates 0 0 0
3-OR gates 0 1 1

14. (a) 1 0 1
1 1 0
0 I0
F=P Q

B I1 17. (b)
Output will be 1 if A > B.
S=A • If B = 00 then there will be three
Y = S I0 + S1 I 1 combinations for which output will be 1 i.e.
when A = 01, 10 or 11.
= A 0 + AB
• If B = 01 there will be two conditions i.e.
= AB
A = 10 and 11.
AND gate
Similarly EXOR gate required 2 MUX to 2 × 1. • If B = 10 there will be one condition i.e.
A = 11.
15. (d) So, total 6 combinations are there for which
F(A, B, C, D) = ABC + ABD + ABC + AB (CD) output will be 1.

= ABC (D + D) + AB (C + C ) D 18. (c)

+ ABC (D + D) + ABCD X Y N=X–Y M

Placing above minterms in Karnaugh map, 0 0 0 0
0 1 1 1
CD
00 01 11 10 1 0 1 0
AB
00 1 1 1 1 0 0

N=X Y
01 1 1
M = XY
11 1

10 1 1 19. (d)

W 0
So, F = m(2, 3, 5, 7, 8, 9, 12)
X
MUX 0
16. (d)
1 MUX F
0 1 0
1 1
S1
1 4×1
F
MUX S2
0
Using the state equation of the multiplexer, we
S1 S0
get
P Q X = S1 W + S1 W
40 Electronics Engineering Digital Electronics

So, F = S2 X + S2 X A = W X I0 + W X I1 + W X I 2 + W X I 3

= S2 (S1 W + S1 W ) + S2 (S1 W + S1 W ) = W X+W X (Since, VCC = 1)

= S1S2 W + S1S2 W + S2 S1 W + S2 S1 W Now output,
F=W S1 S2 F = Y Z I0 + Y Z I1 + Y Z I2 + Y Z I 3

20. (a) = W XY Z + W XY Z + W XY Z + W XY Z
= W X Y (Z + Z) + W X Y (Z + Z )
X Y D B
0 0 0 0 = W XY + W XY
0 1 1 1
22. (c)
1 0 1 0
Depending upon the select lines one input is
1 1 0 0
transferred to the output in multiplexer,
Difference = X Y + X Y = X Y A B C Y
Borrow = X Y 0 0 0 0
0 0 1 D
Also using the state equation of MUX if X is
0 1 0 0
used as a select line and Y as input, we get 0 1 1 D
D = XY + XY 1 0 0 0
1 0 1 0
B = XY 1 1 0 1
Option (a) satisfies. 1 1 1 0

Y I0 Y = ABCD + ABCD + ABC

2:1
D
= ACD ( B + B) + ABC
MUX
= ACD + ABC
I1
S
23. Sol.
X
S Full adder is a combinational circuit that
Y I0 performs the sum of 3-bits i.e. add 2-bits and a
2:1 carry from previous addition and produces
B
MUX
output as sum and carry.
I1 Given carry propagation delay of each
FA = 12 nsec.
Sum-propagation delay of each FA = 15 nsec.
21. (c) A0 B0 A 1 B1 A14 B14 A 15 B15
4 : 1 MUX 4 : 1 MUX
C0 C1 C14 C15
I0 I0 FA0 FA1 FA14 FA 15
A
I1 I1
VCC Q Q F S0 S1 S14 S15
I2 I2
As can be seen from above diagram, full adder
I3 I3 is not received from previous full adder.
So, in 16-bit ripple carry adder, worst case delay
W X Y Z
of this 16-bit adder will be
For the state equation of 4 : 1 MUX, we know = (15 × 12) nsec + 15 nsec = 195 nsec
that,
 GATE Previous Years Solved Paper 41

24. (d) As per the truth table, none of the options given
Consider a 1 × 8 demultiplexer: in the question are correct. However, by making
some (minor) changes in the circuit, the answer
Y0 could be obtained as option (a).
Y0
Din De-MUX 26. (a)
Y0
In case of a full adder,
S0 S1 S2
Cout (A, B, Cin) = (3, 5, 6, 7)

Applied at
So, Y0 = ( Din S0 S1 S2 ) Applied at
select input data input
Y0 = ( Din + S0 + S1 + S2 ) of MUX
of MUX

Y1 = (Din + S0 + S1 + S2 ) I0 I1 I2 I3

Y2 = (Din + S0 + S1 + S2 ) Cin 0 2 4 6

Y3 = (Din + S0 + S1 + S2 ) Cin 1 3 5 7

Y4 = (Din + S0 + S1 + S2 ) 0 Cin Cin 1

Y5 = (Din + S0 + S1 + S2 ) I0 = 0 ; I1 = Cin
I2 = Cin ; I3 = 1
Y6 = (Din + S0 + S1 + S2 )
Y7 = (Din + S0 + S1 + S2 ) 27. Sol.
From the circuit given in question we can see When, T = logic 0, the path followed by the
that, circuit would be
NOR gate MUX 1 MUX 2
Y0 = (1 A0 + 1 A1 + E )
2 ns 1.5 1.5
Y0 = (R + S + P + Q)
5 ns
Similarly, When, T = logic 1, the path followed by the
Y1 = (1 A0 + 1 A1 + 1E) = ( P + Q + R + S ) circuit would be
Y4 = (2 A0 + 2 A1 + 2E ) = ( R + S + P + Q) NOR gate MUX 1 NOR gate MUX 2

So comparing, we get 1 ns 1.5 2 ns 1.5 ns

P = Din 6 ns

Q = S2 Maximum propagation delay is 6 ns.

R = S1 28. (b)
S = S0

25. ( ) Y 0
The truth table of the circuit is shown below:
MUX 0
X2 X1 X0 Y2 Y1 Y0
0 1 MUX F
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1 1
X
0 1 1 0 1 0
1 0 0 1 1 0
Z
1 0 1 1 1 1
1 1 0 1 0 0
1 1 1 1 0 1
42 Electronics Engineering Digital Electronics

F1 = X Y Output of the first multiplexer can be expressed

F = Z F1 + Z F1 as,
F1 = U V + U V
= ( XY ) Z + ( XY ) Z
Output of the second multiplexer can be
= X Y Z + (X + Y ) Z
expressed as,
F = X Y Z + XZ + Y Z
F = W X F1 + W X F1 = W F1
29. (c) = (UV + UV ) W
F = PQ R + PQ R + PQ R
32. (c)
30. Sol. QR
P 00 01 11 10
In this question inputs to be added are
0 0 1 0 0
X3 X2 X1 X0 = 1100
Y3 Y2 Y1 Y0 = 0100 and Z0 = 1 1 0 1 1 1
For this combination of addition, total minimum
delay depends on the addition of most Output, F = PQ R + PQ R + PQ
significant two bits (since least significant two
F = Q R + PQ
bits are zeros they does not cause any change in
Z1 and Z2). So, in the process of addition of given
33. (a)
two digits, waveforms at Z1 and Z2 become
tXOR = 4 ns, tAND = 2 ns, tMUX = 1 ns
stable at t = 0 itself.
Y3 X3 = 01 Y2 X2 = 11 Case (i): When T = 0
Propagation delay = tAND1 + tMUX2
= 2 + 1 = 3 ns
20 20

at t = 20 ns A (at t = 0) Case (ii): When T = 1

15 15
Z2 = 0
(at t = 0) Propagation delay = tAND2 + tMUX1
15 15
at at
+ tAND3 + tMUX2
20 20
B
(at t = 0)
t = 40 ns at t = 15 ns t = 15 ns = 2 + 1 + 2 + 1 = 6 ns
10 10
Hence maximum propagation delay of the
Z3
at t = 25 ns circuit is 6 ns.
Z4 S3 S2
at t = 50 ns at t = 45 ns at t = 20 ns 34. (c)
In this above diagram the waveform at A and B The output of MUX, F is
become stable at t = 0 itself, as the applied input
F = S1S0 I0 + S1S0 I 1 + S1S0 I 2 + S1S0 I 3
combinations does not cause any change.
So, for the given combination of inputs, output F = C DA0 + C DA1 + C DA2 + CDA3
will settle at t = 50 ns. But output,
31. (c) F= C D = CD + CD
I0 I0 Inputs of MUX are,
F1 F(U, V, W, X)
A0 = 0, A1 = 1, A2 = 1, A3 = 0
I1 I1
VCC 4×1 4×1
I2 MUX I2 MUX

I3 I3
S1 S0 S1 S0

U V W X
 GATE Previous Years Solved Paper 43

Answers
EE Combinational Circuits

2. (a) 3. (b) 4. (c) 5. (a) 6. (a) 7. (b) 8. (a) 9. (b)

10. (b) 11. (d)

Solutions
EE Combinational Circuits

1. Sol. 4. (c)
A Q, B R, C Q For a 4 : 1 MUX

2. Sol. I0
(a) F = AC + ABD + ACD I1
4×1
= ACB + ACB + ABDC + ABDC + ACDB F
I2 MUX

= ABCD + ABCD + ABCD + ABCD + ABCD I3

= ACD ( B + B) + ACD ( B + B) + ACDB

A B
= DCA ( B + B) + DCA ( B + B ) + DCA B
F = I0 A B + I1 AB + I 2 AB + I 3 AB
3rd line 7 th line 5th line
A B
Cn
= DCA (1) + DCA (1) + DC A ( B)

Full
0 0 adder
0 1
0 2
1 3 S=A B C
0 4 where sum of full adder is = A B C
B 5
Truth table of full adder:
0 6
S1(A) S0(B) Carry (Cin) Sum
1 7
D C A 0 0 0 0
I0 I0 = Cin
LSB 0 0 1 1
0 1 0 0
I1 I1 = Cin
0 1 1 1
(b) It can not be realized with a 4 to 1 1 0 0 0
I2 I2 = Cin
multiplexer as 5th and 7th lines are being 1 0 1 1
used. 1 1 0 0
I3 I3 = Cin
1 1 1 1
3. (b)
Q F = min(1, 2, 3)
5. (a)
F = x y + x y + xy
F(A, B, C) = A BC + A BC + BC
= x+xy = x+y
= (1, 2, 4, 6)
44 Electronics Engineering Digital Electronics

BC Similarly for
A 00 01 11 10
A2 A1 A0 S0 S1 E O/P
0 1 1 (A0)

0 0 0 0 0 0 I0
1 1 1
0 0 1 0 0 1 1
0 1 1 0 1 1 1
6. (a) 0 1 0 0 1 0 I1
Let us consider active high input, 1 1 0 1 1 0 I3
yz 1 1 1 1 1 1 1
x 00 01 11 10
1 0 1 1 0 1 1
0 0 1 1 0
1 0 0 1 0 0 I2
1 0 1 0 1

9. (b)
F = (1, 3, 5, 6) = M(0, 2, 4, 7)
F=A B, I3 I2 I1 I0
= (Y + Z) ( X + Z) ( X + Y + Z)
= AB + AB
7. (b) = ABI0 + ABI1 + ABI 2 + ABI 3
I0 = 0, I1 = 1, I2 = 1, I3 = 0
A B No. of cases I3 I2 I1 I0 = 0110
01 00 1
10. (b)
10 00, 01 2
Boolean function is f(A, B, C, D) = (1, 5, 12, 15)
11 00, 01, 10 3
implemented with 8 × 1 MUX,
Total = 6
I0 I1 I2 I3 I4 I5 I6 I7
D 0 2 4 6 8 10 12 14
8. (a)
D 1 3 5 7 9 11 13 15
For A2 A1 A0 S0 S1
( A1 ) ( A2 ) D 1 D 1 1 1 D D

0 0 0 0 0
11. (d)
MUX is enabled and output is I0
In the given multiplexer,
For A2 A1 A0 S0 S1
I0 = A, I 1 = A
0 0 0 0 0
Select = B
MUX is enabled and output is ‘1’.
F = BI 0 + BI 1
= B A + AB = A B
 5 Sequential Circuits

ELECTRO NICS EN GINEERIN G Q.3 A 4-bit modulo-16 ripple counter uses JK-flip-
flops. If the propagation delay of each FF is 50 ns,
(GATE Previous Years Solved Papers)
the maximum clock frequency that can be used
Q.1 Choose if correct statements relating to the circuit is equal to
of figure: (a) 20 MHz (b) 10 MHz
(c) 5 MHz (d) 4 MHz
+2 V –
+ P [EC-1990 : 1 Mark]

Vi
Q.4 The circuit given below is a
A
– Q
–1 V +

(a) For Vi = –2 V, P = 0
(b) For Vi = +3 V, P = 0
B Q
(c) For Vi = 0 V, P = 0 always
(d) For Vi = 0 V, P can be either 0 or 1 (a) J-K flip-flop (b) Johnson’s counter
[EC-1987 : 1 Mark] (c) R-S latch (d) None of above
Q.2 A ripple counter using negative edge-triggered [EC-1988 : 1 Mark]
D-flip-flops is shown in figure below. The flip- Q.5 The initial contents of the 4-bit serial-in-parallel-
flops are cleared to ‘0’ at the R input. The out, right-shift. Shift register shown in the figure
feedback logic is a to be designed to obtain the is 0110. After three clock pulses are applied, the
count sequence shown in the same figure. The contents of the shift register will be
correct feedback logic is
Clock
0 1 1 0
Serial in
D0 Q0 D1 Q1 D2
Q2
CLK C0 C1 C2
Q0 Q1 Q2
R R R

(a) 0000 (b) 0101

Feedback (c) 1010 (d) 1111
F logic
[EC-1992 : 1 Mark]
Count sequence in the order Q2 Q1 Q0:
000 001 010 011 100 101
Q.6 A pulse train with a frequency of 1 MHz is
counted using a modulo-1024 ripple-counter
built with J-K flip-flops. For proper operation of
(a) F = Q2 Q1 Q0 (b) F = Q2 Q1 Q0 the counter. The maximum permissible
propagation delay per flip-flop stage is ______
(c) F = Q2 Q1 Q0 (d) F = Q2 Q1 Q0
n-sec.
[EC-1987 : 1 Mark]
[EC-1993 : 1 Mark]
 46 Electronics Engineering Digital Electronics

Q.7 An R-S latch is (a) fixed at 0 and 1, respectively

(a) combinatorial circuit (b) x = 1010 ........ while y = 0101 .......
(b) synchronous sequential circuit (c) x = 1010 ........ and y = 1010 .......
(c) one bit memory element (d) fixed at 1 and 0, respectively
(d) one clock delay element [EC-1998 : 2 Marks]
[EC-1995 : 1 Mark]
Q.11 The ripple counter shown in the figure works
as a
Q.8 In a J-K flip-flop we have J = Q and K = 1
(see figure). Assuming the flip-flop was initially
cleared and then clocked for 6 pulses, the
sequence at the Q output will be Preset Preset Preset
J Q J Q J Q
A B C
J Q Q ‘1’ K Q ‘1’ K Q ‘1’ K Q
Clock
1 K Q
CLK (a) mod-3 up counter
(b) mod-5 up counter
(a) 010000 (b) 011001 (c) mod-3 down counter
(c) 010010 (d) 010101 (d) mod-3 down counter
[EC-1997 : 1 Mark] [EC-1999 : 2 Marks]
Q.9 Figure shows a mod-K counter, here K is equal to Q.12 A sequential circuit using D-flip-flop and logic
gates is shown in the figure, where X and Y are
the inputs and Z is the output. The circuit is

J0 Q0 J1 Q1

1 K0 Q0 1 K1 Q1 X
D Q Z
CLK CLK
Y Q Z
(a) 1 (b) 2
(c) 3 (d) 4
[EC-1998 : 1 Mark]

Q.10 In figure below, A = 1 and B = 1. The input B is

(a) S-R flip-flop with inputs X = R and Y = S.
now replaced by a sequence 101010...., the
(b) S-R flip-flop with inputs X = S and Y = R.
outputs x and y will be
(c) J-K flip-flop with inputs X = J and Y = K.
A X (d) J-K flip-flop with inputs X = K and Y = J.
[EC-2000 : 2 Marks]

Q.13 In the figure, the J and K inputs of all the four

flip-flops are made high . The frequency of the
B Y signal at output Y is
 GATE Previous Years Solved Paper 47

Q.16 A 0 to 6 counter consists of 3-flip-flops and a

J Q J Q J Q J Q
combination circuit of 2 input gate(s). The
CLK CLK CLK CLK
f = 10 kHz
K K K K combination circuit consists of
CLR CLR CLR CLR
(a) one AND gate
(b) on OR gate
(c) one AND gate one OR gate
(a) 0.833 kHz (b) 1.0 kHz (d) two AND gates
(c) 0.91 kHz (d) 0.77 kHz [EC-2003 : 1 Mark]
[EC-2000 : 2 Marks]
Q.17 A 4-bit ripple counter and a 4-bit synchronous
Q.14 For the ring oscillator shown in the figure, the counter are made using flip-flops having a
propagation delay of each inverter is propagation delay of 10 ns each. If the worst
100 pico-sec. What is the fundamental frequency case delay in the ripple counter and the
of the oscillator output? synchronous counter be R and S respectively,
then
Vo
(a) R = 10 ns, S = 40 ns
(b) R = 40 ns, S = 10 ns
(a) 10 MHz (b) 100 MHz (c) R = 10 ns, S = 30 ns
(c) 1 GHz (d) 2 GHz (d) R = 30 ns, S = 10 ns
[EC-2001 : 1 Mark] [EC-2003 : 2 Marks]

Q.15 The digital block in the figure is realized using Q.18 A master-slave flip-flop has the characteristic
two positive edge triggered D-flip-flops. Assume that
that for t < t0, Q1 = Q2 = 0. The circuit in the (a) change in the input immediately reflected
digital block is given by in the output.
(b) change in the output occurs when the state
X Digital Y
of the master is affected.
block
t0 t1 t2 t3
(c) change in the output occurs when the state
t0 t1 t2 t3 t4
of the slave is affected.
1 D1 Q1 1 D2 Q2 Y (d) both the master and the slave states are
(a)
X affected at the same time.
Q1 Q2 [EC-2004 : 1 Mark]

1 D1 Q1 1 D2 Q2 Y Q.19 Choose the correct one from among the

(b) alternatives A, B, C, D after matching an item
X
Q1 Q2 from Group-1 with the most appropriate item
in Group-2.
1 D1 Q1 D2 Q2 Y Group-1
(c)
X P. Shift register
Q1 Q2 Q. Counter
R. Decoder
1 D1 Q1 D2 Q2 Y Group-2
(d) X 1. Frequency division
Q1 Q2 2. Addressing in memory chips
3. Serial to parallel data conversion
[EC-2001 : 2 Marks]
 48 Electronics Engineering Digital Electronics

(a) P - 3, Q - 2, R - 1 (b) P - 3, Q - 1, R - 2
1 0 1 1 D Q A S
(c) P - 2, Q - 1, R - 3 (d) P - 1, Q - 2, R - 2
MSB LSB
[EC-2004 : 1 Mark] CLK Full
adder
Shift registers
Q.20 In the modulo-6 ripple counter shown in the
0 0 1 1 D Q B
figure, the output of the 2-input gate is used to
clear the J-K flip-flops. CLK Ci Co
1
Q D
C J B J A J
Clock CLK
C K B K A K input
Clock

2-input (a) S = 0 C0 = 0 (b) S = 0 C0 = 1

gate
(c) S = 1 C0 = 0 (d) S = 1 C0 = 1
The 2-input gate is [EC-2006 : 2 Marks]
(a) a NAND gate (b) a NOR gate
Q.24 Two D-flip-flops, as shown below, are to be
(c) an OR gate (d) an AND gate
connected as a synchronous counter that goes
[EC-2004 : 2 Marks]
through the following Q1Q0 sequence:
Q.21 The present output Q n of an edge 00 01 11 10 00 ....
trigered JK-flip-flop is logic 0. If J = 1, then Qn + 1 The inputs D0 and D1 respectively should be
(a) cannot be determined connected as:
(b) will be logic 0
D0 Q0 D1 Q1
(c) will be logic 1 LSB MSB
(d) will race around [EC-2005 : 2 Marks] CLK Q0 CLK Q1

Q.22 The given figure shows a ripple counter using Clock

positive edge triggered flip-flops.
1 1
(a) Q1 and Q0 (b) Q0 and Q1

1 T0 Q0 T1 Q1 T2 Q2 (c) Q1Q0 and Q1Q0 (d) Q1Q0 and Q1Q0

[EC-2006 : 2 Marks]
CLK Q0 Q1 Q2
Q.25 The following binary values were applied to the
If the present state of the counter is X and Y inputs of the NAND latch shown in
Q2 Q1 Q0 = 011, then its next state (Q2 Q1 Q0) the figure in the sequence in indicated below:
will be
X = 0, Y = 1; X = 0, Y = 0; X = 1, Y = 1
(a) 010 (b) 100
The corresponding stable P, Q outputs will be
(c) 111 (d) 101
[EC-2005 : 2 Marks] X
P
Q.23 For the circuit shown in the figure below, two
4-bit parallel-in serial-out shift registers loaded
with the data shown are used to feed the data to
a full adder. Initially, all the flip-flops are in Y Q
clear state. After applying two clock pulses, the
outputs of the full adder should be
 GATE Previous Years Solved Paper 49

(a) P = 1, Q = 0, P = 1, Q = 0, P = 1, Q = 0 or P = 0,
Q=1 1
(b) P = 1, Q = 0, P = 0, Q = 1 or P = 0, Q = 1 P = 0, (b) 0
Q=1 4T
t1 + 2 T
(c) P = 1, Q = 0, P = 1, Q = 1, P = 1, Q = 0 or P = 0,
Q=1
1
(d) P = 1, Q = 0, P = 1, Q = 1, P = 1, Q = 1
[EC-2007 : 2 Marks] (c)
0
2T
Q.26 For the circuit shown, the counter state (Q1Q0)
t1 + 2 T
follows the sequence:

1
(d) 0
D0 Q0 D1 Q1 4T
t1 + T

[EC-2008 : 2 Marks]
Clock
Q.28 For the circuit shown in the figure, D has a
(a) 00, 01, 10, 11, 00 ... transition from 0 to1 after CLK changes from
(b) 00, 01, 10, 00, 01 ... 1 to 0. Assume gate delays to be negligible.
(c) 00, 01, 11, 00, 01 ... 1
0 CLK
(d) 00, 10, 11, 00, 10 ...
1 D
[EC-2007 : 2 Marks] 0 Q

Q.27 For each of the positive edge-triggered J-K flip-

flop used in the following figure, the
propagation delay is T. Q

Q0 Q1
1 J0 1 J1 Which of the following statements is true?
CLK (a) Q goes to 1 at the CLK transition and stays
at 1.
1 K0 1 K1
(b) Q goes to 0 at the CLK transition and stays
at 0.
1 (c) Q goes to 1 at the CLK transition and goes
CLK to 0 when D goes to 1.
0 (d) Q goes to 0 at the CLK transition and goes
t
T to 1 when D goes to 1.
t1 [EC-2008 : 2 Marks]
Which of the following waveforms correctly
Q.29 Refer to the NAND and NOR latches shown in
represents the output at Q1?
the figure. The inputs (P1, P2) for both the latches
1
are first made (0, 1) and then, after a few seconds,
(a) made (1, 1). The corresponding stable outputs
0 (Q1, Q2) are
2T
t1 + T
 50 Electronics Engineering Digital Electronics

(a) 0010111... (b) 0001011...

P1
Q1
(c) 0101111... (d) 0110100...
[EC-2010 : 2 Marks]

Q.32 When the output Y in the circuit below is ‘1’, it

Q2
P2 implies that data has
P1
Q1
Y
Data D Q D Q

Clock
Q Q
Q2
P2
(a) changed from ‘0’ to ‘1’
(a) NAND : first (0, 1) then (0, 1) NOR : first
(1, 0) then (0, 0) (b) changed from ‘1’ to ‘0’

(b) NAND : first (1, 0) then (1, 0) NOR : first (c) changed in either direction
(1, 0) then (1, 0) (d) not changed
(c) NAND : first (1, 0) then (1, 0) NOR : first [EC-2011 : 1 Mark]
(1, 0) then (0, 0)
Q.33 Two D-flop-flops are connected as a
(d) NAND : first (1, 0) then (1, 1) NOR : first
synchronous counter that goes through the
(0, 1) then (0, 1)
following QB QA sequence 00 11 01 10
[EC-2009 : 2 Marks] 00 ...
Q.30 What are the counting states (Q1, Q2) for the The connections to the inputs DA and DB are
counter shown in the figure below? (a) DA = QB, DB = QA
Q1 Q2
(b) DA = QA , DB = QB
J1 Q1 J2 Q2
JK JK (c) DA = (QA QB + QA QB ), DB = QA
CLK
flip-flop flip-flop
K1 Q1 1 K2 Q2 (d) DA = (QA QB + QA QB ), DB = QB
[EC-2011 : 2 Marks]

(a) 11, 10, 00, 11, 10, ... Q.34 Consider the given circuit,
(b) 01, 10, 11, 00, 01, ...
A
(c) 00, 11, 01, 10, 00, ...
(d) 01, 10, 00, 01, 10, ...
[EC-2009 : 2 Marks] CLK

Q.31 Assuming that all flip-flops are in reset

B
conditions initially, the count sequence
observed at QA in the circuit shown is In this circuit, the race around
Output (a) does not occur
(b) occurs when CLK = 0
(c) occurs when CLK = 1 and A = B = 1
DA QA DB QB DC QC
(d) occurs when CLK = 1 and A = B = 0
QA QB QC
[EC-2012 : 1 Mark]
Clock
 GATE Previous Years Solved Paper 51

Q.35 The state transition diagram for the logic circuit

X1 D Q
shown in
CLK FF-1
2-1 MUX Q
D Q X1 Output (Y)

Y
CLK X2 D Q
Q X0
Select FF-2
Q
A
A=1 A=0
A=1 CLK
(a) Q=0 Q=1 X1

A=0 X2
A=0 A=0
A=1 W1

(b) Q=0 Q=1 W2

W3
A=1
A=0 A=1 W4
A=0
(a) W1 (b) W2
(c) Q=0 Q=1 (c) W3 (d) W4
[EC-2014 : 2 Marks]
A=1
A=1 A=1 Q.38 The outputs of the two flip-flops Q1, Q2 in the
A=0
figure shown are initialized to 0, 0. The sequence
(d) Q=0 Q=1 generated at Q1 upon application of clock signal
is
A=0
[EC-2012 : 2 Marks] Q1
J1 Q1 J2 Q2
Q.36 Five JK-flip-flops are cascaded to form the circuit
shown in figure. Clock pulses at a frequency of
a 1 MHz are applied as shown. The frequency K1 Q1 K2 Q2

(in kHz) of the waveform at Q3 is _____ .

CLK

(a) 01110... (b) 01010...

1 J4 Q4 1 J3 Q3 1 J2 Q2 1 J1 Q1 1 J0 Q0 (c) 00110... (d) 01100...
CLK CLK CLK CLK CLK [EC-2014 : 2 Marks]
1 K4 1 K3 1 K2 1 K1 1 K0
Q.39 The circuit shown in the figure is a
Clock
Q Q
[EC-2014 : 1 Mark]
D-Latch D-Latch
Q.37 In the circuit shown, choose the correct timing
En Q En Q
diagram of the output (Y) from the given
CLK
waveforms W1, W2, W3 and W4.
 52 Electronics Engineering Digital Electronics

(a) Toggle flip-flop Q.43 A 3-bit pseudo random number generator is

(b) JK flip-flop shown. Initially the value of output Y = Y2 Y1 Y0
(c) SR latch is set to 111. The value of output Y after three
(d) Master-slave D-flip-flop clock cycles is
[EC-2014 : 1 Mark] Y2 Y1 Y0

Q.40 A mod-n counter using a synchronous binary

up-counter with synchronous clear input is D2 Q2 D1 Q1 D0 Q0

shown in the figure. The value of n is _____ .

QA QA
CLK
QB QB
CLK
4-bit binary (a) 000 (b) 001
counter QC QC
QD QD
(c) 010 (d) 100
CLEAR
[EC-2015 : 2 Marks]

Q.44 Assume that all the digital gates in the circuit

[EC-2015 : 1 Mark] shown in the figure are ideal, the resistor
R = 10 k and the supply voltage is 5 V. The
Q.41 The figure shows a binary counter with
D-flip-flops D1, D2, D3, D4 and D5 are initialized
synchronous clear input. With the decoding
with logic values 0, 1, 0, 1 and 0, respectively.
logic shown, the counter works as a
The clock has a 30% duty cycle.
Q3
Q2
Binary
Clock D Q D Q D Q D Q D Q
counter Q 1
Q0 D1 D2 D3 D4 D5
CLR
CLK R = 10 k

The average power dissipated (in mW) in the

resistor R is ______ .
(a) mod-2 counter (b) mod-4 counter
[EC-2016 : 1 Mark]
(c) mod-5 counter (d) mod-6 counter
[EC-2015 : 2 Marks] Q.45 For the circuit shown in the figure, the delay of
the bubbled NAND gate is 2 ns and that of the
Q.42 The circuit shown consists of JK flip-flops, each counter is assumed to be zero.
with an active low asynchronous reset Q0 (LSB)

( Rd input). The counter corresponding to this

3-bit Q1
circuit is synchronous
Q0 Q1 Q2 counter
1 J Q 1 J Q 1 J Q
CLK Q 2 (MSB)
Clock Reset
1 K R 1 K R 1 K R
d d d

(a) a modulo-5 binary up counter. If the clock (CLK) frequency is 1 GHz, then the
(b) a modulo-6 binary down counter. counter behaves as a
(c) a modulo-5 binary down counter. (a) mod-5 counter (b) mod-6 counter
(d) a modulo-6 binary up counter. (c) mod-7 counter (d) mod-8 counter
[EC-2015 : 1 Mark] [EC-2016 : 2 Marks]
 GATE Previous Years Solved Paper 53

Q.46 In the latch circuit shown, the NAND gates have

non-zero, but unequal propagation delays. The
present input conditions is, P = Q = ‘0’. If the
input condition is changed simultaneously to Din A B C D
P = Q = ‘1’, the outputs X and Y are Clock

P [EC-2017 : 2 Marks]
X
Q.49 In the circuit shown, the clock frequency, i.e.,
the frequency of the clock signal, is 12 kHz. The
frequency of the signal at Q2 is _____ kHz.
Q Y

D1 Q1 D2 Q2
(a) X = ‘1’, Y = ‘1’
CLK CLK
(b) either X = ‘1’, Y = ‘0’ or X = ‘0’, Y = ‘1’
Q1 Q2
(c) either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘0’
12 kHz
(d) X = ‘0’, Y = ‘0’
[EC-2017 : 1 Mark] [EC-2019 : 1 Mark]

Q.47 Consider the D-latch shown in the figure, which Q.50 For the components in the sequential circuit
is transparent when its clock input CK is high shown below, tpd is the propagation delay, tsetup
and has zero propagation delay. In the figure, is the setup time, and thold is the hold time. The
the clock signal CLK1 has a 50% duty cycle and maximum clock frequency (rounded off to the
CLK2 is a one-fifth period delayed version of nearest integer), at which the given circuit can
CLK1. The duty cycle at the output of the latch operate reliably, is _____ MHz.
in percentage is ______ .
FF-1 tpd = 2 ns
tpd = 2 ns
TCLK tpd = 3 ns
tsetup = 5 ns
CLK thold = 3 ns
CLK 1

IN
CLK 2 FF-2
TCLK/5 tpd = 8 ns
tsetup = 4 ns
CLK 1 Output thold = 3 ns
D Q

D-Latch
[EC-2020 : 2 Marks]
CK
CLK 2 Q.51 The propagation delay of the exclusive-OR
(XOR) gate in the circuit in the figure is 3 ns.
[EC-2017 : 1 Mark]
The propagation delay of the flip-flops is
Q.48 A 4-bit shift register circuit configured for right- assumed to be zero. The clock (CLK) frequency
shift operation, i.e. Din A, A B, B C, provided to the circuit is 500 MHz.
C D, is shown. If the present state of the shift Q2 Q1
register is ABCD = 1101, the number of clock Q0
D2 D1 D0
cycles required to reach the state ABCD = 1111
is ______ .
CLK
 54 Electronics Engineering Digital Electronics

Starting from the initial value of the flip-flop ELECTRICAL EN GINEERIN G

outputs Q2Q1Q0 = 111 with D2 = 1, the minimum
(GATE Previous Years Solved Papers)
number of triggering clock edges after which
the flip-flop outputs Q2Q1Q0 becomes 1 0 0 Q.1 For a J-K flip-flop, J input is tied to its own Q
(in integer) is _______ .
output and its K input is connected to its own Q
[EC-2021 : 2 Marks]
output. It the flip-flop is fed with a clock of
Q.52 For the circuit shown, the clock frequency is fo frequency 1 MHz, its Q output frequency will
and the duty cycle is 25%. For the signal at the be _______ .
Q output of the flip-flop, ______ . [EE-1995 : 1 Mark]

2-bit binary Q.2 For a flip-flop formed two NAND gates as

counter Flip-flop shown in figure. The unusable state
LSB
J Q corresponds to
X
K Q
MSB

Clock

(a) frequency is fo/4 and duty cycle is 50%. Q

Y
(b) frequency is fo/4 and duty cycle is 25%. (a) X = 0, Y = 0 (b) X = 0, Y = 1
(c) frequency is fo/2 and duty cycle is 50%. (c) X = 1, Y = 0 (d) X = 1, Y =
(d) frequency is fo and duty cycle is 25%. [EE-1999 : 2 Marks]
[EC-2022]
Q.3 The frequency of the clock signal applied to the
Q.53 A state transition diagram with states A, B and rising edge triggered D flip-flops shown in figure
C and transition probabilities p1, p2, ....., p7 is is 10 kHz. The frequency of the signal available
shown in the figure (e.g. p 1 denotes the at Q is
probability of transition from state A to B). For
this state diagram, select the statement(s) which
D Q
is/are universally true.
p2

p1 CLK Q
B 10 kHz

(a) 10 kHz (b) 2.5 kHz

p3
p7 A (c) 20 kHz (d) 5 kHz
p4
[EE-2000 : 1 Mark]

p6 C p5 Q.4 The shift register shown in figure is initially

loaded with the bit pattern 1010. Subsequently
(a) p2 + p3 = p5 + p6 the shift register is clocked, and with each clock
(b) p1 + p3 = p4 + p6 pulse the pattern gets shifted by one bit position
(c) p1 + p4 + p7 = 1 to the right. When each shift, the bit at the serial
(d) p2 + p5 + p7 = 1 input is pushed to the left most position (MSB).
After how many clock pulses will the content of
[EC-2022]
the shift register become 1010 again?
 GATE Previous Years Solved Paper 55

Clock (a) 1010, 1010 (b) 0101, 0101

1 0 1 0
Serial (c) 0010, 0010 (d) 1010, 1011
Input [EE-2004 : 2 Marks]

Q.8 The digital circuit shown in figure generates a

modified clock pulse at the output. Choose the
(a) 3 (b) 7 correct output waveform from the options given
(c) 11 (d) 15 below.
[EE-2003 : 2 Marks]
PR = 1
Q.5 An X-Y flip-flop, whose characteristic table is
given below is to be implement using JK flip-flop. 1 J Q
Output
X Y Qn + 1 CLK
0 0 1 1 K Q
0 1 Qn
1 0 Qn CL = 1
1 1 0

This can be done by making CLK

(a) J = X , K = Y (b) J = X , K = Y

(c) J = Y , K = X (d) J = Y , K = X (a)

[EE-2003 : 2 Marks]
(b)
Q.6 The digital circuit using two inverters shown
in figure will act as:
(c)

(d)
(a) a bistable multi-vibrator
(b) a astable multi-vibrator [EE-2004 : 2 Marks]
(c) a monostable multi-vibrator
Q.9 The digital circuit shown in the figure works as
(d) an oscillator
[EE-2004 : 1 Mark]
D Q
Q.7 A digital circuit which compares two numbers X
A3 A2 A1 A0, B3 B2 B1 B0 is shown in figure. To get
output Y = 0, choose one pair of correct input CLK Q
numbers.
B3 A3 B 2 A2 B1 A 1 B0 A 0 (a) JK flip-flop (b) Clocked RS flip-flop
(c) T flip-flop (d) Ring counter
[EE-2005 : 1 Mark]

Q.10 Select the circuit which will produce the given

output Q for the input signals X1 and X2 given
in the figure.
Y
 56 Electronics Engineering Digital Electronics

X1 Q.12 A 2-bit counter circuit is shown below.

t
QA QB
X2 J Q J Q
t

Q t
K Q K Q

X2
Q
CLK

(a) If the state QAQB of the counter at the clock time

tn is “10” then the state QAQB of the counter at
tn + 3 (after three cycles) will be
X1
(a) 00 (b) 01
X1 (c) 10 (d) 11
Q
[EE-2011 : 2 Marks]
(b)
Q.13 Consider the given circuit:

X2 A

X1
Q
CLK
(c)

B
X2
In this circuit, the race around
X1
Q (a) does not occur

(d) (b) occurs when CLK = 0

(c) occurs when CLK = 1 and A = B = 1

X2
(d) occurs when CLK = 1 and A = B = 0
[EE-2012 : 1 Mark]
[EE-2005 : 2 Marks]
Q.14 The state transition diagram for the logic circuit
Q.11 In the figure, as long as X1 = 1 and X2 = 1, the
shown is
output Q remains
1 2-1 MUX
X1
Q D Q X1
X2
Y
CLK Q X0
Select
(a) at 1 A
(b) at 0 A=1 A=0
(c) at its initial value A=1
(d) unstable
(a) Q=0 Q=1
[EE-2005 : 2 Marks]
A=0
 GATE Previous Years Solved Paper 57

A=1 A=0
A=1

Q=0 Q=1 J Qn
(b) T
(b)
A=1 T flip-flop
K
A=0 A=1 CLK Qn
A=0

(c) Q=0 Q=1

A=1
A=0 A=1 J Qn
A=0 T
(c)
T flip-flop
(d) Q=0 Q=1 K
CLK Qn
A=0
[EE-2012 : 2 Marks]

Q.15 The clock frequency applied to the digital circuit

shown in figure below is 1 kHz. If the initial
J
state of the output Q of the flip-flop is ‘0’, then T Qn
the frequency of the output waveform Q (d) T flip-flop
(in kHz), is K Qn
CLK

X
T Q Q [EE-2014 : 2 Marks]
CLK Q Q Q.18 A state diagram of a logic which exhibits a delay
in the output is shown in the figure, where X is
(a) 0.25 (b) 0.5 the do not care condition, and Q is the output
(c) 1 (d) 2 representing the state.
[EE-2013 : 2 Marks] 0X/1, 10/1

Q.16 A cascade of three identical modulo-5 counters Q=0 Q=1

0X/1,
11/0
has an overall modulus of 10/1

(a) 5 (b) 25 11/0

(c) 125 (d) 625
The logic gate represented by the state diagram
[EE-2014 : 1 Mark] is
Q.17 A JK flip-flop can be implemented by T flip-flops. (a) XOR (b) OR
Identify the correct implementation. (c) AND (d) NAND
[EE-2014 : 1 Mark]

J Q.19 The figure shows a digital circuit constructed

T Qn using negative edge triggered J-K flip-flops.
(a)
CLK Assume a starting state of Q2 Q1 Q0 = 000 will
K Qn
T flip-flop repeat after ______ number of cycles of the clock
CLK.
 58 Electronics Engineering Digital Electronics

1 J0 Q0 J1 Q1 J2 Q2
D Q D Q D Q

CLK
Q Q Q
1 K0 Q0 1 K1 Q0 1 K2 Q2 (MSB) QA QB QC

Clock

Z
[EE-2015 : 2 Marks]
(MSB)
Q.20 In the following sequential circuit, the initial D Q
QA
D Q
QB
D Q
QC

state (before the first clock pulse) of the circuit is

Q1Q0 = 00. The state (Q1Q0), immediately after Q Q Q

the 333rd clock pulse is

Q0 Q1 The minimum number of clock cycles after

J0 Q0 J1 Q1 which the output Z would again become zero is
_______ . [EE-2017 : 2 Marks]

K0 Q0 K1 Q1 Q.23 Which of the following statements is true about

CLK the digital circuit shown in the figure?

(a) 00 (b) 01
D Q D Q D Q
(c) 10 (d) 11 fOUT
[EE-2015 : 2 Marks]
C C C
Q.21 The current state QAQB of a two JK flip-flop fIN
system is 00. Assume that the clock rise-time is (a) It can be used for dividing the input
much smaller than the delay of the JK flip-flop. frequency by 3.
The next state of the system is (b) It can be used for dividing the input
frequency by 5.
5V
(c) It can be used for dividing the input
J QA J QB frequency by 7.
(c) It can not be reliably used as a frequency
QA divider due to disjoint internal cycles.
K K
[EE-2018 : 2 Marks]
CLK
Q.24 A sequence detector is designed to detect
(a) 00 (b) 01
precisely 3 digital inputs, with overlapping
(c) 11 (d) 10 sequences detectable. For the sequence (1, 0, 1)
[EE-2016 : 2 Marks] and input data (1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, 0),
what is the output of this detector?
Q.22 For the synchronous sequential circuit shown
(a) 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0
below, the output Z is zero for the initial
(b) 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0
conditions, Q A QB QC = QA QB QC = 100. (c) 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0
(d) 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0
[EE-2020 : 1 Mark]
 GATE Previous Years Solved Paper 59

Electronics & Electrical Engineering

GATE Previous Years Solved Paper

A n swe rs & Expl a n a t i o n s

Answers
EC Sequential Circuits

1. (b) 2. (a) 3. (c) 4. (c) 5. (c) 6. (100) 7. (c) 8. (d)

9. (c) 10. (a) 11. (d) 12. (d) 13. (b) 14. (c) 15. (c) 16. (d)

17. (b) 18. (c) 19. (b) 20. (c) 21. (c) 22. (b) 23. (d) 24. (a)

25. (c) 26. (b) 27. (b) 28. (c) 29. (c) 30. (a) 31. (d) 32. (a)

33. (d) 34. (a) 35. (d) 36. (62.5) 37. (c) 38. (d) 39. (d) 40. (7)

41. (c) 42. (a) 43. (d) 44. (1.5) 45. (d) 46. (b) 47. (30) 48. (10)

49. (4) 50. (76.92) 51. (5) 52. (a) 53. (a, c)

Solutions
EC Sequential Circuits

1. (b) 4. (c)
For, Vi = +3 V, P = 0 1
fclk =
When, Vi = +3 V nt pd ff
Output of computer 1 = logic 1
1
Output of computer 2 = logic 0 = 9 2 4 = 16
4 × 50 × 10
P = 1 + (output of 2nd NOR gate) fclk = 5 MHz
P= 1 5. (c)
P=0
Clock
2. (a) 0 1 1 0
Serial in
D0 = Q0

D1 = Q1

D2 = Q 2 Serial in = D1 D0

So, flip-flop will be cleared at 0 1 1 0

st
1 1 0 1 clk 1 0 1 1
NAND
Q 2 Q1 Q0 2 nd clk 0 1 0 1

3. (c) 3rd clk 1 0 1 0

R-S latch.
60 Electronics Engineering Digital Electronics

6. Sol. 11. (d)

Ripple counter n-states Trick up/down CP Q, 1 for up and 0 for down.
n = log2 (1024) = 10 CP = (Clock pulse)
1 1 Q = (O/P)
tpd if = = = 100 n-sec
n f clk 10 × 106 0 = –ve edge, Q = 1

1 = +ve edge, Q = 1
7. (c)
An R-S latch is a 1-bit memory element. =1 1 = 0 (down counter)
Counter sequence
8. (d)
1 1 1
When, Q=0 Q=1 1 1 0
So, J = K=1 1 0 1
1 0 0
Qn + 1 = Qn = 1
0 1 1 (preset state) so mod-5
When, Q=1 Q=0
12. (d)
J = 0, K = 1
Qn + 1 = 0 D = X Z + Y Z, D = KQ+ JQ
So, the sequence at the Q output will be 010101.
Y = J, X = K, D = Q (for D-flip-flop)
9. (c)
13. (b)
Let initial, Q1 = Q0 = 0
Given counter is mod-10 up counter
J0 K0 J1 K1 Q1 Q0
10 k
0 0 Frequency of output = =1k
10
1 1 0 1 0 1
1 1 1 1 1 0 14. (c)
0 1 0 1 0 0
tpd of all 5 intervals
It is a mod-3 counter. = 5 × 100 p sec
So, K=3
= 500 p sec
10. (a) fundamental frequency of oscillator,
When, A = 1 and B = 1 1
output =
X= Y 2 × 500 ps
Y= X = 1 GHz
Now, A = 1 and B = 0
15. (c)
Y=1
It is given that clock is positive edge triggered
X=0
than only option (a) and (c) are possible. Out of
Now, A = 1 and B = 1
which only (c) option gives the required result.
X = Y=0
16. (d)
Y = X=1
Decoding logic = 111
So, the outputs x and y will be fixed at 0 and 1
respectively. Hence, CLR = Q2 Q1 Q0
 GATE Previous Years Solved Paper 61

LSB MSB 27. (b)

J Q 1 J Q 1 J Q Time period of waveform of output at
1 CLK Q1 = 2 × 2 × T = 2T
K Q 1 K Q 1 K Q Delay time at output,
Clr Clr Clr Q1 = 2 T
Note:
(i) In case of n-flip-flops in such case, time
period of last output waveform = 2nT
17. (b)
where,
Prop. delay of 4-bit ripple counter
T = Time period for clock pulse
R = 4 × tpd = 40 ns
(ii) Delay time = n T
In synchronous counter all flip-flops are given
where,
clock simultaneously so, S = 10 ns.
T = propagation delay provided by one
20. (c) flip-flop
At the end of 6th pulse all states should be cleared.
29. (c)
CBA = 110, C B X = 00X
For NAND gates: Inputs [(0, 1); (1, 1)]
Output of desired gate should be zero as clear is
Output [(1, 0); (1, 0)]
given active low.
For NOR gates: Inputs [(0, 1); (1, 1)]
So given gate should be OR as OR gate output is
Output [(1, 0); (0, 0)]
zero if both inputs are 0.
30. (a)
21. (c)
Q1 Q2
Since, J = 1 and Qn = 0 So, Qn + 1 = 1
As given if K = 0, Qn + 1 = 1 (set) J1 Q1 J2 Q2
JK JK
CLK
flip-flop flip-flop
and if K = 1, Qn + 1 = Qn = 1 (toggle)
K1 Q1 Q2

22. (b)
Q2 Q1 Q0 = 011 Clock J1 K1 J2 K1 Q1 Q2
1st clk Q2 Q1 Q0 = 100
0 1 1 1 1 0 0
Q0 = 1 (triggers T1) 1 1 1 1 1 1 1
Q1 = 1 (triggers T2) 2 0 0 0 1 1 0
3
23. (d)
So, the sequence is 11, 10, 00, 11, 10, 00 ...
A B Ci S Co
After 1st CP : 1 1 0 0 1 31. (d)
After 2nd CP : 1 1 1 1 1 Initially, QA = QB = QC = 0
DA = QB QC = 1, DB = QA = 0
24. (a)
DC = QB = 0
Q1 Q0 D1 (Q0 ) D0 (Q1 ) After 1-clock pulse,
0 0 0 1 QA = 1, QB = 0, QC = 0
0 1 1 1 DA = QB QC = 1,
1 1 1 0 DB = QA = 1, DC = QB = 0
1 0 0 0
62 Electronics Engineering Digital Electronics

After 2-clock pulses, 34. (a)

QA = 1, QB = 1, QC = 0 Given flip-flop is S-R flip-flop with A = S and
DA = QB QC = 0 B = R. In S-R flip-flop race around condition
DB = QA = 1, DC = QB = 1 does not occur.
After 3-clock pulses,
QA = 0, QB = 1, QC = 1 35. (d)
DA = QB QC = 1 When A = 1, then Q will be selected by MUX
DB = QA = 0, DC = QB = 1 and feedback to D-flop-flop which gives output
After 4-clock pulses, Q again.
QA = 1, QB = 0, QC = 1 So, at A = 1 it holds its state. When A = 0, then Q
DA = QB QC = 0
will be selected by MUX and feedback to D-flip-
DB = QA = 1, DC = QB = 0
flop and output will be inverted.
After 5-clock pulses, So, for A = 1 it holds the state and for A = 0 it
QA = 0, QB = 1, QC = 0 interchange the state i.e. if Q = 0 then it will go
DA = QB QC = 0 to Q = 1 and if Q = 1 then it will go to Q = 0.
DB = QA = 0, DC = QB = 1 So, option (d) is correct option.
After 6-clock pulses,
QA = 0, QB = 0, QC = 1 36. Sol.
Therefore, the count sequence observed at QA is The circuit or the counter given is the
0110100 ...... asynchronous counter in which the clock is
applied to first flip-flop only and the remaining
32. (a) flip-flop take the clock from the previous flip-
Y = 1, it is possible only when both flip-flop flops outputs.
outputs are ‘1’. It means before applying clock As we know that 1 flip-flop divides the frequency
both flip-flop input should be ‘1’. by 2. So, output of Q3 is taken at 4th flip-flop. So,
Before applying clock output of 1st flip-flops division of frequency be f/16.
should be ‘0’. (Because input of 2nd flip-flop is Frequency (in kHz) of the waveform of Q3

connected to Q) and after applying clock output 1 MHz

= = 62.5 kHz
16
of 1st flip-flop should be ‘1’.
And it depends only upon input data when it 37. (c)
changes from ‘0’ to ‘1’. X1 D Q
CLK FF-1
33. (d)
Q
Output (Y)
Present State Next State
QB QA QB QA
X2 D Q
0 0 1 1 FF-1
1 1 0 1 Q
0 1 1 0 The flip-flop are negative edge trigger.
1 0 0 0 X1 X2 Y
0 0 1 1 X X Previous output/No change

Now using excitation table of D-flip-flop, 0 0 0

0 1 0
DA = (QAQB + QA QB )
1 0 0
DB = QB 1 1 1
 GATE Previous Years Solved Paper 63

So, according to waveform, 39. (d)

Given circuit diagram is a master slave D-flop-
CLK flop in which master flip-flop works on the
X1 positive cycle of clock and slave flip-flop works
on negative cycle of clock.
X2
40. Sol.
W3
QA QA
Solution waveform W3 satisfies it.
QB QB
4-bit binary
CLK
38. (d) counter QC QC
QD QD
CLEAR
Q1
J1 Q1 J2 Q2

Clear signal is QB QC .
K1 Q1 K2 Q2
Counter is cleared after 0110.

CLK
MOD is the counter is 7 as it counts states
from 0 to 6.
Initially, Q1 = Q2 = 0
Truth table of JK: 41. (c)
J K Qn Clear signal = Q3 Q2
0 0 Previous state Counter is clear after 0100.
0 1 0 So number of states counted are 0 to 4.
1 0 1 MOD of the counter is 5.
1 1 Qn
42. (a)
Case-1 : 1st clock pulse Q is applied as negative edge triggering clock.
Q1 = 0, Q1 = 1, Q2 = 0, Q2 = 1 Counter is up counter.

So, J1 = 1, K1 = 0 and J2 = 0, K2 = 1 Reset signal = Q2 Q0

The counter resets at 101.
So, Q1+ = 1, Q2+ = 0
Counter is MOD-5.
Case-2:
Q1 = 1, Q2 = 0 43. (d)
The given circuit is similar to,
Q1 = 0, Q2 = 1
Y2 Y1 Y0
So, J1 = 1, J2 = 1
K 1 = 0, K2 = 0

So, Q1+ = 1, Q2+ = 1

Case-3: Y2 Y1 Y0
Q1 = 1, Q1 = 0, Q2 = 1, Q2 = 0 Initial 1 1 1
1st clock 0 1 1
J1 = 0, K1 = 1, J2 = 1, K2 = 0
nd
2 clock 0 0 1
Q1+ = 0, Q2+ = 1 rd
3 clock 1 0 0
So, the sequence will be 01100. After three clock Y is 100.
64 Electronics Engineering Digital Electronics

44. Sol. When input condition is changed to P = Q = 1

from P = Q = 0:
Clock Q1 Q2 Q3 Q4 Q5 Y = Q3 + Q5
Possibility-1:
0 0 1 0 1 0 0
Let gate-1 is faster than gate-2, then the
1 0 0 1 0 1 1
possible outputs are X = 0, Y = 1.
2 1 0 0 1 0 0
Possibility-2:
3 0 1 0 0 1 1
4 1 0 1 0 0 1
Let gate-2 is faster than gate-1, then the
5 0 1 0 1 0 0
possible outputs are X = 1, Y = 0.

The waveform of the gate output, 47. Sol.

CK = CLK 2
0
T 2T 3T 4T 5T
T1 = 5T D = CLK 1

Y = Q3 + Q5 Output
Average power dissipated,
TCLK/5
2
V T
P= × ON TCLK/2 TCLK/2
R T
52 3T Duty cycle of output
= × = 1.5 mW
10 k 5T TCLK TCLK
= 2 5 × 100
45. (d) TCLK
Clock frequency = 1 GHz
3
Clock time period = 1 ns = × 100 = 30%
10
If the propagation delay of the NAND gate were
0 ns, the circuit would have behaved as MOD-6 48. Sol.
counter.
However, the delay of NAND gate is 2 ns. Clock Din = A D
A B C D
During this time, two more clock pulses would Number Just before clock

reach the counter, and therefore it would count Initial 1 1 0 1

two more states. Hence, it acts as MOD-8 1 0 0 1 1 0
counter. 2 0 0 0 1 1
3 1 1 0 0 1
46. (b) 4 0 0 1 0 0

P 5 0 0 0 1 0
1 X
6 0 0 0 0 1
7 1 1 0 0 0
8 1 1 1 0 0
9 1 1 1 1 0
Q 2 Y 10 1 1 1 1 1

Present input condition: So, 10 clock cycles are required.

P = Q=0
Corresponding outputs are X = Y = 1
 GATE Previous Years Solved Paper 65

49. Sol. 52. (a)

D1 = Q2 Q1 = Q2 + Q1 2-bit counter:

PS D2 D1 NS MSB LSB(J, K)
Q2 Q1 Q +2 Q +1 0 0
0 0 0 1 0 1 0 1
1 0
0 1 1 0 1 0
1 1
1 0 0 0 0 0

MOD = 3
CLK
f clk 12
fQ2 = = kHz = 4 kHz
3 3 J

50. Sol. K
Total propagation delay
Q
= (tpd + tset-up)max
= 8 ns + 5 ns = 13 ns Duty cycle = 50%
Frequency of operations fo
Output frequency =
1000 4
= MHz = 76.92 MHz
13
53. (a, c)
51. (5) p2 + p3 = 1
p2 + p3 = p5 + p6
Given: tXOR = 3 ns, f = 500 MHz p5 + p6 = 1
1 Option (a) is correct,
T= = 2 ns
f p1 + p4 + p7 = 1
Initially, Q2Q1Q0 = 111 and D2 = 1 Option (c) is correct.

Clock D2 = Q2 Q0 Q2 Q1 Q0

0 1 1 1 1

1 (at 0 ns) 1 1 1 1 (at 0 ns)

2 (at 2 ns) 1 1 1 1 (at 2 ns)

3 (at 4 ns) 0 (at 3 ns) 0 1 1 (at 4 ns)

4 (at 6 ns) 0 (at 5 ns) 0 0 1

5 (at 8 ns) 1 (at 7 ns) 1 0 0

66 Electronics Engineering Digital Electronics

Answers
EE Sequential Circuits

1. (0.5) 2. (a) 3. (b) 4. (d) 5. (d) 6. (a) 7. (d) 8. (b)

9. (c) 10. (a) 11. (d) 12. (c) 13. (a) 14. (d) 15. (b) 16. (c)

17. (b) 18. (d) 19. (6) 20. (b) 21. (c) 22. (6) 23. (b) 24. (a)

Solutions
EE Sequential Circuits

1. Sol. Excitation table:

Q(t) Q(t + 1) J K X Y
f in 1 MHz
fout = + = 0.5 MHz 0 0 0 x x 1
2 2
0 1 1 x x 0
3. (b) 1 0 x 1 1 x
Q3 Q2 Q1 Q0 1 1 x 0 0 x
y1 = Q 1 Q0
1 0 1 0 y2 = y 1 Q2 To make (X-Y) FF using (JK) FF, (J) should to (Y )
Serial
(Input) and (K) should be (X).
y2
6. (a)
y1

Q3(t + 1) = Q0(t) Q1(t) Q2(t) For the both states (0, 6); our system is stable.
It is bistable multivibrator.
CLK pulse Q3 Q2 Q1 Q0
0 1 0 1 0 7. (d)
1
1 1 1 0 1
2 For a 4-input X-NOR gate output will be zero if
2 0 1 1 0
3 number of 1’s will be odd.
3 0 0 1 1
4 We also know that output of XOR gate will be
4 0 0 0 1
5 ‘1’ will number of 1’s will be odd.
5 1 0 0 0
6
6 0 1 0 0 If the inputs will be same then output of XOR
7
7 1 0 1 0 gate will be 0 so all inputs to XNOR will be zero
so output Y will be ‘1’. So only in option (d) the
4. (d) inputs are different so Y will be zero.
In toggle mode,
8. (b)
f in 10 kHz
fout = = = 5 kHz
2 2

5. (d) CLK

X-Y truth table: J-K truth table

X Y Qn + 1 J K Qn + 1
Q
0 0 1 0 0 Qn
0 0 Qn 0 1 0
1 0 Qn 1 0 1 Output

1 1 0 1 1 Qn
 GATE Previous Years Solved Paper 67

9. (c) 13. (a)

Truth table of circuit, A

X Q(t) Q (t + 1)
CLK
0 0 0
0 1 1
T-FF
1 0 1 B

1 1 0 The above circuit is SR flip-flop. The race

around condition occurs in J-K. flip-flop.

10. (a) 14. (d)

When A = 1, then Q will be selected by MUX
X2 R and feedback to D flip-flop which gives output
Q
Q again.
So, at A = 1 it holds its state. When A = 0, then

Q will be selected by MUX and feedback to D

Q
X1 S flip-flop and output will be inverted.
So for A = 1 it holds the state and for A = 0 it
S R interchange the state i.e., if Q = 0 then it will go
to Q = 1 and it Q = 1 then it will go to Q = 0.
X1 X2 Q+
So option (d) is correct option.
1 0 1 S R Q+
0 0 NC 0 0 NC 15. (b)
0 1 0 0 1 0
x = (Q Q ) (Q Q)
1 0 1 1 0 1
0 1 0 1 1 X = 1 0 = 1 (always)
1 0 1 Q X = 1=T
Q always toggles whenever clock triggers.
11. (d)
CLK
As no combination of ‘Q’ with (X1 and X2) = 1
output is stable.
It always switches its state from ‘1’ to ‘0’ and
from ‘0’ to ‘1’.
Q
12. (c)

J K QA T QB

1 0 1 1 1 f clk 1 kHz
fQ = = = 0.5 kHz
2 2
0 1 0 1 0

1 0 1 1 0 16. (c)
Overall modulus = 5 × 5 × 5 = 125

QAQB at tn + 3 is ‘1 0’.
68 Electronics Engineering Digital Electronics

17. (b) 19. Sol.

To obtain a JK flip-flop from a T flip-flop, we JK flip-flop 1 and 2 form a synchronous
first construct the characteristic table of sequential circuits and they are synchronized
JK flip-flop, and then obtain the excitation with the output of 0th JK flip-flop.
values for the T flip-flop flop as shown below.
J1 K1 J2 K2 Q2 Q1 Q0

1 1 0 1 0 0 0
T1
J K Qn Qn + 1 T 1 1 1 1 0 1 1
0 0 0 0 0 T2
0 1 0 1 1 0 0
0 0 1 1 0 T3
1 1 0 1 0 0 0
table of JK flip-flop

values for T flip-flop

0 1 0 0 0
Characteristic

Number of cycles = 3 i.e. equal to 6 clock cycles.

Excitation
0 1 1 0 1
1 0 0 1 1
20. (b)
1 0 1 1 0
From the circuit we can find out that,
1 1 0 1 1
J0 = Q1 , K0 = Q1
1 1 1 0 1
J1 = Q0, K1 = Q0

Now, assuming T to be an output, we solve it in Present state Next state

J0 K0 J1 K1
terms of J, K, Qn inputs. This gives the definition Q1 Q0 Q1 Q0

of the logic to be applied on the T input. 1 0 0 1 0 1 0 1

Also, observing the given options, we solve for 1 0 1 0 0 1 1 1
T using a maxterms map instead of using a
0 1 1 0 1 1 1 0
minterms map, as shown below.
0 1 0 1 1 0 0 0
KQn
J K + Qn K + Qn K + Qn K + Qn So, the state diagram is

J 0 0 0 00 01

J 0

10 11
T = ( J + Qn ) (K + Qn )
At every 4n clock the system is at 00.
The circuit corresponding to this expression is
So, at 332 it will be at 00.
given option (b).
So, 33rd clock it will be at 01.
18. (d)
21. (c)
A B Q From the figure we get,
0 0 1 JA = KA = 1
0 1 1
JB = KB = QA
1 0 1
1 1 0 Clock JAKA JBKB QBQB
If any one of the input is zero output is logic ‘1’ 0 11 11 00
then output of is logic ‘0’, which represents the 1 11
NAND gate. So next state will be 11.
 GATE Previous Years Solved Paper 69

22. Sol. 24. (a)

Clock QA QB QC Q A Q B Q C QA QA QB QB QC QC Z
Sequence detector program:
0 1 0 0 1 0 0 0 0 0 0 • If consider the case of non-overlapping
1 0 1 0 1 1 0 1 0 0 1 sequence detector, then the pattern 101 is
2 0 0 1 1 1 1 1 1 0 1
appearing 2 times in the given bit sequence.
3 1 0 0 0 1 1 1 1 1 1
4 0 1 0 0 0 1 0 1 1 1 • If we consider the case of overlapping
5 0 0 1 0 0 0 0 0 1 1 sequence detector, then the pattern 101 is
6 1 0 0 1 0 0 0 0 0 0
appearing 3 times in the given bit sequence.
The output Z will again become zero after The question says that the detector is
6 clock cycles. overlapping, hence answer is (a).

23. (b)

D D D fOUT
QA QB QC

CLK
fIN

QB QC QA QB
DA DB DC QA QB QC
0 0 0
1 0 0 1 0 0
1 1 0 1 1 0
1 1 1 1 1 1
0 1 1 0 1 1 Cycle
0 0 1 0 0 1
1 0 0 1 0 0
1 1 0 1 1 0 Repeated

mod 5 counter

So, frequency will be divided by 5.

 6 Finite State Machine and
Miscellaneous
ELECTRO NICS EN GINEERIN G (a) Input A is connected to Q2 .
(GATE Previous Years Solved Papers)
(b) Input A is connected to Q2.
Q.1 The point P in the following figure is stuck-at-1. (c) Input A is connected to Q1 and S is
The output ‘f ’ will be
complemented.
A
B f
P (d) Input A is connected to Q1 .
[EC-2014 : 2 Marks]
C
Q.3 The state transition diagram for a finite state
machine with states A, B and C and binary
(a) ABC (b) A inputs X, Y and Z is shown in the figure.

(c) ABC (d) A Which one of the following statements is

correct?
[EC-2006 : 2 Marks]

Q.2 The digital logic shown in the figure satisfies Y=1

X = 1, Y = 0, Z = 0
the given state diagram when Q1 is connected A B Y=1
to input A of the XOR gate. Y = 0, Z = 0
X = 1, Y = 1,
Z=1 Z=1
X = 0, Z = 1
D1 Q1 A
D2 Q2
CLK X = 1, Y = 0 Y = 0, Z = 1
S
Q1 Q2
A

Z=0

S=0
(a) Transitions from State A are ambiguously
S=1 defined.
00 01
(b) Transitions from State B are ambiguously
S=0
defined.
S=1 S=1
(c) Transitions from State C are ambiguously
S=0
defined.
10 11 (d) All of the state transitions are defined
S=1
unambiguously.
S=0 [EC-2016 : 2 Marks]

Q.4 Transistor geometries in a CMOS inverter have

Suppose the XOR gate is replaced by an XNOR
been adjusted to meet the requirement for worst
gate. Which one of the following options
case charge and discharge times for driving a
preserves the stage diagram?
load capacitor C. This design is to be converted
 GATE Previous Years Solved Paper 71

to that of a NOR circuit in the same technology, Assume that XIN is held at constant logic level
so that its worst case charge and discharge times throughout the operation of the FSM. When the
while driving the same capacitor are similar. FSM is initialized to the QAQB = 00 and clocked,
The channel lengths of all transistors are to be after a few clock cycles, it starts cycling through
kept unchanged. Which one of the following (a) all of the four possible states if XIN = 1
statements is correct? (b) three of the four possible states if XIN = 0
VDD (c) only two of the four possible states if XIN = 1
(d) only two of the four possible states if XIN = 0
VDD
[EC-2017 : 2 Marks]
IN 2 Q.6 The state Diagram of a finite state machine
IN 1
(FSM) designed to detect an overlapping
OUT
sequence of 3-bits is shown in the figure. The
IN OUT
FSM has an input ‘IN and an output ‘OUT. The
C C initial state of the FSM is S0.

In = 0
00
Out = 0
S0
In = 1
(a) Widths of PMOS transistors should be Out = 0
In = 0 In = 1
doubled, while widths of NMOS transistors 01
Out = 0 Out = 0
should be halved. S1 In = 0
(b) Widths of PMOS transistors should be Out = 0
doubled, while widths of NMOS transistors In = 1
10
should not be changed. Out = 0
S2
In = 0 In = 1
(c) Widths of PMOS transistors should be Out = 0 Out = 1
halved, while widths of NMOS transistors
should not be changed. 11

(d) Widths of PMOS transistors should be S3

unchanged, while widths of NMOS In the input sequence is 10101101001101,

transistors should be halved. starting with the left most bit, then the number
[EC-2016 : 1 Mark] of times ‘OUT’ will be 1 is ______ .
Q.5 A Finite State Machine (FSM) is implemented [EC-2017 : 2 Marks]
using the D-flip-flops A and B, and logic gates, Q.7 A traffic signal cycles from GREEN to YELLOW,
as shown in the figure below. The four possible YELLOW to RED and RED to GREEN. In each
states of the FSM are QAQB = 00, 01, 10 and 11. cycle, GREEN is turned-on for 70 seconds,
YELLOW is turned-on for 5 seconds and the
RED is turned-on for 75 seconds. This traffic
light has to be implemented using a finite state
D Q D Q QB
QA machine (FSM). The only input to this FSM is a
A B clock of 5 seconds period. The minimum number
XIN
CK Q CK Q of flip-flops required to implement this FSM is
CLK ______ .
[EC-2018 : 1 Mark]
 72 Electronics Engineering Digital Electronics

Q.8 In the circuit shown below, a positive edge- A=0

A=1
A=0
triggered D-flip-flop is used for sampling input (c)
Q=0 Q=1
data Din using clock CK. The XOR gate outputs
A=1
3.3 Volts for logic HIGH and 0 Volts for logic
LOW levels. The data bit and clock periods are A=0
A=0
equal and the value of T/TCK = 0.15, where the A=1
parameters T and TCK are shown in the figure. (d)
Q=0 Q=1
Assume that the flip-flop and the XOR gate are A=1
ideal.
[EC-2019 : 2 Marks]
X
Q.10 The state diagram of a sequence detector is
Din D Q
shown below. State S0 is the initial state of the
D-FF
sequence detector. If the input is 1, then
CLK
0/0
1/0 0/0
CK

TCLK
S0 S1 S2 S3
0/0 1/0 0/0
CK
1/0
Din
S4
1/0
0/1
T T T
1/0
If the probability of input data bit (Din) transition
in each clock period is 0.3, the average value (a) the sequence 01010 is detected.
(in volts, accurate to two decimal places) of the (b) the sequence 01011 is detected.
voltage at node X, is ______ . (c) the sequence 01001 is detected.
[EC-2018 : 2 Marks] (d) the sequence 01110 is detected.
Q.9 The state transition diagram for the circuit [EC-2020 : 2 Marks]
shown is Q.11 The content of the registers are R1 = 25 H,
R2 = 30 H and R3 = 40 H. The following machine
instructions are executed:
D Q 1 PUSH {R1}
PUSH {R2}
PUSH {R3}
Q 0
CLK POP {R1}
A POP {R2}
A=1
A=0
A=0 POP {R3}
After execution, the content of registers R1, R2,
(a) Q=0 Q=1
R3 are:
A=1 (a) R1 = 25 H, R2 = 30 H, R3 = 40 H
A=0 (b) R1 = 40 H, R2 = 30 H, R3 = 25 H
A=0 (c) R1 = 30 H, R2 = 40 H, R3 = 25 H
A=1

(b) (d) R1 = 40 H, R2 = 25 H, R3 = 30 H
Q=0 Q=1
[EC-2021 : 2 Marks]
A=1
 GATE Previous Years Solved Paper 73

Electronics & Electrical Engineering

GATE Previous Years Solved Paper

A n swe rs & Expl a n a t i o n s

Answers
EC Finite State Machine and Miscellaneous

1. (d) 2. (d) 3. (c) 4. (b) 5. (d) 6. (4) 7. (5)

8. (0.8415) 9. (b) 10. (a) 11. (b)

Solutions
EC Finite State Machine and Miscellaneous

1. (d) So, to keep this output, A should be connected

to Q1 as,
B 1 A
f
0 A A D2 = Q1 S
0 1
= Q1 S = Q1 S

C 3. (c)
C
For State A :
2. (d) X Y Z Present State Next State
0 0 0 A B
0 0 1 A A
D1 Q1 A
D2 Q2 0 1 0 A A
CLK 0 1 1 A A
S
Q1 Q2 1 0 0 A C
1 0 1 A C
1 1 0 A A
Initially when X-OR gate is connected to the
1 1 1 A A
input of flip-flop 2 i.e. input of D2, i.e.
D2 = A S = Q1 S For State B :
Now, X-OR is replaced by X-NOR, keeping state X Y Z Present State Next State
diagram to be unchanged it means the input to 0 0 0 B A
D2 should not get changed. 0 0 1 B C
When replaced by X-NOR gate. 0 1 0 B B
Now, D2 = A S 0 1 1 B B
Also, we know that, 1 0 0 B A
A B = A B= A B 1 0 1 B B
1 1 0 B B
We require output to be as D2 = A S
1 1 1 B B
74 Electronics Engineering Digital Electronics

For State C : 6. Sol.

X Y Z Present State Next State By observing the given state diagram, it is clear
0 0 0 C C that, the FSM can be used to detect the sequence
0 0 1 C C ‘101.
0 1 0 C C It is given in the question that, the FSM detects
0 1 1 C B overlapping sequences also.
1 0 0 C C The given input sequence is,
1 0 1 C A 10101101001101 So, output will be 1
1 1 0 C C
for 4 times.
1 1 1 C AB
In state ‘C’ when XYZ = 111; the ambiguity 7. Sol.
occurs. Because from state ‘C’. GREEN 70 seconds
When, X=1 YELLOW 5 seconds
Z=1 Next state = A RED 75 seconds
When Y=1 Clock period 5 seconds
Z=1 Next state = B Total number of unique states required
70 + 5 + 75
5. (d) = = 30
5
In the given diagram, Minimum number of flip-flops required is,
DA = QA QB
n = log 2 (30) = 4.91 = 5
and DB = QA XIN
For XIN = 0 : 8. Sol.
DA = QA QB TCLK
and DB = 1
CK
Present State Present State
DA DB Din
QA QB Q A+ Q B+
T T T
0 0 0 1 0 1
3.3 V (1)
0 1 1 1 1 1 0V
1 1 0 1 0 1 0V (2)

0 1 1 1 1 1 1. When input is changed during clock period

So, for XIN = 0, number of possible states = 2 (with probability 0.3).
For XIN = 1 : 2. When input is not changed during clock
DA = QA QB period (with probability 0.7).
and DB = Q A T
VX (avg) = 0.3 × 3.3 1 + [0.7 × 0] V
Tclk
Present State Present State
DA DB = 0.3 × 3.3 × (1 – 0.15) V
QA QB Q A+ Q B+
= 0.3 × 3.3 × 0.85 V
0 0 0 1 0 1
= 0.8415 V
0 1 1 1 1 1
1 1 0 0 0 0 9. (b)
0 0 0 1 0 1 When, A = 0, Qn + 1 = 1

So, for XIN = 1, number of possible states = 3 When, A = 1, Qn + 1 = Qn

 GATE Previous Years Solved Paper 75

So, the correct state transition diagram is, Stack memory

A=0
A=0 Pop R1
A=1
Pop R2 40 H R1
Q=0 Q=1
Pop R3 30 H R2
25 H R3
A=1
i.e., R 1 = 40 H, R2 = 30 H, R3 = 25 H
10. (a)
The sequence detected is 01010.

11. (b)
R 1 = 25 H, R2 = 30 H, R3 = 40 H
Stack memory

Push R1
Push R2 40 H
Push R3 30 H
25 H
 7 Logic Families

ELECTRO NICS EN GINEERIN G (c) the load transistor has a smaller W/L ratio
compared to the driver transistor.
(GATE Previous Years Solved Papers)
(d) none of the above [EC-1997 : 1 Mark]
Q.1 In figure, the Boolean expression for the output
Q.4 For the NMOS logic gate shown in figure, the
in terms of inputs A, B and C when the clock
logic function implemented is
‘CK’ is high, is given by
VDD

p-channel

F
CK
A B A D

C B C E

n-channel

(a) ABCDE
[EC-1991 : 1 Mark]
(b) ( AB + C ) ( D + E)
Q.2 The CMOS equivalent of the following n MOS
(c) A ( B + C ) + D E
gate (figure) is (draw the circuit).
(d) ( A + B) C + D E
VDD
[EC-1997 : 1 Mark]

Output Q.5 The threshold voltage for each transistor in

figure is 2 V. For this circuit to work as an
B inverter, Vi must take the values

A C

[EC-1991 : 1 Mark] Vi Vo

Q.3 The gate delay of an NMOS inverter is

dominated by charge time rather than discharge
time because
–5 V
(a) the driver transistor has a larger threshold
(a) –5 V and 0 V (b) –5 V and 5 V
voltage than the load transistor.
(c) 0 V and 5 V (d) –3 V and 3 V
(b) the driver transistor has larger leakage
currents compared to the load transistor. [EC-1998 : 1 Mark]
 GATE Previous Years Solved Paper 77

Q.6 The circuit in the figure has two CMOS NOR- (a) P NOR Q (b) P NAND Q
gates. This circuit functions as a (c) P OR Q (d) P AND Q
R [EC-2008 : 2 Marks]
VSS
Vo (output) Q.9 In the circuit shown

5V
VSS

0 Vi A
C

(a) flip-flop
C
(b) schmitt trigger
(c) monostable multi-vibrator B

(d) astable multi-vibrator Y

[EC-2002 : 2 Marks]
C
Q.7 Both transistors T1 and T2 shown in the figure,
have a threshold voltage of 1 volts. The device
parameters K 1 and K 2 of T 1 and T 2 are, A B
respectively, 36 µA2 and 9 µA/V2. The output
voltage Vo is
5V

(a) Y = A B + C (b) Y = (A + B) C
T1
Vo (c) Y = ( A + B) C (d) Y = AB + C

T2 [EC-2012 : 1 Mark]

Q.10 In the circuit shown below, Q1 has negligible

(a) 1 V (b) 2 V collector-to-emitter saturation voltage and the
diode drops negligible voltage across it under
(c) 3 V (d) 4 V
forward bias. If VCC is +5 V, X and Y are digital
[EC-2005 : 2 Marks]
signals with 0 V as logic 0 and VCC as logic 1,
Q.8 The logic function implemented by the following the Boolean expression for Z is
circuit at the terminal OUT is
+VCC
Vdd
R1

Z
R2
OUT
X Q1
Diode
P Q
Y

(a) XY (b) X Y

(c) X Y (d) XY
[EC-2013 : 2 Marks]
 78 Electronics Engineering Digital Electronics

Q.11 The output (Y) of the circuit shown in the figure (a) 3 input OR gate
is (b) 3 input NOR gate
VDD (c) 3 input AND gate
(d) 3 input XOR gate
A B C [EC-2015 : 1 Mark]

Y
Q.14 An SR latch is implemented using TTL gates as
shown in the figure. The set and reset pulse
A inputs are provided using the push-button
switches. It is observed that the circuit fails to
B work as desired. The SR latch can be made
functional by changing,
C

Set Q

(a) A + B + C (b) A + B C + A C 5V
(c) A + B + C (d) A B C
[EC-2014 : 1 Mark] Q
Reset
Q.12 In the following circuit employing pass
(a) NOR gates to NAND gates.
transistor logic, all NMOS transistors are
(b) inverting to buffers.
identical with a threshold voltage of 1 V.
(c) NOR gates to NAND gates and inverters to
Ignoring the body-effect, the output voltages at
buffers.
P, Q and R are
(d) 5 V to ground.
5V 5V 5V
[EC-2015 : 2 Marks]

Q.15 The functionally implemented by the circuit

5V below is
P Q R
(a) 4 V, 3 V, 2 V (b) 5 V, 5 V, 5 V P
Q
(c) 4 V, 4 V, 4 V (d) 5 V, 4 V, 3 V
R
[EC-2014 : 1 Mark] S Y
Q0
Q.13 In the circuit shown, diodes D1, D2 and D3 are
ideal, and the inputs E1, E2 and E3 are ‘0 V’ for
C1 Q1
logic ‘0’ and ‘10 V’ for logic ‘1’. What logic gate
2:4
does the circuit represent? Decoder Q2
D1 C0
E1 Q3

D2
E2 Enable = 1

D3 is a tristate buffer
E3 Vo
(a) 2-to-1 multiplexer
1k
(b) 4-to-1 multiplexer
10 V (c) 7-to-1 multiplexer
(d) 6-to-1 multiplexer [EC-2016 : 2 Marks]
 GATE Previous Years Solved Paper 79

Q.16 The logic functionally realized by the circuit Q.19 The logic gates shown in the digital circuit
shown below is below use strong pull-down nMOS transistors
B B for LOW logic level at the outputs. When the
pull-downs are off, high value resistors set the
output logic levels to HIGH (i.e. the pull-ups
A are weak). Note that some nodes are
Y intentionally shorted to implement “wired
logic”. Such shorted nodes will be HIGH only if
the outputs of all the gates whose outputs are
(a) OR (b) XOR shorted are HIGH.
(c) NAND (d) AND
X0
[EC-2016 : 1 Mark]

Q.17 For the circuit shown in the figure. P and Q are X1

the inputs and Y is the output. X2
Y
X3
PMOS

The number of distinct values of X3 X2 X1 X0

Y
(out of the 16 possible values) that give Y = 1 is
P NMOS _________ .
Q [EC-2018 : 2 Marks]

Q.20 In the circuit shown, A and B are the inputs and

The logic implemented by the circuit is F is the output. What is the functionality of the
(a) XNOR (b) XOR circuit?
(c) NOR (d) OR Vdd
[EC-2017 : 1 Mark]

Q.18 The logic f(X, Y) realized by the given circuit is

VDD

X X

Y F
Y

f(X, Y)

A B

(a) XNOR (b) SRAM Cell

(a) NOR (b) AND (c) XOR (d) Latch
(c) NAND (d) XOR [EC-2019 : 1 Mark]
[EC-2018 : 1 Mark]
 80 Electronics Engineering Digital Electronics

Q.21 In the circuit shown, what are the values of F for 3V 3V 3V

EN = 0 and EN = 1, respectively?
VDD

Vout2

EN 3V

(a) 1.8 and 2.4 (b) 2.4 and 1.2

D
(c) 1.8 and 1.2 (d) 2.4 and 2.4
[EC-2019 : 2 Marks]

(a) 0 and 1 (b) Hi-Z and D

ELECTRICAL EN GINEERIN G
(c) Hi-Z and D (d) 0 and D (GATE Previous Years Solved Papers)
[EC-2019 : 1 Mark]
SECTIO N - A
Q.22 A standard CMOS inverter is designed with
equal rise and fall times ( n = p). If the width of Q.1 The open collector outputs of two inputs
the pMOS transistor in the inverter is increased, NAND-gates are connected to a common pull
what would be the effect on the LOW noise up resistor. If the input to the gates are P, Q and
margin (NML) and the HIGH noise margin R, S respectively, the output is equal to
NMH?
(a) PQ RS (b) PQ + RS
(a) NML decreases and NMH increases
(c) PQ + RS (d) PQRS
(b) No change in the noise margins
[EE-1998 : 1 Mark]
(c) Both NML and NMH increases
(d) NML increases and NMH decreases Q.2 If X1 and X2 are the inputs to the circuit shown
[EC-2019 : 1 Mark] in the figure, the output Q is
VDD
Q.23 In the circuits shown, the threshold voltage of
each nMOS transistor is 0.6 V. Ignoring the effect
of channel length modulation and body bias,
the values of Vout1 and Vout2, respectively,
(in Volts), are Q

3V
X1 X2

(a) X1 + X2 (b) X1 X2
3V (c) X 1 X 2 (d) X 1 X 2
Vout1 [EE-2005 : 2 Marks]
3V Q.3 The TTL circuit shown in the figure is fed with
the waveform X (also shown). All gates have
equal propagation delay of 10 ns. The output Y
of the circuit is
 GATE Previous Years Solved Paper 81

X (a) XY (b) XY
100 ns (c) XY (d) XY
1
[EE-2013 : 2 Marks]
t
0
Q.5 The logical gate implemented using the circuit
X
Y shown below where, V1 and V2 are inputs (with
0 V as digital 0 and 5 as digital 1) and Vout is the
output, is
Y 5V

1k
(a) 1
V out
1k
t Q1
0 V1
1k
Y V2 Q2

(b) 1

t (a) NOT (b) NOR

0
(c) NAND (d) XOR
Y
[EE-2017 : 2 Marks]

1
(c) SECTIO N -B
t
0 Q.1 A 10 bit A/D converter is used to digitize an
analog signal in the 0 to 5 V range. The
Y
maximum peak to peak ripple voltage that can
be allowed in the dc supply voltage is
(d) 1
(a) nearly 100 mV (b) nearly 50 mV
t (c) nearly 25 mV (d) nearly 5 mV
0
[EE-1993 : 1 Mark]
[EE-2010 : 2 Marks]
Q.2 The number of comparisons carried out in a 4-bit
Q.4 In the circuit shown below, Q1 has negligible
flash type A/D converter is
collector-to-emitter saturation voltage and the
(a) 16 (b) 15
diode drops negligible voltage across it under
forward bias. If VCC is +5 V, X and Y are digital (c) 4 (d) 3
signals with 0 V as logic 0 and VCC as logic 1, [EE-1994 : 1 Mark]
the Boolean expression for Z is Q.3 A dual-slope analog-to-digital converter uses
+V CC an N-bit counter. When the input signal Va is
being integrated, the counter is allowed to count
R1
up to a value
Z (a) equal to 2N – 2
X Q1 (b) equal to 2N – 1
R2 Diode (c) proportional to Va
(d) inversely proportional to Va
Y
[EE-2000 : 2 Marks]
 82 Electronics Engineering Digital Electronics

Q.4 Among the following four, the slowest ADC Q.7 The Octal equivalent of the HEX number AB CD
(analog-to-digital converter) is is
(a) parallel-comparator (i.e. flash) type (a) 253.314 (b) 253.632
(b) successive approximation type (c) 526.314 (d) 526.632
(c) integrating type [EE-2007 : 2 Marks]
(d) counting type [EE-2001 : 1 Mark]
Q.8 An 8-bit, unipolar successive approximation
Q.5 The voltage comparator shown in the figure can register type ADC is used to convert 3.5 V to
be used in the analog-to-digital conversion is digital equivalent output.
V1 The reference voltage is +5 V. The output of the
–
Vo ADC at the end of 3rd clock pulse after the start
V2 +
of conversion, is
(a) a 1-bit quantizer (b) a 2-bit quantizer (a) 1010 0000 (b) 1000 0000
(c) a 4-bit quantizer (d) a 8-bit quantizer (c) 0000 0001 (d) 0000 0011
[EE-2004 : 1 Mark] [EE-2015 : 2 Marks]
Q.6 A student has made a 3-bit binary down counter Q.9 A temperature in the range of –40°C to 55°C is
and connected to the R-2-R ladder type DAC to be measured with a resolution of 0.1°C. The
[Gain = (–1 k /2R)] as shown in figure to minimum number of ADC bits required to get a
generate a staircase waveform. The output matching dynamic range of the temperature
achieved is different as shown in figure. What sensor is
could be the possible cause of this error? (a) 8 (b) 10
R R R 1k (c) 12 (d) 14
[EE-2016 : 1 Mark]
2R 2R 2R 2R
+12 V
Q.10 A 2-bit flash analog-to-digital converter (ADC)
–
Vo is given below. The input is 0 < Vin < 3 Volts.
Counter
+ The expression for the LSB of the output B0 as a
1 kHz –12 V
Clock Boolean function of X2, X1 and X0 is
10 k
3V

100

7 + X2
6 –
200
5 B1
4 + X1 Digital
3 circuit
200 –
2
B0
1
+ X0
0
100 –
0 1 2 3 4 5 6 7 ms
V in
(a) The resistance values are incorrect.
(b) The counter is not working properly. (a) X 0 X 2 X1 (b) X 0 X 2 X1
(c) The connection from the counter to DAC is (c) X0[X2 X1] (d) X0 [ X 2 X1 ]
not proper.
[EE-2016 : 2 Marks]
(d) The R and 2R resistances are interchanged.
[EE-2006 : 2 Marks]
 GATE Previous Years Solved Paper 83

Electronics & Electrical Engineering

GATE Previous Years Solved Paper

A n swe rs & Expl a n a t i o n s

Answers
EC Logic Families

1. (Sol.) 2. (Sol.) 3. (c) 4. (c) 5. (a) 6. (c) 7. (c) 8. (d)

9. (a) 10. (b) 11. (a) 12. (c) 13. (c) 14. (d) 15. (b) 16. (d)

17. ( ) 18. (d) 19. (8) 20. (a) 21. (b) 22. (d) 23. (a)

Solutions
EC Logic Families

1. Sol. 3. (c)
When clock is high then p-channel is off, so the The gate delay of an NMOS inverter is
input to CMOS is logic 0, then the output of the dominated by charge time rather than discharge
CMOS inverter is logic 1. time because the load transistor has a smaller
W/L ratio compared to the driver transistor.
2. Sol.
CMOS circuit: PMOS and NMOS both , 4. (c)

VDD F = A ( B + C ) + DE

A 5. (a)
VT = 2 V
Vi = –5 V Vo = 0
B C Vi = 0 V Vo = –5 V

7. (c)
Output ID1 = ID2

B K1 (VGS 1 Vt )2 = K 2 (VGS 2 Vt )2
A 36(5 – Vo – 1)2 = 9(Vo – 0 – 1)2
C Vo = 3 V

9. (a)
Series combination of n-mos is equivalent to
AND and parallel combination is equivalent to
Output = A + BC OR.
So, Y = C ( A + B) = C + ( A + B) = C + A B
84 Electronics Engineering Digital Electronics

10. (b) According to the given options the only

condition satisfied for the voltages at P, Q and
X Y Z X Y Q Z
R is only option (c).
0 0 0 0 0 OFF 0
0 1 1 0 +5 V OFF +5 V 13. (c)
1 0 0 +5 V 0 ON 0 Case-(i) : If any input is logic 0 (i.e., 0 V) then
1 1 0 +5 V +5 V ON 0 corresponding diode is ‘ON’ and due to ideal
diode output voltage Vo = 0 as well as if there is
11. (a) any input logic 1 (i.e., 10 V) corresponding diode
will be OFF.
VDD Case-(ii) : If all the inputs are high (i.e., 10 V)
then all the diodes are R.B.(OFF) and output
A B C voltage Vo = 10 V.
So, it is a positive 3-inputs AND gate.
Y
Output 14. (d)
A
For TTL gate, open end acts as logic ‘1’.
So if we connect 5 V battery to ground then
B pressing the switches allow logic ‘0’ while
operating the switches allow logic ‘1’. In case of
C 5 V battery both opening and closing of switches
allow logic ‘1’ and hence circuit can’t act as SR
latch.
This is the diagram of NAND gates made up of
15. (b)
CMOS gates. So output X is given as,
When the outputs (O0, O1, O2, O3) of the decoder
Y = A B C = (A + B + C) are at logic 1, the corresponding tristate buffer
is activated. In that case, whatever data is
12. (c) applied at the input of a buffer, becomes its
5V 5V 5V output. Hence when,
C1C 0 = 00, Then O0 = 1
Y=P
C1C 0 = 01, Then O1 = 1
5V Y=Q
P Q R C1C 0 = 10, Then O2 = 1
Y=R
As we know that for proper operation,
C1C 0 = 11, Then O3 = 1
VDS = VGS – VT
Y=S
VD – VS = VG – VS – VT
the circuit effectively behaves as a 4 to 1
VD = VG – VT
multiplexer.
At P :
VD = VG – VT 16. (d)
Given VG for all transistor = 5 V and VT for all The output Y will be logic 1, when
transistor = 1 V
A = 1, B = 1 and B = 0
VD at P = VG – VT = 5 – 1 = 4 V
VD at Q = VG – VT = 5 – 1 = 4 V Y = A B B=A B
VD at R = VG – VT = 5 – 1 = 4 V AND operation
 GATE Previous Years Solved Paper 85

17. ( ) 21. (b)

The given circuit is wrong. VDD

18. (d) x1
From pull-down network, EN

f ( X , Y ) = X Y + XY = X Y F

f (X, Y) = X Y =X Y x2
D
19. Sol.

X0 Wired AND
When, EN = 0
B
X1 x 1 = (D 0) = 1 PMOS is in OFF state
A
X2
x 2 = (1 + D) = 0 NMOS is in OFF state
Y
X3 Both the transistors are in OFF state, which offers
high impedance.
A = (X1 X2 ) X3 When, EN = 1
B = [( X 1 X 2 ) X 3 X0 ] X 0 = 0 x 1 = (D 1) = D
Y = B + X3 = 0 + X3 = X3
x 2 = (0 + D) = D
Out of 16 possible combinations of X3 X2 X1 X0,
X3 will be high for 8 combinations. So, Y will be F=D
high for 8 combinations. 22. (d)
20. (a) VOUT

Vdd VDD
Slope = –1
Q1
NML

Q2
When, n = p

NMH
Q3 Q4
VDD
0 VIN
VOL VIL VIH VOH
A B VDD
VIT =
2
A B Q1 Q2 Q3 Q4 F
0 0 ON ON OFF OFF 1 Making PMOS wider, shifts input transition
0 1 OFF ON ON OFF 0 point (VIT) towards VDD.
1 0 ON OFF OFF ON 0 Making NMOS wider, shifts input transition
1 1 OFF OFF ON ON 1 point (VIT) towards zero.
So, as PMOS made wider, NML increases and
So, the given logic circuit acts as an XNOR gate.
NMH decreases.
86 Electronics Engineering Digital Electronics

23. (a) 3V 3V 3V

3V + + +
0.6 0.6 0.6
+ – – –
0.6 Vout2
2.4 V
–
3V 2.4 V 2.4 V
+
0.6
3V
–
Vout1
Vout 2 = 2.4 V
3V

Vout 1 = 3 – 0.6 – 0.6 = 1.8 V

Answers
EE Logic Families (Section-A)

1. (a) 2. (d) 3. (a) 4. (b) 5. (b)

Solutions
EE Logic Families (Section-A)

1. (a)
Pull up resistor works as a AND gate.
P X1

Q
t
PQ RS
20 nsec
R
S

1
2. (d)
Output Y
Y 1 = X1 0
t

Output, Q = Y1 + X 2 = ( X1 + X 2 )
Q = X1 X 2 4. (b)

3. (a) X Y Q Z
0 0 OFF 0
0 +5 V OFF +5 V
100 nsec
1
+5 V 0 ON 0

X +5 V +5 V ON 0

t
0 Z = XY
 GATE Previous Years Solved Paper 87

5. (b) When, V1 = high 5 V Q1 on Vout = 0

V2 = high 5 V Q2 on Vout = 0
5V
Thus when any V1 or V2 is high then,
1k Vout = 0

Vout V1 V2 Vout
1k 0 0 1
V1 Q1
1k 0 1 0
V2 Q2
1 0 0
1 1 0

Thus it is a NOR gate.

Answers
EE Logic Families (Section-B)

1. (d) 2. (b) 3. (c) 4. (c) 5. (a) 6. (c) 7. (b) 8. (a)

9. (b) 10. (a)

Solutions
EE Logic Families (Section-B)

1. (d) Similarly next state of counter = (101)2 = (5)10

If the ripple voltage is more than the resolution, Input to DAC = (101)2 = (5)10
it will go to next level. So, output = 5 V
V 5 When output goes to (100)2 then input to DAC
Resolution = n
= 5 mV = (001)2 = (1)10
2 2 10
So, output = 1 V
2. (b) So, connections are not proper.
Number of comparators = 2N – 1 = 24 – 1 = 15
7. (b)
5. (a) Hex number (AB CD)
Even when V1 > V2, the (output) ‘Vo’ is high and A B C D
for the next case (V1 < V2) (output) is low it is 1010 1011 1100 1101
1 bit quantizer. Since it has two states which For finding its octal number, we can add one
can be represented by 1 bit. zero in both extreme and grouping.
6. (c) 010 1 01 0 11 11 0 0 11 010
2 5 3 6 3 2
Initial stage of the counter = (111)2 = (7)10
So output will be equal to 7 V. equivalent octal number: 253.6328
Next state of counter = (110)2 = (6)10
8. (a)
So output should be = 6 V
But output is 3 V that means LSB of counter is The reference voltage is 5 V.
connected to MSB of DAC and MSB of counter The number of bits in ADC are 8.
is connected to LSB of DAC.
88 Electronics Engineering Digital Electronics

5 5 10. (a)
So, the resolution will be = 8
=
2 1 255 The input to digital circuit is X2, X1, X0 and
The applied input is 3.5 V. output is B1B0.
The successive approximation ADC start
X2 X1 X0 B1 B0
working from the MSB so.
0 0 0 0 0
After one clock:
0 0 1 0 1
SAR will toggle it’s MSB from 0 1 so output of
0 1 1 1 0
SAR will be 1000 0000.
1 1 1 1 1
After second clock:
SAR will toggle its 7th bit from 0 1 but 1100 X1X0
0000 will result in value greater than 3.5 so B0 = X2 00 01 11 10

output of SAR after 2nd clock will be 1000 0000. 0 0 1 0 X

After third clock:

1 X X 1 X
SAR will toggle it’s 6th bit from 0 ® 1 and output
will be 10100000.
B0 = X 2 X 1 X0 + X 2 X 1 X0
9. (b)
= X0 ( X 2 X1 + X 2 X1 )
Temperature range of –40°C to 55°C.
So total range in 95°C. = X0 ( X2 X1 )
Since resolution is 0.1°C.
So number of steps will be 950.
To have 950 steps we need at least 10 bits.
 8 Memories

ELECTRO NICS EN GINEERIN G Q.6 In the DRAM cell in the figure, the Vt of the
NMOSFET is 1 V. For the following three
(GATE Previous Years Solved Papers)
combinations of WL and BL voltages.
Q.1 Choose the correct statement from the following: Word line (WL)
(a) PROM contains a programmable AND
array and a fixed OR array.
(b) PLA contains a fixed AND array and a
Bit line
programmable OR array. (BL)
(c) PROM contains a fixed AND array and a C

programmable OR array.
(d) PLA contains a programmable AND array (a) 5 V, 3 V, 7 V (b) 4 V, 3 V, 4 V
and a programmable OR array.
(c) 5 V, 5 V, 5 V (d) 4 V, 4 V, 4 V
[EC-1992 : 1 Mark]
[EC-2001 : 2 Marks]
Q.2 A PLA can be
Q.7 If the input X3, X2, X1, X0 to the ROM in the figure
(a) as a microprocessor.
are 8 4 2 1 BCD numbers, then the outputs Y3,
(b) as a dynamic memory. Y2, Y1, Y0 are
(c) to realize a sequential logic.
X3 X2 X1 X 0
(c) to realize a combinational logic.
[EC-1994 : 1 Mark]
ROM BCD-to-decimal decoder
Q.3 A dynamic RAM consists of
D0 D1 D8 D9
(a) 6 transistors
(b) 2 transistors and 2 capacitors
(c) 1 transistor and 2 capacitor
Y3
(d) 2 capacitors only Y2
Y1
[EC-1994 : 1 Mark] Y0

Q.4 The minimum number of MOS transistors

required to make a dynamic RAM cell is
(a) Gray code numbers.
(a) 1 (b) 2
(b) 2 4 2 1 BCD numbers.
(c) 3 (d) 4
(c) Excess-3 code numbers.
[EC-1995 : 1 Mark]
(d) None of the above [EC-2002 : 2 Marks]
Q.5 Each cell of a static Random Access Memory
contains Q.8 In the circuit shown in the figure, A is parallel-
in, parallel-out 4-bit register, which loads at the
(a) 6 MOS transistors.
rising edge of the clock C. The input lines are
(b) 4 MOS transistors and 2 capacitors.
connected to a 4-bit bus, W. Its output acts as
(c) 2 MOS transistors and 4 capacitors.
the input to a 16 × 4 ROM whose output is
(d) 1 MOS transistor and 2 capacitors. floating when the enable input E is 0. A parallel
[EC-1996 : 1 Mark] table of the contents of the ROM is as follows:
 90 Electronics Engineering Digital Electronics

Address 0 2 4 6 8 10 11 14 WL
VDD
Data 0011 1111 0100 1010 1011 1000 0010 1000 BL BL
W
MSB

(c)

C A

1
ROM WL
E VDD
BL BL

(d)
C:

t1 t2 time
The clock to the register is shown, and the data
on the W bus at time t1 is 0110. The data on the [EC-20014 : 2 Marks]
bus at time t2 is
Q.10 In a DRAM,
(a) 1111 (b) 1011
(a) periodic refreshing is not required.
(c) 1000 (d) 0010
(b) information is stored in a capacitor.
[EC-2003 : 2 Marks] (c) information is stored in a latch.
Q.9 If WL is the Word Line and BL the Bit Line, an (d) both read and write operations can be
SRAM cell is shown in performed simultaneously.
[EC-2017 : 1 Mark]
WL
VDD Q.11 A 2 × 2 ROM array is built with the help of
BL BL
diodes as shown in the circuit below. Here W0
and W1 are signals that select the word lines
and B0 and B1 are signals that are output of the
(a)
sense amps based on the stored data
corresponding to the bit lines during the read
operation.
B0 B1

Sense amps
WL
VDD W0
BL BL

W1

(b)
VDD
 GATE Previous Years Solved Paper 91

B0 B1 1 0 0 1
(a) 0 1 (b) 1 0
W0 D00 D01
W1 D10 D11
1 0 1 1
Bits stored in the ROM array (c) 1 0 (d) 0 0
During the read operation, the selected word
[EC-2018 : 2 Marks]
line goes high and the other word line is in a
high impedance state. As per the Q.12 Addressing of a 32 k × 16 memory is realized
implementation shown in the circuit diagram using a single decoder. The minimum number
above, what are the bits corresponding to Dij of AND gates required for the decoder is
(where, i = 0 or 1 and j = 0 or 1) stored in the (a) 2 8 (b) 2 32
ROM? (c) 2 19 (d) 2 15
[EC-2021 : 1 Mark]

Electronics & Electrical Engineering

GATE Previous Years Solved Paper

A n swe rs & Expl a n a t i o n s

Answers
EC Memories

1. (c, d) 2. (d) 3. (c) 4. (b) 5. (a) 6. (b) 7. (b) 8. (c)

9. (b) 10. (b) 11. (a) 12. (d)

Solutions
EC Memories

1. (c, d) 3. (c)
PROM contains a fixed AND array and a A dynamic RAM consists of 1 transistor and 1
programmable OR array. capacitor or 2 MOSFETs.
PLA contains a programmable AND array and
5. (a)
a programmable OR array.
Each cell of a static RAM contains six MOS
2. (d) transistors. Each bit on static RAM is stored on
PLA is a type of fixed architecture logic devices four transistors out of which two are PMOS and
with programmable AND gates followed by two are NMOS, that from cross-coupled
programmable OR gates. The PLA can be used inverters. Remaining two transistors are used
to implement a complex combinational circuits. to control reading from or writing into cell.
92 Electronics Engineering Digital Electronics

7. (b) 11. (a)

2 4 2 1
B0 B1
x3 x2 x1 x0 y3 y2 y1 y0
Sense amps
0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 1 W0
0 0 1 0 0 0 1 0 2
0 0 1 1 0 0 1 1 3
W1
0 1 0 0 0 1 0 0 4
0 1 0 1 0 1 0 1 5
VDD
0 1 1 0 1 1 0 0 6
0 1 1 1 1 1 0 1 7
1 0 0 0 1 1 1 0 8
1 0 0 1 1 1 1 1 9

It is 8421BCD to 2421BCD. • When, W0 = VDD, B0 = VDD, otherwise B0 = 0

• When, W1 = VDD, B1 = VDD, otherwise B1 = 0
8. (c)
So, B0 = W0 and B1 = W1
When ‘W’ has data 0110 i.e. 6 in decimal its B 0B 1
data value at that adder is 1010.
W0 1 0
Now 1010 i.e. 10 is acting as address at time t2 Hence,
W1 0 1
and data at that moment is 1000.

9. (b) 12. (d)

Memory size = 32 k × 16 = 215 × 16
WL
VDD 32 k × 16 memory

BL BL
A14

M5 M2 M4
M6 15
address
lines

Q 2
15

Q A0
Decoder
memory
locations

M1 M3

10. (b) 16

In a DRAM, data is stored in the form of charge

So, number of AND gates required = 215.
on capacitor and periodic refreshing is needed
to restore the charge on capacitor.
 9 ADC and DAC

ELECTRO NICS EN GINEERIN G Q.5 The number of comparators in a 4-bit flash ADC
is
(GATE Previous Years Solved Papers)
(a) 4 (b) 5
Q.1 For an ADC, match the following: if (c) 15 (d) 16
List-I [EC-2000 : 1 Mark]
A. Flash converter
Q.6 For the 4-bit DAC shown in the figure, the output
B. Dual slope converter
voltage Vo is,
C. Successive approximation converter
1k 7k
List-II
1. requires a conversion time of the order of a +15 V
few seconds. –
R R R Vo
+
2. requires a digital-to-analog converter.
–15 V
3. minmizes the effect of power supply 2R 2R 2R 2R 2R
interference.
4. requires a very complex hardware. 1V 1V

5. is a tracking A/D converter. (a) 10 V (b) 5 V

[EC-1995 : 1 Mark] (c) 4 V (d) 8 V
Q.2 The advantages of using a dual slope ADC in a [EC-2000 : 2 Marks]
digital voltmeter is that, Q.7 The number of comparators required in a 3-bit
(a) its conversion time is small. comparator type ADC is
(b) its accuracy is high. (a) 2 (b) 3
(c) it gives output in BCD format.
(c) 7 (d) 8
(d) it does not require a comparator.
[EC-2002 : 1 Mark]
[EC-1998 : 1 Mark]
Q.8 The minimum number of comparators required
Q.3 The resolution of a 4-bit counting ADC is to build an 8-bit flash ADC is
0.5 Volts. For an analog input of 6.6 Volts, the
(a) 8 (b) 63
digital output of the ADC will be
(c) 255 (d) 256
(a) 1011 (b) 1101
[EC-2003 : 1 Mark]
(c) 1100 (d) 1110
[EC-1999 : 1 Mark] Q.9 The circuit shown in the figure is a 4-bit DAC.

Q.4 An 8-bit successive approximation analog to R

R
digital converter has full scale reading of 2.55 V
and its conversion time for an analog input of 2R
–
1 V is 20 µs. The conversion time for a 2 V input
4R +
will be
(a) 10 µs (b) 20 µs 8R R
(c) 40 µs (d) 50 µs
[EC-2000 : 1 Mark]
 94 Electronics Engineering Digital Electronics

The input bits 0 and 1 are represented by 0 and

5 V respectively. The op-amp is ideal, but all the (c)
resistances and the 5 V inputs have a tolerance
of ±10%. The specification (rounded to the
nearest multiple of 5%) for the tolerance of the (d)
DAC is
[EC-2006 : 2 Marks]
(a) ± 35% (b) ± 20%
(c) ± 10% (d) ± 5% Statement for Linked Answer Questions (12 and 13):
[EC-2003 : 2 Marks] In the Digital-to-Analog converter circuit shown in the
figure below, VR = 10 V and R = 10 k .
Q.10 A digital system is required to amplify a binary- R R R i 2R
VR
econded audio signal. The user should be able
to control the gain of the amplifier from a
2R 2R 2R 2R R
minimum to a maximum in 100 increments. The
minimum number of bits required to encode, in
–
straight binary, is Vo
+
(a) 8 (b) 6
(c) 5 (d) 7
[EC-2004 : 1 Mark] Q.12 The current ‘i’ is
Q.11 A 4-bit D/A converter is connected to a free- (a) 31.25 µA (b) 62.5 µA
running 3-bit UP counter, as shown in the (c) 125 µA (d) 250 µA
following figure. Which of the following [EC-2007 : 2 Marks]
waveforms will be observed at Vo?
Q.13 The voltage Vo is
1k
(a) –0.781 V (b) –1.562 V
Q2 D3 (c) –3.125 V (d) –6.250 V
–
D2
Vo
[EC-2007 : 2 Marks]
+
Q1 D1
Statement for Linked Answer Questions (14 and 15):
Q0 D0 1k
Clock In the following circuit, the comparator output is logic
3-bit 4-bit
counter DAC ‘1’ if V1 > V2 and is logic ‘0’ otherwise. The D/A
conversion is done as per the relation.
In the figure shown above, the ground has been
shown by the symbol .
3
VDAC = 2 n 1 bn Volts, where b3(MSB), b2, b1 and
n=0
b0(LSB) are the counter outputs. The counter starts from
(a) the clear state.
VDAC 4-bit D/A
converter
+5 V Binary 2 Digit
to LED
CLK BCD Display
4-bit
(b) – upcounter
+

Vin = 6.2 V

Clock
 GATE Previous Years Solved Paper 95

Q.14 The stable reading of the LED display is

(a) 06 (b) 07 Vo
(c) 12 (d) 13
(c)
[EC-2008 : 2 Marks]

Q.15 The magnitude of the error between VDAC and

Vin at steady-state, (in Volts) is,
(a) 0.2 (b) 0.3
(c) 0.5 (d) 1.0 Vo

[EC-2008 : 2 Marks] (d)

Q.16 The output of a 3-stage Johnson (Twisted-ring)

counter is fed to a digital-to-analog (D/A)
converter as shown in the figure below. Assume [EC-2011 : 2 Marks]
all states of the counter to the unset initially.
Q.17 Consider a 4-bit D to A converter. The analog
The waveform which represents the D/A
value corresponding to a digital signals of
converter output Vo is
values 0000 and 0001 are 0 V and 0.0625 V
respectively. The analog value (in Volts)
Vref D/A corresponding to the digital signal 1111 is ___ .
Converter Vo [EC-2015 : 1 Mark]
D2 D1 D0 Q.18 In an N-bit flash ADC, the analog voltage is fed
simultaneously to 2 N – 1 comparators. The
Q2 Q1 Q0 output of the comparators is then encoded to a
Johnson binary format using digital circuits. Assume that
Clock Counter
the analog voltage source Vin (whose output is
being converted to digital format) has a source
resistance of 75 as shown in the circuit
diagram below and the input capacitance of
Vo each comparator is 8 pF.
The input must settle to an accuracy of 1/2 LSB
even for a full scale input change for proper
(a)
conversion. Assume that the time taken by the
thermometer to binary encoded is negligible.
–

Vref 255 +

Vo Thermometer
Digital
– code to binary
output
conversion
(b) Vref 2 +

Vin –

Vref1 +
 96 Electronics Engineering Digital Electronics

If the flash ADC has 8-bit resolution, which one Q.20 An 8-bit unipolar (all analog output values are
of the following alternatives is closest to the positive) Digital-to-Analog Converter (DAC)
maximum sampling rate? has a full scale voltage range from 0 V to 7.68 V.
(a) 1 mega samples per second If the digital input code is 10010110 (the left
(b) 6 mega samples per second most bit is MSB), then the analog output voltage
(c) 64 mega samples per second of the DAC (Rounded off to one decimal place)
is _______ Volts.
(d) 256 mega samples per second
[EC-2021 : 1 Mark]
[EC-2016 : 2 Marks]

Q.19 A 10-bit D/A converter is calibrated over the

full range from 0 to 10 V. If the input to the D/A
converter is 13 A (in hex), the output (rounded
off to three decimal places) is ______ V.
[EC-2020 : 1 Mark]

Electronics & Electrical Engineering

GATE Previous Years Solved Paper

A n swe rs & Expl a n a t i o n s

Answers
EC ADC and DAC

1. (A-4, B-3, C-2) 2. (b) 3. (d) 4. (b) 5. (c) 6. (b) 7. (c)

8. (c) 9. (a) 10. (d) 11. (b) 12. (b) 13. (c) 14. (d) 15. (b)

16. (a) 17. (0.9375) 18. (a) 19. (3.069)

Solutions
EC ADC and DAC

1. Sol. 4. (b)
A-4, B-3, C-2 Conversion time of successive approximate
ADC depends upon the number of bits only.
2. (b)
The advantage of using a dual slope ADC in a 5. (c)
digital voltmeter is its high accuracy. Number of comparators in a flash ADC is equal
to 2n – 1, where n = number of bits.
3. (d)
24 – 1 = 15
6.6
Vo = = 13.2 14
0.5
Binary equivalent = 1110
 GATE Previous Years Solved Paper 97

6. (b) I/2 R I/4 R I/8 R i = I/16 2R

VR
1 1 5 I/2 I/8
Vin at non-inverting terminal = + =
8 2 8 2R 2R 2R 2R R

Rf I/4 I/16
Vo = 1+ Vin –
R Vo
+
5
= 8× =5V
8
3
7. (c) I 1 × 10
then, i= = = 62.5 µA
16 16
2n –1 = 23 –1
13. (c)
8. (c)
Net current in inverting terminal of op-amp
2n – 1 = 28 – 1
= 255 I I 5I
= + =
4 16 16
9. (a) 5I
Vo = R×
R R R R 16
Vo = VR d3 + d2 + d1 + d0
R 2R 4R 8R
10 × 10 3 × 5 × 1 × 10 3
=
R 16
Vo = VR (Constant)
R = –3.125 V
Worst case tolerance in,
14. (d)
1.1 × 1.1
Vo = = 35% VDAC = 2–1 b0 + 20 b1 + 21 b2 + 22 b3
0.9
= 0.5 b0 + b1 + 2b2 + 4b3
10. (d) Counter output will start from 0000 and will
increase by 1 at every clock pulse.
2n 100
Table for VDAC is shown below:
n 7
b3 b2 b1 b0 VDAC
11. (b)
0 0 0 0 0
0 0 0 1 0.5
C/P 1 2 3 4 5 6 7
0 0 1 0 1
Counter 001 010 011 100 101 110 1000 0 0 1 1 1.5
0 1 0 0 2
Decoder 0001 0010 0011 1000 1001 1010 0000 0 1 0 1 2.5
1 2 3 8 9 10 0 0 1 1 0 3
0 1 1 1 3.5
D2 is connected to ground and Q2 to D3.
1 0 0 0 4
12. (b) 1 0 0 1 4.5
1 0 1 0 5
Using concept of convert division rule:
1 0 1 1 5.5
VR
I= 1 1 0 0 6
R 1 1 0 1 6.5
10 1 1 1 0 7
= = 1 mA
10 k 1 1 1 1 7.5
98 Electronics Engineering Digital Electronics

Counter will increase till Vin > VDAC. So, when 19. Sol.
VDAC = 6.5 V, the comparator output will be zero Given, n = 10
and the counter will be stable at that reading. VFS = 10 V
The corresponding reading of LED display is 13. Input voltage = (13A)16 = (314)10
Output voltage = Resolution × Decimal
15. (b)
equivalent of input
Magnitude of the error between VDAC and Vin at
10
steady state Vo = 10
× 314 = 3.069 V
= 6.5 – 6.2 2 1
= 0.3 V 20. (4.5)

16. (a) FSO = 7.68 V (28 – 1) step size = 7.68

Sequence of Johnson counter is 7.68

Step size = Volts
255
Q2 Q1 Q0 D2 D1 D0 V0 Digital input = 100101102 = 9616 = 15010
0 0 0 0 0 0 0 Analog output,
1 0 0 1 0 0 4 7.68
1 1 0 1 1 0 6 Vo = 15010 × = 4.5 Volts
255
1 1 1 1 1 1 7
0 1 1 0 1 1 3
0 0 1 0 0 1 1
0 0 0 0 0 0 0

17. Sol.
Step size = 0.0625 V
Decimal equivalent = 15
Analog output = 15 × 0.0625
= 0.9375 Volts