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CoursVHDL 01process

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6 views38 pages

CoursVHDL 01process

Uploaded by

avenirsirene
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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• Process is the primary concurrent VHDL

statement used to describe sequential


behavior.
• The statements inside the process will
executed sequentially in zero time.
• Variables can only be used inside a process.
• Sequential statements do not generate
sequential hardware always.
• We can use sequential statements to make
combinatorial hardware.
• What are the changes of the signals that my
process is sensitive to?
• What are the signals controlled by the process
to execute again the sequence of its
statements.
• The execution of a process statement consists
of the repetitive execution of its sequence of
statements.
The sensitivity list
• All the input ports used inside the process
must be appear in the sensitivity list.
• Static Signal names can be used as parameters
of the sensitivity list.
• Outputs can not be part of the sensitivity list,
because we cannot read outputs!
The sensitivity list
• Using sensitivity list to control signals.
• It is possible to use the command wait on
rather than the sensitivity list.
• Only
• For generating combinational logic circuits
• Example:
Process (a,b,c)
Begin
z <=( a and b) xor c;
End process;
 Here, the process waits either a, b, or c
changes to be recalled again
• If statement evaluates each condition in order.
• If statement can be nested.
• The result hardware can be different.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity IF_else is
port( A,B,C,D: in std_logic;
S: in std_logic_vector (2 downto 0);
o: out std_logic
);
end IF_else;

architecture Behavioral of IF_else is

begin
process (A,B,C,D,S)
begin
if S(0)='1' then
o<=A;
elsif S(1)='1' then
o <=B;
elsif S(2)='1' then
o <=C;
else
o <=D;
end if;
end process;

end Behavioral;
• Avoiding using more than three levels of
if_else statements because the path from the
input to the output will be more and more
longer.
• Longer the path  longer the delay (time)
• If statement produces priority-encoded logic
•  Multiplexer in cascade.
• Case statement is a series of parallel checks to
check a condition
• Statements following each ‘when’ clause is
evaluated, only if the choice value matches the
expression value.
Does not result a priority logic strucutre unlike if
statement.
Case statement produces parallel logic (one Mux)
Corresponds to the « with ..0 select » in concurrent
statements.
• Generate synchronous logic.
• Example: D-Flip Flop
• Any assignment under a clock generates a
Flip-Flop.
• “if” of clk has not an else.
• We can use if above “if” of the clock
• We can put if clk inside a previous “if else “
block
Any assignment under a clock generates a Flip-Flop.
(clk’ event and clk=‘1)  Rising_edge(clk)
These are the same!
• Using if clk inside previous if-else block 
okay!
• With nested if_else statement
• Using Variables inside a clocked process:
 They used as temporal connections that
need values immediately.
We have to consume all variables inside the
process itself.
We use := to assign variables.
<= is used for ports and signals.
• Remember:
 Any assignment under if (clk’event) generates
a FF.
Assignments
Assignments above or outside the if
(clk’event) do not generate FFs.
What hardware will generate the
below code?
AND --- OR --Mux21—Flip Flop
• Incompletely specified conditional expression
infers A LATCH.
• We have to add the else satement if it is
needed.
• If we do not add a nedded else, then, we get a
latch
• Most Synthesizer tools provide warnings
when latches are inferred.
• If we need of that latch design, then, it is okay.
WARNING:Xst:737 - Found 1-
bit latch for signal <Z>.
Latches may be generated
from
incomplete case or if
statements.
We do not recommend the
use of latches in
FPGA/CPLD designs, as they
may lead to timing problems.

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