Analog & Digital VLSI

Design

BITS Pilani
EEE / INSTR F313
Pilani Campus
 BITS Pilani
Pilani Campus

Switch Logic design styles—

input to S/ D/ G terminal
Adv.----Less inputcapacitances , reduced transistor count.
Threshold voltage Drop
in logic propagation
VDD VDD
PUN
Good S D
high pass VDD

D 0  VDD S 0  VDD - VTn

VGS
CL CL

PDN
Good
VDD  0 VDD  |VTp|
Low pass
VGS
D CL S CL
VDD

S D

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

NMOS–
good low pass/ bad high pass

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

NMOS Transistors
in Series/Parallel Connection
• Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high

A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

84
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
NMOS–
good low pass/ bad high pass

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Threshold voltage Drop
in logic propagation
VDD VDD
PUN
Good S D
high pass VDD

D 0  VDD S 0  VDD - VTn

VGS
CL CL

PDN
Good
VDD  0 VDD  |VTp|
Low pass
VGS
D CL S CL
VDD

S D

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

PMOS Transistors
in Series/Parallel Connection

PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

PMOS–
good high pass/ bad low pass

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Pass Transistor Logic (PTL)
Single rail

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Level restoration- refresh for 1 Vt
loss in signal for single rail output

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Analog & Digital VLSI
Design

BITS Pilani
EEE / INSTR F313
Pilani Campus
 BITS Pilani
Pilani Campus

Switch Logic design styles—

input to S/ D/ G terminal
Adv.----Less inputcapacitances , reduced transistor count.
Differential/ Dual rail CPL

only 4 transistors

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Threshold drop– need level restoration

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Delay of N stage PT chain

elmore  delay  formula

t p  R1C  (R1  R2 )C2  (R1  R2  R3 )C3      (R1  R2  R3    Rn )Cn

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Rnmos, Rpmos-- variation

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Delay reduction--- add
Repeaters

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Optimum no. of Repeaters in
long PT chain for minimum delay
Total no. of sections of PT segments in entire length =N
No. of PT after which buff is placed= M,
Total such M-segment in entire length =(N/ M)
Total no. of buffers=(N/ M) -1
R/ C------resistance/ capacitance of NMOS/ PMOS
D  ( ) M segment   1 BUFF
DELAY-- N N
M M 
N  M (M  1)RC   N 
D( )  1  BUFF
M  
2   M 
D
M
 0,  M segment  BUFF

2  BUFF
M 
0 .7 R C
BITS Pilani, Pilani Campus
 BITS Pilani
Pilani Campus

Transmission Gate design

Therefore, the transmission gate functions as a “closed” switch when
CONTROL = 1 and operates as an “open” switch when CONTROL = 0, serving
as a voltage-controlled switch. The symbol representing the gate of the PMOS
FET is indicated by a bubble.
 A B S F

Mux 0/1 0/1 0 B’

0/1 0/1 0 B’
0/1 0/1 1 A’
0/1 0/1 1 A’
Transmission Gate (TG)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Resistance plot
Resistance of transmission
gate

BITS Pilani, Pilani Campus

 BITS Pilani
Pilani Campus

TG circuits
 BITS Pilani
Pilani Campus

Long TG chain
How to reduce delay?
Delay of N stage TG chain
Same size repeaters

elmore  delay  formula

t p  R1C  (R1  R2 )C2  (R1  R2  R3 )C3      (R1  R2  R3    Rn )Cn

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Break the chain----
insert Repeaters

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Optimum no. of buffers
-in TG chain for minimum delay
Total no of TG ( or wire segments in wire ) in chain=N
No. of [TG] per section=M
Total no. of sections=N/ M
Total no. Of buffers=[N/M ]-1
R/ C------resistance/ capacitance of TG
DELAY :
N  M (M 1)RTG CTG   N 
D  ( )    1 BUFF
M  2  M 
D
 0
 M
2 BUFF
M 
0 .7 R TG C T G
BITS Pilani, Pilani Campus
Optimum size S of repeaters ,
optimum no. N in a PT/ TG chain

Derive yourself

BITS Pilani, Pilani Campus

 BITS Pilani
Pilani Campus

Clocked/ Dynamic logic

Differential output Level
restoration- 2 i/p XOR gate

Only 6 transistors

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

FULL ADDER

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Full Adder design--- Full static CMOS

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Full adder design--- CPL

22 TRANSISTORS

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Full adder design--- CPL
Alternate view

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Delay of N stage TG chain
Same size repeaters

elmore  delay  formula

t p  R1C  (R1  R2 )C2  (R1  R2  R3 )C3      (R1  R2  R3    Rn )Cn

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Break the chain----
insert Repeaters

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Optimum no. of buffers
-in TG chain for minimum delay
Total no of TG ( or wire segments in wire ) in chain=N
No. of [TG] per section=M
Total no. of sections=N/ M
Total no. Of buffers=[N/M ]-1
R/ C------resistance/ capacitance of TG
DELAY :
N  M (M 1)RTG CTG   N 
D  ( )    1 BUFF
M  2  M 
D
 0
 M
2 BUFF
M 
0 .7 R TG C T G
BITS Pilani, Pilani Campus
Optimum size S of repeaters ,
optimum no. N in a PT/ TG chain

Derive yourself

BITS Pilani, Pilani Campus

 Analog & Digital VLSI
Design

BITS Pilani
EEE / INSTR F313
Pilani Campus
 BITS Pilani
Pilani Campus

Clocked/ Dynamic logic

 BITS Pilani
Pilani Campus

Precharge - Evaluate Logic

Dynamic circuits
Using NMOS logic
Precharge - Evaluate Logic

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Precharge/ evaluation

• Clk=0 precharge
• Output charges

• Clk=1 evaluation
• Output conditionally discharges

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Using PMOS logic

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Using PMOS logic
Pre-discharge/ evaluation

• Clk=1 pre-discharge
• Output charges

• Clk=0 evaluation
• Output conditionally discharges

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Salient features-
• Non Ratioed —only one path is on at a time

• Inverting Logic

• Less Transistors (N+2)

• No glitches (Only 1→0 Transition)

• Low NML

• Low Input Cap. (less g)

• High switching activity

• High clk .power

BITS Pilani, Pilani Campus
PE gate- VTC

Vm
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Power Issues (high???)
1. Power dissipated by clk circuit is huge
2. Static Power dissipated by dynamic gate is less---
due to no glitches, less capacitance, but has high P0->1

BITS Pilani, Pilani Campus

Advantages of PE logic

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Logical Effort
Dynamic (PE) gate

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

PE CMOS gate---- logical effort, g
𝑝𝑢 2
=
𝑝𝑑 1

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

PE CMOS gate---- parasitic effort, p
𝑝𝑢 2
=
𝑝𝑑 1

𝟒 𝟓 𝟔
𝒑= 𝒑𝒊𝒏𝒗 𝒑= 𝒑𝒊𝒏𝒗 𝒑= 𝒑𝒊𝒏𝒗
𝟑 𝟑 𝟑

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Dynamic logic
Drawbacks
Dynamic Logic ---
Data loss Possibility

Due to -

• Subthreshold current

• Charge sharing

• Clock feedthrough / back gate coupling

BITS Pilani, Pilani Campus

Charge leakage
Subthreshold Current ---

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Charge Sharing

• Charge sharing/ Charge leakage/ clock feed

through -- degraded logic levels

• Remedy----Extra keeper MOSFET -- Tphl more

BITS Pilani, Pilani Campus

Charge Sharing ---
(evaluation----degrades logic ‘1’at output)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Charge Sharing

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Charge Sharing
(degrades logic ‘1’ at output)

Change in Vout

= - ½ Vdd

If Ca≈CL

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Back gate coupling, / clock
feedthrough

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Back gate coupling, / clock
feedthrough

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Back Gate Coupling,
clock feed-through

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Back Gate Coupling, clock
feed-through

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Clock Feed-through
(degrades logic ‘1’at output)

𝐶𝑃
∆𝑉𝑜𝑢𝑡 = × 0−5
1
𝐶𝐿1 + 𝐶𝑃
−𝐶𝑃
∆𝑉𝑜𝑢𝑡 = × 5
1
𝐶𝐿1 + 𝐶𝑃
1
𝐶𝑃 = 𝐶𝐿1
3

∆𝑽𝑶𝑼𝑻𝟏 = −𝟎. 𝟐𝟓 × 𝟓 = −𝟏. 𝟐𝟓𝑽

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Remedy
For Charge Sharing, charge Leakage/ clk feedthrough –
keeper mosfet
Weak PMOS

Keeper mosfet—should not interfere with output

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 BITS Pilani
Pilani Campus

Cascading problem in dynamic

--leads to malfunctioning circuit
Precharge/ Evaluation

• Clk=0 precharge
• Output charges

• Clk=1 evaluation
• Output conditionally discharges

BITS Pilani, Pilani Campus

Problem-

• Output tri-stated in evaluation phase

• E=1, F = 1→0,

• E cannot change (turn off ) instantaneously

• So Vout starts discharging

• VOH gets degraded

BITS Pilani, Pilani Campus

Example--- G= (A.B) +(C.D)

Logic ‘1’
degraded

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Remedy1—
Domino CMOS

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Domino logic- pipeline operation
Data moves one stage at a time

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Domino gate – 2 gates path--
logical/ parasitic effort

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Footless domino

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Footless Domino— LESS ‘g’

BITS Pilani, Pilani Campus

Logicimplementation-------Example---A.B +C.D+E

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

DOMINO CMOS using PMOS block

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Domino CMOS combining with static CMOS gates
condition---- even no. of static gates

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Compound DOMINO CMOS—
Dynamic logic + static logic

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

NP CMOS domino - implementation
Single cycle operation, 2 phase clocking scheme required

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956