IL Instruction Guide E
IL Instruction Guide E
________________________________________________________________________________________________________________
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Manual
Reference Guide
SAIA PCD
Table of contents
Page
1. Introduction
2. BIT Instructions
Page
3. WORD Instructions
Page
4. INTEGER arithmetic
Page
6. BLOCTEC Instructions
7. GRAFTEC Instructions
Page
Mode C 8-3
Mode D 8-4
Mode MM4 8-5
Mode S-Bus 8-6
PROFIBUS 8-7
Page
9. LAN2 Instructions
Notes
Please note:
To obtain the best performance from your SAIA PCD, closely follow the
guidelines for assembly, wiring, programming and commissioning given
in these manuals. In this way, you will also become one of the many en-
thusiastic SAIA PCD users.
Summary
PCD1/2 series PCD4 series PCD6 series
H ar dw ar e H ar dw a re H a r dw a re
PCD1 PC D 4 P CD6
PCD2
S er ie x x7 PC D4.H 1.. *)
PCD2.M250
U s e r's
G u id e
R eferen ce
Gui de
(P G3)
P C D 8 .P 1 ..
- S-Bus - LON
- PROFIBUS
- Remote I/O
In s ta llat io n
C o m p on e nts
fo r R S 4 8 5 -
N e tw o rk s
- PG4
- Modem
FUPLA/
KOPLA
function
families
• state-of-the-art technology
• compliance with standards
• ISO 9001 certification
• international approvals: e.g. Germanischer Lloyd,
United Laboratories (UL), Det Norske Veritas, CE mark ...
• choice of high-quality componentry
• quality control checks at various stages of production
• in-circuit tests
• run-in (burn-in at 85°C for 48h)
Despite every care, the excellent quality which results from this does
have its limits. It is therefore necessary, for example, to reckon with the
natural failure of components. For this reason SAIA-Burgess Electronics
Ltd. provides a guarantee according to the "General terms and conditions
of supply".
The plant engineer must in turn also contribute his share to the reliable
operation of an installation. He is therefore responsible for ensuring that
controller use conforms to the technical data and that no excessive stres-
ses are placed on it, e.g. with regard to temperature ranges, overvoltages
and noise fields or mechanical stresses.
If all these points are taken into consideration, the SAIA PCD will provi-
de you with a modern, safe programmable controller to control, regulate
and monitor your installation with reliability for many years.
1. Introduction
This Reference Guide describes in detail each instruction in the SAIA PCD family.
The instructions are grouped together by type of instruction to facilitate their
learning.
This guide is intented as a support to the "User's Guide" which gives a detailed
description of the "PCD Utilities" and the structured programming methods used
in the SAIA PCD.
Important
The instructions described in this guide are valid for:
PCD1 version V001 (and above)
PCD2 version V004 (and above)
PCD4.Mxx0 version V005 (and above)
PCD4.Mxx5 version V00C (and above)
PCD6.M5 version V004 (and above)
PCD6.M1/M2 version V009 (and above)
PCD Utilities version V2.0
If you have a PCD with an older version certain instructions can differ or be
non-existant.
One or more pages are provided for each instruction of the SAIA PCD.
Top Line For each instruction, the mnemonic(s) and the instruction name are shown on the
top line.
Usage Shows how the instruction is used and gives the type and range of each operand.
An "[X]" after the mnemonic means that indexed addressing is possible by adding
the optional 'X' to the mnemonic (eg: STHX, INCX).
For indexed addressing, the indexed operand(s) is marked with a "(i)".
Practice A practical example which shows the use of the instruction in a suitable context.
Typographic Conventions:
(i) When indexed addressing is possible (see [X]); the indexed operand(s)
is marked with a "(i)"
..... A series of "." in an example shows that this one can be continued by
yourself.
LABEL: In the examples, all the labels are represented with their name
followed by a ':'; this is necessary if you use another editor than
SEDIT.
If you use SEDIT do not put this ':' after the label.
<> Angle brackets enclose texts or expression which should not be typed
verbatim, but replaced by any text or valid expression.
Medium control codes [mc] are used to select the element type
Flags
Flags are 1 bit storage cells which can be treated like outputs, e.g. they can be set
or reset, and can be interrogated as to their state. Accordingly flags are used for
the storage of any suitable information.
When a Timer or Counter contains a non-zero value its state is High (H),
when its content is zero its state is Low (L)
Registers
A register is a 32 bits storage cell which can hold any information, in binary,
decimal, hexadecimal, floating-point. You can perform arithmetical operations on
them, transfer of information (from or to: inputs, outputs, flags, timers, counters,
registers).
Registers can hold positive as well as negative values.
Constants
Several types of constant are used (see next page).
teXt
Texts are ASCII strings that can be memorized in the PCD for output on a serial
line.
Data Block
A "Data Block" is an area of memory which is used for storing 32-bit data, which
can be transfered to and from Registers, Timers and Counters
1.2 Constants
There are several types of constants used in PCD instructions, the valid range
depends on the instruction.
K constants are NOT allowed for the LOAD instructions (LD, LDH and LDL).
Binary
End the value with a 'Q', eg. 1001Q, 11111111Q. Max 12 bits.
Decimal
Default, no special format.
Hexadecimal
End the hex value with an 'H', eg. ABCDH, 1234H, DEADH.
ASCII
Enclose the ASCII character in inverted commas, eg. 'A', 'z'.
Floating point
Include a '.' and/or an exponent 'E', eg. 1.2, 12E-1.
Range (FFP) is 2.710505E-20 to - 9.223371E+18.
K Constants
Used where a medium control code (mc) is required; this is never used for the
LOAD instructions (LD, LDL, LDH)
To show it is a constant, the mc type 'K' is used.
Binary, decimal, hexadecimal or Ascii values can be given, eg. K 10, K 11Q,
K FFH, K 'A',
The Error flag can be set High (and Low) by any instruction which is executed
with invalid data.
P Positive High if result of arithmetic instruction is positive
N Negative High if result of arithmetic instruction is negative
(the P flag is always the inverse of the N flag)
Z Zero High if the result of arithmetic instruction is 0
E Error High if an instruction cannot be executed
(set High on Overflow, Underflow or
Conversion)
Accumulator
Since the processor "reads" one instruction line after the other, it follows, that it
can only interrogate one element after the other as to its signal state (H or L). In
order to process a complete linkage (Linkage: section of program consisting of
several instruction lines; it normally begins with a start instruction and ends with
an action instruction. Each line in a linkage depends on the result of the previous
one) up to an action instruction, the existing intermediate result of the linkage
must be stored in the Accumulator (ACCU).
At the end of the linkage the end result is present in the ACCU (0 or 1). On the
basis of this result the corresponding element (e.g. an output) is either not
activated (ACCU = 0) or activated (ACCU = 1)
Notes
2. BIT Instructions
Bit instructions work with the Accumulator, Inputs, Outputs, Flags and the state of
Timers or Counters.
Notes
Description The ACCU is set to the logical state of the addressed element.
This is the start of a new linkage line.
The previous linkage results are cleared with the start instruction; simultaneously
the signal state "H" of the addressed element I, O, F, T, C will be read and the
result stored in the ACCU.
I7 O 32
I 12 O 40
Description The ACCU is set to the inverted logical state of the addressed element. This is the
start of a new linkage line.
The previous linkage results are cleared with the start instruction; simultaneously
the signal state "L" of the addressed element I, O, F, T, C will be read, inverted
and the result stored in the ACCU.
I8 O 33
Timer T 15 O 34
Description The ACCU is AND linked with the logical state of the addressed element, the
ACCU is set to the result.
I3 I6 O 32
I3
I6 & O 32
STH I 3 ; If input 3 is H
ANH I 6 ; and input 6 is H
OUT O 32 ; Then set output 32
; Else reset output 32
Description The ACCU is AND linked with the inverted logical state of the addressed element,
the ACCU is set to the result.
I2
O 32
I3 &
I4
STH I 2 ; If input 2 is H
ANL I 3 ; AND input 3 is L
ANH I 4 ; AND input 4 is H
OUT O 32 ; Then set output 32
; Else reset output 32
ORH OR HIGH
Description The ACCU is OR linked with the logical state of the addressed element, and the
ACCU is set to the result.
OR instructions are used for parallel linkages of elements.
The total linkage begins with a start (STH or STL); each additional parallel partial
linkage begins with an ORH.
If a parallel partial linkage is detected as successful (ACCU=1) then the logical
states of the following partial linkages no longer exercise any influence on the
result of this total linkage.
Example STH I5 ; If I 5 is H
ORH I 13 ; OR I 13 is H
; Then ACCU = 1, Else ACCU = 0
Flags ACCU set to the result.
See also ORL.
Practice
I5 O 32
I 13
I5
I 13 >1 O 32
STH I 5 ; If input 5 is H
ORH I 13 ; or input 13 is H
OUT O 32 ; Then set output 32
; Else reset output 32
I0 I1
I0
I2 O 32 I1 &
I2
>1 O 32
I3 I4 I3
I4 &
COB 0 ; COB Header
0
STH I 0 ; If input 0 is H
ANH I 1 ; and input 1 is H
ORH I 2 ; or input 2 is H
ORH I 3 ; or input 3 is H
ANH I 4 ; and input 4 is H
OUT O 32 ; Then set output 32
; Else reset output 32
It can be seen from the above example that the OR- instruction has "priority"
over AND.
I0 I2 O 32
I1
I0 F 10
I1
F 10 I2 O 32
STH I 0 ; If Input 0 is H
ORH I 1 ; or input 1 is H
OUT F 10 ; Then set flag 10
; Else reset flag 10
STH F 10 ; If Flag 10 is H
ANH I 2 ; and input 2 is H
OUT O 32 ; Then set output 32
; Else reset output 32
ORL OR LOW
Description The ACCU is OR linked with the inverted logical state of the addressed element,
and the ACCU is set to the result. OR instructions are used for parallel linkages of
elements.
Example STH I3 ; If I 3 is H
ORL I7 ; OR I 7 is L
; Then ACCU = 1, else ACCU = 0
Flags ACCU set to the result.
See Also ORH.
XOR EXCLUSIVE OR
Description The ACCU is XOR linked with the logical state of the addressed element, the
ACCU is set to the result.
With the XOR instruction the signal states of two elements can be compared with
one another. If they are identical, the ACCU content is 0; where they are
different, it is 1.
I8
I5 =1 O 37
STH I 8 ; If input 8 is H
XOR I 5 ; XOR input 5 is H
OUT O 37 ; Then set output 37
; Else reset output 37
I8 I5 O 37
L L L
L H H
H L H
H H L
CMP R 99 ; Compare R 99
TR 5 'x' ; with ASCII character 'x'
ACC Z ; If equal Then ACCU is set H
; (copy of Z flag in ACCU)
ST 1 STXT 1
10
TR 6 ....
Description Sets the Output or Flag to the state of the ACCU. If the ACCU is High then
the Output or Flag is set High. If the ACCU is Low, then the Output or Flag
is set Low.
.
Usage OUT[X] element (i) ; O 0-8191, F 0-8191
I7 O 32
I2 O 35
O 40
F 777
STH I 7 ; If input 7 is H
OUT O 32 ; Then set output 32
; Else reset output 32
STH I 2 ; If input 2 is H
OUT O 35 ; Then set output 35, else reset output 35
OUT O 40 ; set output 40, else reset output 40
OUT F 777 ; set flag 777, else reset flag 777
Description The Output or Flag is set High only if the ACCU is High. If the ACCU is Low,
nothing is done.
An output or flag set with a SET-instruction remains set (H) until it is reset again
by a RES-instruction.
SET and RES are generally used in sequentially programs (GRAFTEC)
IST
TR
ST
TR STH I 7 ; input = on ?
Description The Output or Flag is set Low only if the ACCU is High.
If the ACCU is Low, nothing is done.
Description The state of the Output or Flag is complemented (inverted) only if the ACCU is
High. If the ACCU is Low, nothing is done
Note:
This instruction is mainly used for the activation of the "WATCHDOG".
The "COM O 255" instruction must be placed in a cyclic program. Care must be
taken that this instruction is only executed when the ACCU is H. (The "ACC H"
instruction can be placed before the instruction or the instruction "COM" can be
placed directly after the COB instruction)
I0
I0 O 32
O 32
Description The Output or Flag is set High after the delay given in the 2nd operand only if the
ACCU is High. The delay is in timebase units, as set by the DEFTB instruction.
SETD and RESD are designed for the use in sequentially programs (GRAFTEC).
The use of these instructions give simpler structures because the end of the delay
must not be waited.
(If these instructions are used in BLOCTEC programs; they must always be
combined with a DYN instruction. Without the DYN instruction, another timer
will be activated on each program loop causing the ERROR flag to be set after the
16th loop when all the timers will be used.)
The operands cannot be supplied as Function Block parameters.
TR
STH ... ; condition to continue
Description The Output or Flag is set Low after the delay given in the 2nd operand only if the
ACCU is High. The delay is in timebase units, as set by the DEFTB instruction.
SETD and RESD are designed for the use in sequentially programs (GRAFTEC).
The use of these instructions give simpler structures because the end of the delay
must not be waited.
(If these instructions are used in BLOCTEC programs; they must always be
combined with a DYN instruction. Without the DYN instruction, another timer
will be activated on each program loop causing the ERROR flag to be set after the
16th loop when all the timers will be used.)
The operands cannot be supplied as Function Block parameters.
TR
STH ... ; condition to continue
3. WORD Instructions
These instructions all work with Registers.
Registers contain binary, decimal, BCD or floating point values.
For floating point values, the floating point instructions must be used.
Notes
Description The addressed Register, Timer or Counter is loaded with the given 32-bit value.
For Timers and Counters:
• the operation is done only if the ACCU is High.
• cannot be loaded with negative or floating point values.
(only decimal, Hex, ASCII or binary values)
• if a timer is loaded, the timer starts immediately.
• The state of a timer or counter is H when it contains a non-zero
value else its state is L
For Registers:
• the operation is independent of the ACCU state.
• the value can be a decimal, Hex, ASCII or floating point value.
Binary values are post-fixed with a 'Q' or 'Y'.
Hex values are post-fixed with an 'H'.
Floating point values must contain a decimal point '.' or an exponent "E6".
ASCII values are enclosed in single quotes 'a', 'A'.
Since the value is 32-bits, three program lines are used for the whole instruction.
Description Loads the lower 16 bits (0-15) of a Register, Timer or Counter with a 16-bit value
(0-65535); the upper 16 bits are always set to 0.
LDL (and LDH, Load High) allow 16-bit constants to be passed as Function Block
parameters, or loaded directly.
LDH loads the upper 16 bits.
Using these instructions, a 32-bit value can be loaded. To load all 32 bits, LDL
must be executed first, because this sets the upper 16 bits to 0.
Values can be loaded in decimal, hex, binary or ASCII, NOT floating point.
Description Loads the upper 16 bits (16-31) of a Register, the lower 16 bits are not affected.
LDH (and LDL, Load Low) allow 16-bit constants (0-65535) to be passed as
Function Block parameters, or loaded directly. Using these instructions, a 32-bit
value can be loaded. To load all 32 bits, LDL must be executed first, because this
sets the upper 16 bits to zero (0).
Values can be loaded in decimal, hex, ASCII or binary, NOT floating point.
LDH cannot be used to load Timers or Counters, where the upper 16 bits cannot
be loaded separately.
FB 0 ; FB Header
LDL R 0 ; Load the lower 16 bits of Register 0
= 1 ; with the 1st parameter (lower 16 bits)
LDH R 0 ; Load the upper 16 bits of Register 0
= 2 ; with the 2nd parameter (upper 16 bits)
EFB
Description The logical state of an Input, Output or Flag, or the contents of a Register, Timer
or Counter, or a constant, can be loaded into the Display register.
This value is displayed on the PCD8.P100 Programming Unit in decimal.
It is useful as an error code or status display.
I0
Set
I1
Up
O 32
I2 Down
C 50
STH I 0 ; If input 0 is H
LD C 50 ; Then load counter 50 with 5
5
; Else do nothing
STH I 1 ; If input 1 goes H
DYN F 1 ; (Edge detection)
INC C 50 ; Then counter 50 incremented by 1
; Else do nothing
STH I 2 ; If input 2 goes H
DYN F 2 ; (Edge detection)
DEC C 50 ; Then counter 50 decremented by 1
; Else do nothing
STH C 50 ; If counter 50 content >> 0
OUT O 32 ; Then set output 32
; Else reset output 32
DSP C 50 ; Display counter 50
ECOB
0 0
Zero Flag
Counter status
0 0
min - min -
Zero Flag
Negative Flag
Positive Flag
Error Flag
Indexed Addressing
It is frequently necessary for series of inputs, outputs, flags,... to be dealt with in
the same way (for example resetting of all retentive flags or registers). In cases
like this, long programs can be drastically shortened with the help of address
indexing.
Each COB or XOB has its own Index register.
This register is used for indexed addressing, where the contents of the Index
register is added to the operand value to provide the actual address.
Indexing instructions are always ended with an 'X', for Example STHX, BITIX.
The Index register can be loaded or saved, incremented up to a given limit, or
decremented down to a given limit.
Description The current Index register is loaded with the supplied constant (K 0-8191) or the
contents of the indicated Register.
NOTE: The value range of the Index register is 0..8191 (13 bits).
If a value > 8191 is entered then the Index is set to 8191 and the XOB 12 is
called.
If a value < 0 is entered then the Index register is set to 0 and the XOB 12 is
called.
COB 0
0
Description The current Index register is compared to the value of the operand (supplied K
constant or the contents of a Register).
If the Index register is less than this value, the Index register is incremented and
the ACCU is set 1.
If the Index register is equal or greater than the value of the operand, the Index
register is NOT incremented and the ACCU is set 0.
If the value in the operand is > 8191 or < 0 then XOB 12 is called.
The current Index register is compared to the value of the operand (K constant or
Description
the contents of a Register).
If the Index register is greater than this value, the Index register is decremented
and the ACCU is set 1.
If the Index register is equal or less than the value of in the operand (constant or
Register contents), the Index register is NOT decremented and the ACCU is set 0.
If the value in the operand is > 8191 or <0 then XOB 12 is called.
SEI SEI
INI DEI
8191 8191
End value Initial value
ACCU ACCU
Description The value in the current Index register is stored in the given Register.
It can be re-loaded into the Index register using the RSI instruction.
The Index register is not changed.
Example STI R 100 ; Stores the Index register contents in Register 100
Flags Unchanged.
See Also RSI
Description Loads the Index register with the contents of the given Register.
The value in the Register will typically be an Index register value saved by the STI
instruction.
The maximum value the Register should contain is 8191, only the lower 13 bits are
loaded.
If a parameter <0 or > 8191 is entered then the XOB 12 is called.
Example RSI R 100 ; Loads the Index register with the contents of Register 100.
Flags Unchanged.
See Also STI, SEI
Practice
Q = bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D = digit 9 8 7 6 5 4 3 2 1 0
N = nibble 7 6 5 4 3 2 1 0
B = byte 3 2 1 0
W = word 1 0
L = long word 0
Example Move the Highest nibble (N7) from Register 100 to the Lowest nibble (N0) of
Register 101
; Before: R100: 1111 1010 1010 1010 1010 1010 1010 1010
R101: 0001 0001 0001 0001 0001 0001 0001 0001
MOV R 100
N 7
R 101
N 0
; After: R100: 1111 1010 1010 1010 1010 1010 1010 1010
R101: 0001 0001 0001 0001 0001 0001 0001 1111
Flags Unchanged.
See Also COPY, GET, PUT, LD, LDH, LDL
Description The COPY, GET and PUT instructions are all related.
They are used for the indexed transfer of data between Registers, Timers and
Counters. In each case, an entire Register, Timer or Counter is copied.
For COPYX, the contents of the first operand is copied into the second, BOTH
are indexed.
SEI K0 R 10 R 50
loop: COPYX R 10 R 11 R 51
R 50
... R 12 R 52
INI K4 R 13 R 53
JR H loop R 14 R 54
Description The COPY, GET and PUT instructions are all related.
They are used for the indexed transfer of data between Registers, Timers and
Counters. In each case, an entire Register, Timer or Counter is copied.
For GETX, the contents of the first operand is copied into the second, only the
first operand is indexed.
In addition, the GET instruction allows the transfer from the Texts / Data Blocks
to the Registers/Timers/Counters.
SEI K0 R 10 R 50
loop: GETX R 10 R 11
R 50
... R 12
INI K4 R 13
JR H loop R 14
Similarly, GET[X] can transfer the data items present in a Data Block to the
R/T/C's until the end of the Data Block.
A DATA BLOCK is an area of user memory where large numbers of Registers,
Timers or Counters can be saved and read at run-time. Data Blocks can be used
for storing values which are specific to a process to liberate R/T/C's for use by
other processes.
If the instruction tries to read from a Text or Data Block which doesn't exist then
XOB 13 (Error flag set) is called. If the indexed Text or Data Block number is
greater than 3999 then XOB 12 is called (Index Register Overflow)
Texts and Data Blocks are numbered 0..3999 but because they share the same
area of memory, they cannot share the same number. For Example, if Data Block
10 is defined then Text 10 is unavailable.
A Text can be defined as normal with a maximum possible length of 3069
characters.
A Data Block can hold a maximum of 383 data items, where a data item is a
register or timer or counter.
Note: It is forbidden to have <254> or <255> in the first byte of a normal Text. If
the PCD contains EPROM memory then the Data Blocks and Texts can only be
read (GET instruction).
Examples:
DB 100 [10] ; Data Block number 100 of 10 data item
; all values initialised to zero.
Example 1:
Data Block as declared in the source program:
DB 100 [5] 0h,1h,2h,0a5a5a5a5h,720h
Instruction:
GET DB 100 ; Transfer Data Block 100
R 1000 ; into Regiters 1000 and consecutive.
Result:
Register Value in Hex
1000 00000000
1001 00000001
1002 00000002
1003 a5a5a5a5
1004 00000720
Example 2:
Text as declared in the source program:
TEXT 100 "THIS IS A TEXT 123"
Instruction:
GET X 100 ; Transfer Text 100
R 1000 ; into Registers 1000 and consecutive.
Result:
Register Value in ASCII Value in Hex
1000 THIS 54484953
1001 IS 20495320
1002 A TE 41205445
1003 XT 1 58542031
1004 23 32332020
Description The COPY, GET and PUT instructions are all related.
They are used for the indexed transfer of data between Registers, Timers and
Counters. In each case, an entire Register, Timer or Counter is copied.
For PUTX, the contents of first operand is copied to the second, only the
destination (second) operand is indexed.
In addition, the PUT instruction allows the transfer from the Registers / Timers /
Counters to the Texts / Data Blocks.
SEI K0 R 10 R 50
loop: PUTX R 10 R 51
R 50
... R 52
INI K4 R 53
JR H loop R 54
Example 1:
Data Block as declared in the source program:
DB 100 [5] ; Initial values are zero
Contents of Registers:
Register Value in Dec
1000 00000001
1001 00000002
1002 00000003
1003 01234567
1004 00000720
Instruction:
PUT R 1000 ;Transfer Register 1000 and consecutive
DB 100 ; into Data Block 100.
Example 2:
Text as declared in the source program:
TEXT 100 [17] ; A text of 17 spaces
Contents of Registers:
Register Value in ASCII Value in Hex
1000 THIS 54484953
1001 IS 20495320
1002 A TE 41205445
1003 XT 1 58542031
1004 23 32332020
Instruction:
PUT R 1000 ; Transfer Registers 1000 and consecutive
X 100 ; into Text 100
Description This instruction enables the indexed data transfer of individual values from a Data
Block or a Text to Registers, Timers or Counters; and vice versa.
The 1st operand is the Data Block (or Text) containing the value to transfer.
The 2nd operand is the position of the value inside the Data Block (or Text);
this position can be given as a constant or indirectly via a Register.
The 3rd operand is the destination Register, Timer or Counter
The 1st operand is the Register, Timer or Counter containing the value to transfer
(source).
The 2nd operand is the destination Data Block (or Text).
The 3rd operand is the position inside the Data Block (or Text) where the value
must be transferred, this position can be given as a constant or indirectly via a
Register.
Remark:
The length of the Data Block is dependent of the PCD memory type:
Memory Address Maximum length of 1 DB
Standard DB 0..3999 383 values
Extended DB 4000..7999 16383 values
Practice From Data Block 4010, the 4 values from position 2..5 are copied to Registers
100..103.
…. Source Destination
LD R 999 Pos Data Block Registers
2 0 12345
SEI K 0 1 67845612
LOOP: TFRX DB 4010 2 33 33 R 100
R 999 3 1024 1024 R 101
R 100 4 R 102
0 0
INC R 999
5 89 89 R 103
INI K 3
6 13
JR H LOOP
… 7 90
…. Destination Source
LD R 999 Registers Data Block Pos
2 12345 0
SEI K 0 67845612 1
LOOP: TFRX R 100 R 100 2
33 33
DB 4010
R 101 1024 1024 3
R 999
INC R 3 R 102 0 0 4
JR H LOOP R 103 89 89 5
… 13 6
90 7
Description This instruction enables the indirect indexed data transfer of individual values
from a Data Block or a Text to Registers, Timers or Counters; and vice versa.
This instruction does not work in parametrised mode
The 1st operand specifies that the source is a Data Block or a Text and the
variable reg1 is a register number containing the address of the DB or Text.
The 2nd operand is the position of the value inside the Data Block (or Text); this
position can be given as a constant or indirectly via a Register.
The 3rd operand specifies the type of the destination (R or T|C). The variable reg2
is a Register number which contains the destination number of the media.
The 1st operand specifies the type of the source (R or T|C). The variable reg1 is a
Register number which content the destination address of the media.
The 2nd operand specifies the type of the destination (DB or Text) and the
variable reg2 is a register number containing the address of the destination.
The 3rd operand is the position inside the Data Block (or Text) where the value
must be transfered, this position can be given as a constant or indirectly via a
Register.
Remark:
The length of the Data Block is dependent of the PCD memory type:
Memory Address Maximum length of 1 DB
Standard DB 0..3999 383 values
Extended DB 4000..7999 16383 values
Examples Transfer the element at position 10 od Data Block 4000 to Register 4095.
LD R 100 ; Initialisation of the DB address
4000
LD R 101 ; Initialisation of the Register address
4095
TFRI DB 100 ; Transfer DB
K 10
R 101
Transfer the Counter 1000 to the position 50 of Data Block 4000
LD R 100 ; Initialisation of the DB address
4000
LD R 101 ; Initialisation of the position
50
LD R 102 ; Initialisation of the Counter address
4095
TFRI C 102 ; Transfer Counter
DB 100
R 101
Flags The Zero (Z) and Sign (P or N) flags are set according to the value copied.
See Also TFR, PUT, GET
BITI BIT IN
Description Moves a sequence of binary bits from Inputs, Outputs, Flags, a Timer or a Counter
into a Register.
The 1st operand is the number of bits to be moved (1-32).
The 2nd operand is the source (I, O, F, T or C).
The 3rd operand is the destination Register.
If the source are Inputs, Outputs or Flags, the source address given is the lowest
element of the sequence.
The LOWEST element becomes the LEAST SIGNIFICANT bit in the destination
Register.
This is contrary to the SAIA PCA.
Description Moves a sequence of binary bits from Inputs, Outputs, Flags, a Timer or a Counter
into a Register.
The 1st operand is the number of bits to be moved (1-32).
The 2nd operand is the source (I, O, F, T or C).
The 3rd operand is the destination Register.
If the source are Inputs, Outputs or Flags, the source address given is the lowest
element of the sequence.
The LOWEST element becomes the MOST SIGNIFICANT bit in the destination
Register.
This is the same as the SAIA PCA.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Destination: Register 0
Destination: Register 0
Description Moves a sequence of binary bits from a Register to corresponding Outputs, Flags
or bits in a Timer or Counter.
The 1st operand is the number of bits to transfer (1-32).
The 2nd operand is the source Register number.
The 3rd operand is the destination Outputs, Flags, Timer or Counter.
If the destination are Outputs or Flags, the address given is that of the lowest
element in the sequence.
The LEAST SIGNIFICANT bit of the Register is moved to the LOWEST element.
This is contrary to the SAIA PCA
ECOB
Description Moves a sequence of binary bits from a Register to corresponding Outputs, Flags
or bits in a Timer or Counter.
The 1st operand is the number of bits to transfer (1-32).
The 2nd operand is the source Register number.
The 3rd operand is the destination Outputs, Flags, Timer or Counter.
If the destination are Outputs or Flags, the address given is that of the lowest
element in the sequence.
The LEAST SIGNIFICANT bit of the Register is moved to the HIGHEST element.
This is the same as the SAIA PCA.
Source: Register 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITO 32
R 10
O 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Source: Register 0
BITOR 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 10
O 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIGI DIGIT IN
Description Moves Binary Coded Decimal (BCD) digits from Inputs, Outputs or Flags into a
Register.
A BCD digit is 4 bits (eg. 4 Inputs), which represents a decimal digit (0-9).
The 1st operand is the number of digits to move (1-10).
The 2nd is the base Input, Output or Flag.
The 3rd operand is the destination Register.
The lowest addressed Input, Output or Flag becomes the least significant bit of the
least significant digit in the destination Register.
This is contrary to the PCA.
3 Digits BCD 5 9 1
Input addresses: 27 26 25 24 23 22 21 20 19 18 17 16 LSB
Inputs activated: 0 1 0 1 1 0 0 1 0 0 0 1
BCD Binary
R 123 = 591 0 1 0 0 1 0 0 1 1 1 1
The format inside the register is always binary.
Description Moves Binary Coded Decimal (BCD) digits from Inputs, Outputs or Flags into a
Register.
A BCD digit is 4 bits (eg. 4 Inputs), which represents a decimal digit (0-9).
The 1st operand is the number of digits to move (1-10).
The 2nd is the base Input, Output or Flag.
The 3rd operand is the destination Register.
The lowest addressed Input, Output or Flag becomes the most significant bit of the
most significant digit in the destination Register.
This is the same as the PCA.
3 Digits BCD 7 8 5
MSB
Input addresses: 16 17 18 19 20 21 22 23 24 25 26 27
Input values: 800 400 200 100 80 40 20 10 8 4 2 1
Inputs activated: 0 1 1 1 1 0 0 0 0 1 0 1
BCD Binary
R 123 = 785 0 1 1 0 0 0 1 0 0 0 1
The format inside the register is always binary.
Binary BCD
Flag values: 80 40 20 10 8 4 2 1
MSD LSD
Binary BCD
Flag addresses: 50 51 52 53 54 55 56 57
Flag values: 80 40 20 10 8 4 2 1
MSD LSD
Description The contents of the 1st Register is logically ANDed with the contents of the
second register, and the result is placed in the 3rd Register.
bit 31 bit 0
R 11 1 0 1 1 0 0 1 0 1 1 0
AND
R 12 1 1 1 0 0 1 1 0 0 1 1
R 13 1 0 1 0 0 0 1 0 0 1 0
OR OR REGISTERS
Description The contents of the 1st Register is logically ORed with the contents of the 2nd
Register, and the result is placed in the 3rd Register.
bit 31 bit 0
R 1 1 0 1 1 0 0 1 0 1 1 0
OR
R 2 1 1 1 0 0 1 1 0 0 1 1
R 3 1 1 1 1 0 1 1 0 1 1 1
Description The contents of the 1st Register is Exclusive ORed with the contents of the 2nd
Register, and the result is placed in the 3rd Register.
bit 31 bit 0
R 1 1 0 1 1 0 0 1 0 1 1 0
EXOR
R 2 1 1 1 0 0 1 1 0 0 1 1
R 2 0 1 0 1 0 1 0 0 1 0 1
Description The contents of the 1st Register is inverted (1's complement) and stored in the 2nd
Register.
R 100 0 0 0 1 1 0 0 1 1 0 0
( R 106 )
R 105
SHIU R 100 R 104
R 105 R 103
R 102
R 101
0 R 100
NOTE:
This instruction use one register more than those specified: the register which
follows the end of the block is also used.
0 R 105
R 104
SHID R 100 R 103
R 105 R 102
R 101
R 100
( R 99 )
NOTE:
This instruction use one register more than those specified: the register which
precedes the start of the block is also used.
R 105
R 104
ROTU R 100 R 103
R 105 R 102
R 101
R 100
R 105
R 104
ROTD R 100 R 103
R 105 R 102
R 101
R 100
Description The contents of the addressed Register is shifted left by the number of bits given
by the second operand.
The content of the ACCU (1 or 0) is shifted in from bit 0 (the least significant bit),
n times.
At the end of the operation, the ACCU is set to the status of the last bit shifted out
of the Register
from Accu
31 0
1 0 1 1 0 1 1 0 1 1 0 0 0 0 1 1 R 10 before
to Accu
SHIL R 10
4
0 1 1 0 x x x x 1 1 0 0 0 0 0 0 R 10 after
Accu was 0 Accu = 1
1 0 1 1 0 1 1 0 1 1 0 0 0 0 1 1 R 10 before
to Accu
SHIL R 10
4
0 1 1 0 x x x x 1 1 0 0 1 1 1 1 R 10 after
Accu was 1 Accu = 1
SHIL by 4 bits
Description The contents of the addressed Register is shifted right by the number of bits given
by the second operand.
The contents of the ACCU (1 or 0) is shifted in from bit 31 (the most significant
bit), n times.
At the end of the operation, the ACCU is set to the status of the last bit shifted out
of the Register.
from Accu
31 0
1 0 1 1 0 1 1 0 1 1 0 0 0 0 1 1 R 10 before
to Accu
SHIR R 10
4
0 0 0 0 1 0 1 1 x x x x 1 1 0 0 R 10 after
Accu was 0 Accu = 1
1 0 1 1 0 1 1 0 1 1 0 0 0 0 1 1 R 10 before
to Accu
SHIR R 10
4
1 1 1 1 1 0 1 1 x x x x 1 1 0 0 R 10 after
Accu was 1 Accu = 1
SHIR by 4 bits
Description The contents of the addressed Register is rotated left by the number of bits given
in the 2nd operand.
The most significant bit 31 is copied into the least significant bit 0.
The ACCU is set to status of the last bit that was rotated.
31 0
1 0 1 1 0 1 1 0 1 1 0 0 0 0 1 1 R 10 before
ROTL R 10
4
0 1 1 0 x x x x 1 1 0 0 1 0 1 1 R 10 after
Accu = 1
(Last bit that was rotated)
ROTL by 4 bits
Description The contents of the addressed Register is rotated right by the number of bits given
in the 2nd operand.
The least significant bit 0 is copied into the most significant bit 31.
The ACCU is set to status of the last bit that was rotated.
31 0
1 0 1 1 0 1 1 0 1 1 0 0 0 0 1 1 R 10 before
ROTR R 10
4
0 0 1 1 1 0 1 1 x x x x 1 1 0 0 R 10 after
to Accu Accu = 0
(Last bit that was rotated)
ROTR by 4 bits
4. INTEGER arithmetic
For floating point values, the Floating point instructions must be used.
INTEGER format
Notes
ECOB
SUB R 10 ; R 12 = R 10 - R 11
R 11
R 12
ECOB
MUL R 50 ; R 4000 = R 50 * R 55
R 55
R 4000
ECOB
Example DIV R 20 ; R 20 is
K 1000 ; divided by 1000
R 21 ; the result is placed in Register 21
R1 ; and the remainder in Register 1
Flags The Zero (Z) and Sign (P or N) flags are set according to the result.
The Error (E) flag is set on divide by zero.
See Also FDIV
Practice Read two numbers, divide them and put the result in another register.
The two numbers come from BCD encoders (2 digits) on inputs 16 to 23,
respectively 24 to 31
PB 99
SET O 47 ; Alarm if division by zero (output 47)
EPB
ECOB
Compares the contents of the 1st Register or constant with the contents of the 2nd
Description
Register or constant. This is done by subtracting the 2nd value from the 1st value,
the Status flags are set according to the result.
The contents of the Registers are unchanged
NOTE:
Floating point values are stored in Registers in a special binary format, using the
value as an integer will yield incorrect results.
Mixing integer and floating point values in arithmetic operations gives invalid
results. The integer values must first be converted to floating point with the IFP
instruction.
Floating point values can be converted to integer with the FPI instruction.
The floating point format is based on 32 bits with the following format:
m m m m m m m m m m m m m m m m mm mm m mm ms e e e e e e e
31 0
Notes
Description Converts the integer value in the specified Register to floating point format.
The 2nd operand indicates the power of ten to which the integer is to be raised,
this controls the position of the decimal point.
For example, if the power of ten is +3, the contents of the Register is multiplied by
1000 (103), and the result is stored in the Register in floating point format.
If the Register contained 12, the result would be 12000.00.
If the conversion is not possible (number too big or too small), the Error flag is set
and no conversion is done.
Description Converts the floating point value in the specified Register to integer format.
The 2nd operand indicates the power of ten to be used in the conversion.
The result is the integer of the result of the Register contents multiplied by 10 to
the power of the 2nd operand.
For example, if the Register contains 1234.56 and the power of ten is -2, the
integer result will be 12.
If the conversion is not possible, the Error flag is set and nothing is done.
Description Adds the contents of the 1st Register to the contents of the 2nd Register, and
stores the result in the 3rd Register.
The Registers must contain valid floating point format values.
Description Subtracts the contents of the 2nd Register from the contents of the 1st Register,
and stores the result in the 3rd Register.
Both Registers must contain valid floating point format values.
Description Multiplies the contents of the 1st Register by the contents of the 2nd Register, and
stores the result in the 3rd Register.
Both Registers must contain valid floating point format values.
Example FMUL R 20 ; R 0 = R 20 * R 30
R 30
R0
Flags The Zero (Z) and Sign (P or N) flags are set according to the result.
The Error (E) flag is set on overflow, e.g. if the result is greater than
4.611686 E+18
See Also MUL
Description Divides the contents of the 1st Register by the contents of the 2nd Register, and
stores the result in the 3rd Register.
Divide by zero sets the Error flag, and the operation is not performed.
NOTE: Since Floating Point arithmetic is more exact, there is no remainder
Description Stores the square root of the contents of the 1st Register into the 2nd Register. If
the 1st Register contains a negative value, the Error flag is set, and the square root
of the absolute (+ve) value is taken.
Description Compares the contents of the 1st Register with the contents of the 2nd Register
and sets the Status flags according to the result.
Neither of the Registers are altered.
Both Registers must contain valid floating point format values.
Z P N
Value 1 = Value 2 High High Low
Value 1 > Value 2 Low High Low
Value 1 < Value 2 Low Low High
The Error (E) flag is set low
See Also CMP
Note NEVER compare Floating Point values for equality, use > or < to avoid
accuracy errors !
Description The sine of the contents of the 1st Register is stored in the 2nd Register.
The 1st Register must contain a floating point value in RADIANS in the range
of ± 106
Description The cosine of the contents of the 1st Register is stored in the 2nd Register.
The 1st Register must contain a floating point value in RADIANS in the range
of ± 106.
Description The arc tangent of the contents of the 1st Register is stored in the 2nd Register.
The 1st Register must contain a valid floating point value in RADIANS.
The result is in the second Register will range from -π/2 to + π/2
Description 'e' to the power of the contents of the 1st Register is stored in the 2nd Register.
The Register must contain a valid floating point format value.
Example FEXP R0 ; R 1 = eR 0
R1
Flags The Zero (Z) flag is set according to the result, the Negative (N) flag is always set
Low (P = 1).
The Error (E) flag is set on overflow .
See Also FPI, IFP
Description The natural log of the contents of the 1st Register is stored in the 2nd Register.
The 1st Register must contain a valid floating point format value.
If the natural log of a negative value is taken, the Error flag is set and the log of
the absolute (+ve) value is taken.
Example FLN R1 ; R 2 = ln R 1
R2
Flags The Zero (Z) and Sign (P or N) flags are set according to the result.
The Error (E) flag is set if the "ln" of zero or a negative value is taken
See Also FEXP
Description The absolute value (converted to positive if it is negative) of the 1st Register is
stored in the 2nd Register. The 1st Register must contain a valid floating point
format value.
6. BLOCTEC Instructions
Bloctec is a structured programming method which breaks a program down into
separate blocks of code.
A Cyclic Organisation Block (COB) is a main block of code which will typically
call Program Blocks (PB), which in turn will call Function Blocks (FB).
At least one COB (COB 0) must be present in the program.
COBs can call PBs or FBs (with optional parameters).
PBs and FBs can themselves call any other PB or FB up to a nesting depth of 7.
The operand(s) of these instructions cannot be supplied as Function Block
parameter(s).
PB Program Block
EPB End of Program Block
CPB Call Program Block
CPBI Call Program Block Indirect
FB Function Block
EFB End of Function Block
CFB Call Function Block
If these instructions are used in a program which uses GRAFCET then serious
problems can arise.
If they are not used with the utmost care: these instructions can cause at best, the
user program to become slow, or at worst, cause a complete desynchronisation of
the GRAFTEC and a CRASH.
Avoid to use these instructions within a GRAFTEC structure.
Notes
The ACCU is always set High (1) at the start of each COB.
Description Ends the current COB. The next COB (if present) will begin execution.
A COB body must always be terminated by an ECOB instruction.
Level 4 exceptions:
Priority level 4 is the highest priority, only XOB 0 and 8 can interrupt execution of
another XOB.
Level 3 exceptions:
If a level 2 or 3 exception occurs during execution of a lower priority XOB, then it
will be treated directly after execution of the current level XOB.
XOB 20/25/11 have been given a higher priority level so that if the XOB is
provoked during execution of a lower or equal priority then it will be executed
directly after completion of the current XOB.
Level 2 exceptions:
XOB 1 Power down in extension rack
The voltage monitor in the supply module of an extension rack (PCD 2 or PCD6)
detected an excessive drop in voltage.
In this case all Outputs of the extension rack are set low within 2ms and XOB 1 is
invoked.
If Outputs from this "dead" extension rack continue to be handled (set, reset or
polled) by the user program in any CPU, XOB 4 and/or XOB 5 are also invoked.
(Only PCD4). XOB 1 will be called once up to 250 ms after detection of the error.
Level 1 exceptions:
Any level 1 exception which occurs during another exception will never be
treated.
PB PROGRAM BLOCK
Description Marks the beginning of a Program Block (PB), a subroutine without parameters.
Example PB 26 ; Start of PB 26
... ; Body of PB 26
...
...
EPB ; End of PB 26
Flags The ACCU is set High (1) at the start of the PB
See Also EPB, CPB, FB, User's Guide
Example PB 0 ; Start of PB 0
... ; Body of PB 0
...
...
EPB ; End of PB 0
Flags The ACCU is restored to the state it had before the PB was called
See Also PB, CPB, User's Guide
COB 0
0
...
STH I 15 ; IF Input 15 is High
CPB H 20 ; THEN call PB 20
CPB L 25 ; ELSE call PB 25
...
ECOB
PB 20
.....
EPB
PB 25
.....
EPB
Example CPBI L 10 ; If the ACCU is Low (0), then the PB whose number
; is contained in R 10 is called
Flags The Error flag is set if the given Register contains an invalid PB number or if the
PB does not exist.
The ACCU is set High (1) at the start of the PB.
In the program from where the PB is called, the ACCU is restored to the state it
has before the PB was called
See Also PB, EPB, CFB, User's Guide
FB FUNCTION BLOCK
Example FB 0 ; Start of FB 0
...
STH =1 ; FB Parameter reference
...
EFB ; End of FB 0
Flags The ACCU is set high (1) at the start of the FB
See Also EFB, CFB, User's Guide
Practice Computation of the formula: Z = X * (X+Y)
COB 7
0
...
STH I 1 ; If Input 1 goes H
DYN F 1
CFB H 25 ; Then R107 = R100 * (R100+330)
R 100 ; Parameter 1 (X)
K 330 ; Parameter 2 (Y)
R 107 ; Parameter 3 (Z)
Description Ends the current Function Block (FB). Returns to the instruction following the
Call Function Block (CFB) instruction.
Example FB 0 ; Start of FB 0
... ; Body of FB 0
...
...
EFB ; End of FB 0
Flags The ACCU is restored to the state it had before the FB was called.
See Also FB, CFB, User's Guide
Description Conditionally or unconditionally forces the program to switch to the next COB.
If the condition code is not satisfied, the NCOB instruction is ignored.
Wait loops can be programmed using NCOB without interfering with the
execution of any other COBs.
For every wait loop, an NCOB instruction should be inserted. This allows
"parallel" execution of COBs.
Condition
blank Always (no condition code)
H If Accumulator = H (1)
L If Accumulator = L (0)
P If Positive flag = H (Negative flag = L)
N If Negative flag = H
Z If Zero flag = H
E If Error flag = H
If these instructions are used in a program which uses GRAFCET then serious
problems can arise.
If they are not used with the utmost care: these instructions can cause at best, the
user program to become slow, or at worst, cause a complete desynchronisation of
the GRAFTEC and a CRASH.
Avoid to use these instructions within a GRAFTEC structure.
Condition
blank Always (no condition code)
H If Accumulator = H (1)
L If Accumulator = L (0)
P If Positive flag = H (Negative flag = L)
N If Negative flag = H
Z If Zero flag = H
E If Error flag = H
Condition
blank Always (no condition code)
H If Accumulator = H (1)
L If Accumulator = L (0)
P If Positive flag = H (Negative flag = L)
N If Negative flag = H
Z If Zero flag = H
E If Error flag = H
If these instructions are used in a program which uses GRAFCET then serious
problems can arise.
If they are not used with the utmost care: these instructions can cause at best, the
user program to become slow, or at worst, cause a complete desynchronisation of
the GRAFTEC and a CRASH.
Avoid to use these instructions within a GRAFTEC structure.
Description Conditionally or unconditionally allows a COB that was stopped by the SCOB
instruction to resume execution.
If the condition is not satisfied, the COB is not resumed.
CCOB does not cause the COB to be executed immediately, but allows it to be
executed the next time it is scheduled.
Condition
blank Always (no condition code)
H If Accumulator = H (1)
L If Accumulator = L (0)
P If Positive flag = H (Negative flag = L)
N If Negative flag = H
Z If Zero flag = H
E If Error flag = H
If these instructions are used in a program which uses GRAFCET then serious
problems can arise.
If they are not used with the utmost care: these instructions can cause at best, the
user program to become slow, or at worst, cause a complete desynchronisation of
the GRAFTEC and a CRASH.
Avoid to use these instructions within a GRAFTEC structure.
Description Restarts any COB, conditionally or unconditionally, from the given program line.
This instruction can be used within any COB or XOB.
If the condition is not satisfied, the RCOB instruction is ignored.
The 1st operand is the COB number to be restarted.
The 2nd operand is the program line number to restart from. The line number is an
offset from the start of the COB, it is NOT an absolute program line number.
Condition
blank Always (no condition code)
H If Accumulator = H (1)
L If Accumulator = L (0)
P If Positive flag = H (Negative flag = L)
N If Negative flag = H
Z If Zero flag = H
E If Error flag = H
If these instructions are used in a program which uses GRAFCET then serious
problems can arise.
If they are not used with the utmost care: these instructions can cause at best, the
user program to become slow, or at worst, cause a complete desynchronisation of
the GRAFTEC and a CRASH.
Avoid to use these instructions within a GRAFTEC structure.
Notes:
7. GRAFTEC Instructions
SAIA GRAFTEC is a self-documenting programming method for step-by-step
processes.
SB Sequential Block
ESB End of Sequential Block
TR Transition
ETR End of Transition
Notes
SB SEQUENTIAL BLOCK
Example SB 10 ; Start of SB 10
... ; Body of SB 10, will contain STs and TRs.
ESB ; End of SB 10
Flags Unchanged.
See Also ESB, CSB, RSB, IST, ST, TR, User's Guide
Example SB 10 ; Start of SB 10
... ; Body of SB 10, contains STs and TRs.
ESB ; End of SB 10
Flags The ACCU is restored to the state it had before the SB was called
See Also SB, ST, TR, User's Guide
If the restart must take place in simultaneous branches (parallel programs), the
"RSB" instruction will contain as many additional lines as steps to be restarted.
Condition :
blank Always (no condition code)
H If Accumulator = H (1)
L If Accumulator = L (0)
P If Positive flag = H (Negative flag = L)
N If Negative flag = H
Z If Zero flag = H
E If Error flag = H
Description The Initial Step defines the first Step to be executed when a Sequential Block (SB)
is called.
Every SB must have at least one Initial Step.
In all other respects the Initial Step is the same as any other Step (see ST).
IST is followed by a list of incoming (I) and outgoing (O) Transitions.
ST STEP
Example ST 10 ; Step 10
I 9 ; Incoming from Transition 9
O 10 ; Outgoing to Transition 10
... ; Body of Step
EST ; End of Step
Flags The ACCU is set High (1) at the start of the ST
See Also EST, IST, TR, SB, User's Guide
Example ST 0 ; Start of ST 0
I 25 ; Incoming from Transition 25
O 47 ; Outgoing to Transition 47
... ; Body of ST 0
EST ; End of ST 0
Flags Unchanged.
See Also ST, TR, SB, User's Guide
TR TRANSITION
With OR branching, the order of handling of the parallel TRs is set by the order of
the outgoing Transitions defined in the preceding Step.
TRs can only appear inside SBs.
Example TR 0 ; Start of TR 0
I 12 ; Incomming from Step 12
O 14 ; Outgoing to Step 14
... ; Body of TR 0
ETR ; End of TR 0
Flags Unchanged.
See Also TR, ST, SB, User's Guide
Notes
Before any communications is done, the SASI instruction must be executed for
each serial channel (up to 4).
This will configure the channels operating mode and baud rate.
Each channel can be run in a different mode and at different speeds.
Each channel also has its own reception and transmission buffers.
The serial channels control lines (CTS, RTS, DSR, DTR and DCD) can be read or
written (SICL, SOCL).
SCON allows to open or close a virtual PROFIBUS channel. Communication via
the LAN 1 is also possible after the SCON instruction has been executed.
Notes
MODE C
Character or Text mode:
• Single characters from a Register or a Text are output.
• Single characters can be received and transferred into a Register.
• Often used to communicate with a terminal or printer.
MC0
Mode C without automatic handshaking
The user must control by himself the control signals with the SICL and SOCL
instructions.
MC1
Mode C using RTS and CTS handshaking
The RTS control signal is automatically positionned by the PCD in function of the
remaining space in the reception buffer.
The CTS signal influences the transmission of the PCD.
RTS Low Receive buffer contains more than 450
characters
High Receive buffer contains less than 300 characters
CTS Low Transmission is stopped
High Transmission is resumed
MC2
Mode C using Xon/Xoff protocol
This mode is similar to the RTS/CTS handshaking and is used when no control
signals are present (eg. current loop).
Two special characters Xon (CTRL/Q) and Xoff (CTRL/S) are sent to control the
transmission of the partner.
Receiver send when
Xoff Receive buffer contains more than 450
characters
Xon Receive buffer contains less than 300 characters
Transmitter receives then
Xoff Transmission is stopped
Xon Transmission is resumed
MC3
Mode C with Echo
This mode is used when communicating with a terminal; all received characters
are sent back to the terminal screen.
MC4
Mode C for RS485 interface
The MC4 mode is a low level mode which will set the RS485 driver/receiver in
drive mode only during the transmission of information (character/text) and will
default to receive at any other time.
MODE D
Uses telegrams in accordance with ISO 1745, IBM BSC and DIN 66019.
SAIA PCD specific data can be exchanged between two PCDs or between a
PCD and another intelligent system (IBM PC, etc) connected directly or via the
SAIA LAN 1.
The data can be the state of Inputs, Outputs or Flags; or the contents of Registers,
Timers or Counters.
<mode> Description
MD0 Mode D master
SD0 Mode D slave
The two modes are equivalent in functionality; the only difference is that when a
conflict occurs in the full-duplex communication, the Master station always has
priority over the Slave to repeat his request.
When communicating with a PC, the PCD must be set as Slave (SD0).
SAIA LAN 1
The D mode can be used with the SAIA LAN 1: in this case, the connection
between two stations can be achieved with the SCON instruction.
For more informations about the SAIA LAN 1 network, consult the
"SAIA LAN 1" manual.
MODE MM4
The MM4 mode allows the connection of the PCD on the COMPEX LAC/LAC2
Network. The LAC/LAC2 is an industrial local area network which enables the
easy connection of heterogeneous intelligent machines. The PCD is connected to
the network via a communicator which provides the required transmission
services.
This mode also supports the point to point connection between 2 PCDs.
For more information, consult the "Description of the LAC MM4 Protocol".
MODE SBUS
S-Bus is the name of an efficient communication protocol for the SAIA PCD
generation of controllers. It can be used for both point-to-point communications
and within a local master/slave network.
For point-to-point communications, any of the PCD's serial interfaces can be used.
At the physical level, an S-Bus network uses the RS 485 standard, via two-core
twisted and shielded cable.
<mode> Description
SM2 S-Bus master, with data mode
SM1 S-Bus master, with parity bit control
SM0 S-Bus master, no parity, with break character
SS2 S-Bus slave, with data mode
SS1 S-Bus slave, with parity bit control
SS0 S-Bus slave, no parity, with break character
GS2 S-Bus Gateway Slave, with data mode
GS1 S-Bus Gateway Slave, with parity bit control
GS0 S-Bus Gateway Slave, no parity, with break character
GM S-Bus Gateway Master
OFF De-initialize the serial line
For more information, consult the "Manual SAIA S-BUS" (ref 26/739).
PROFIBUS
PROFIBUS is the most successfull open Fiedlbus which can be used in wide range
of applications.
PROFIBUS-DP is optimized for high speed and has been tailored for
communication between automation systems and local peripherals. The usage of a
PROFIBUS-DP network (master or slave) requires a module PCD7.F750 or.
..F770.
EXOB
TEXT 10 "UART:4800,7,E,1;"
"MODE:MC0;"
"DIAG:F1000,R4000;"
Flags 1000 .. 1007 are used as diagnostics flags and Register 4000 is used as
diagnostic register.
TEXT 10 "UART:4800,7,E,1;MODE:MC0;DIAG:F1000,R4000;"
SASI Texts
A special definition text is needed for the Assign Serial Interface SASI instruction.
FORMAT:
TEXT xxxx "<uart_def>;"
"<mode_def>;"
"<diag_def>;"
["<rx_buf>;"]
["<tx_buf>;"]
where xxxx is any valid text number (0..3999)
The two last parameters are optional and only used in mode C:
<rx_buf> Receive buffer length (default = 1).
<tx_buf> Transmit buffer length.
MODE OFF
This mode differs from the standard SASI texts and is used when an interface
which has already been assigned must be re-assigned.
To avoid contention over the interfaces a semaphore mechanism is implemented.
When a serial interface is assigned a semahore is set so that if another assignation
is tried on the same serial interface then the error led will be set and the instruction
aborted. A serial interface can only be reassigned after it has been DESASI'd and
this is done by executing the instruction SASI with the following text:
<uart_def>
Defines the baud rate, data length, parity, number of stop bits, timeout
Format:
"UART:<baud-rate>,<char_len>,<parity>,<stop_bit>[,<timeout>];
<time_out>:
The time_out is irrelevant for Mode C.
The default timeouts are given in seconds and are function of the baud rate
In the other modes, the timeout is the time after which a message is repeated if the
partner receiving this messages does not give an acknowledgement.
If after 2 retries, the partner does not respond, he is declared "not responding".
Mode S-BUS:
The SBUS mode always use 11 bits (10 bits for data mode) to transmit one
character: there is no definition for <char_len>, <parity>, <stop_bit>.
"UART:<Baudrate>[,<Timeout>][,<TS-Delay>][,<TN-Delay>][,<Break-Length>];"
<baud_rate>: 110 .. 38.400
<time_out>: 10 .. 15000 ms
<TS delay>: 10 .. 15000 ms
<Break-Length>: 4 .. 15 char
TimeOut, TS-Delay, TN-Delay and Break-Length are optional and normally only
needed to be defined for special applications.
For more informations, consult the "Manual SAIA S-BUS" (ref. 26/739).
"UART:9600,7,E,1;"
9600 bauds, 7 data bits, Even parity, 1 stop bits and default timeout
Note: All characters must be typed in Upper case. When the text is between the
$SASI and $ENDSASI directives, the assembler tests the syntax of the text
and all characters are converted in uppercases.
<mode_def>
Defines the operating mode of the serial channel.
(1)
D Mode with LAN 1
When using the SAIA LAN 1, the PCA2.T9x interface uses a Register to inform
the PCD about the status of the connection. For more information, see the SCON
instruction.
(2)
SBUS Client
The address of the remote partner station is given in a Register.
(3)
MM4 <mode_opt> consists of the following:
<BCS_opt>,<trpartner>,<trinfo>,<repartner>,<reinfo>,<rechar>
<mode_opt> Value Description
<BCS_opt> 0 or 1 Block Check Sum (0: no BCS, 1: CRC-16
<trpartner> R xxxx Transmission partner station number
<trinfo> R xxxx Remote ACK information
<repartner> R xxxx Reception partner station number
<reinfo> R xxxx Receive information
<rechar> R xxxx Number of received characters
<diag_def>
Defines the communications diagnostics media.
Format:
"DIAG:<dia_elem>,<dia_reg>;"
Type Description
<dia_elem> O xxxx Base address of 8 consecutive Flags (or Outputs)
F xxxx
<dia_reg> R xxxx Address of a register for diagnostic
where xxxx is a valid address
The 8 Flags give informations about the status of the serial line. In case of error
when executing an serial communication instruction, more informations can be
obtained by examining the contents of the diagnostic register.
DIAGNOSTIC FLAGS
The Output or Flag address following the DIAG definition of the SASI texts is the
base address of 8 consecutive Outputs or Flags, used as follows:
RFUL
Receive Buffer Full
Mode
C RFUL is set High when the number of incoming characters in
the PCD Receive buffer is equal to or greater than the value of
rx_buf (Receive buffer length).
RFUL is Low when the number of characters remaining in the
receive buffer is less than the vale of rx_buf. The internal
reception buffer of the PCD always has room for 512
characters.
D RFUL is High when a correct data frame has been received.
MM4
SBUS RFUL is High when elements in the slave station have been
changed by the master station.
PROFIBUS High indicates that a write telegram has been received.
RDIA
Receiver Diagnostic
Mode
C RDIA is set High if the PCD detects an error during reception
D of a character; more information about the error can be
SBUS obtained by examining the contents of the Communication
MM4 diagnostic register. RDIA will be reset when all receiver
PROFIBUS diagnostic bits (0...15) in the diagnostic register are reset.
TBSY
Transmitter Busy
Mode
C TBSY is set High when the PCD transmits characters over the
serial line. TBSY is set Low when all characters from the
Transmission buffer have been transmitted
D TBSY is set High when the PCD is transferring data.
SBUS TBSY is set Low when the telegram has been acknowledged or
MM4 when the number of retries is reach.
PROFIBUS
TFUL
Transmit Buffer Full
Mode
C TFUL is set High when the number of characters remaining in
the PCD transmission buffer is greater than or equal to the
value declared for tx_buf (Transmit buffer length).
The TFUL is reset when the number of characters remaining in
the Transmit buffer is less than the value of TBUF.
D Not used
SBUS
PROFIBUS
MM4 TFUL is High when the acknowledgment has been received.
TDIA
Transmitter Diagnostic
Mode
C TDIA is set High when the PCD detects an error during
D transmission of a character; more information about the error
SBUS can be obtained by examining the contents of the
MM4 Communication diagnostic register. TDIA will be reset when all
PROFIBUS transmitter diagnostic bits (16...31) in the diagnostic register are
reset.
XBSY
Text busy
Mode
C XBSY is set High when the PCD transmits a text (STXT); when
all the text has been transmitted XBSY is reset. Note: XBSY is
reset at the beginning of the sending of the last character.
D XBSY is High when a connection via the LAN1 is open.
SBUS XBSY is low when the user has the permission to perform a
SASI OFF.
MM4 XBSY is High when there is activity on the LAC network
(STXM instruction)
PROFIBUS Cross busy / channel open
NEXE
Not executed
Mode
C
D If the PCD is unable to perform the requested operation, NEXE
SBUS is set High; further information about the error can be obtained
MM4 by examining the contents of the Communication diagnostic
register.
PROFIBUS Set High when, after 3 attemps, it has not been possible to
execute an instruction (STXM or RSXM). The flag is reset at
the next instruction.
The address of a Diagnostic Register must also be supplied with the DIAG
definition in the SASI text.
Normally all 32 bits of this Diagnostic Register are Low (0).
The register is to be reset to 0 by the user program.
If a bit is High (1) then its significance is the following (see relevant Mode):
Bit Description Cause MODE
C D SBUS MM4 PROFI
BUS
0 Overrun error Should never occur (notify SAIA)
1 Parity error Received a character with a parity error
2 Framing error Usually caused by an incorrect baud rate
3 Break Break in data line
4 BCC error Bad Block Check Code (or CRC-16)
5 S-Bus PGU status S-Bus PGU with Public Line modems
6 End of transmit Transmission ended SASI OFF
7 Overflow error Receive buffer overflow
8 Length error The telegram length is invalid
9 Format error Invalid telegram format
10 Address error Adress of ACK is invalid
11 Status error PCD in false status
12 Range error Invalid element address
13 Value error Error in the received value
14 Missing media err Address of media not defined or invalid
15 Program error Read from an empty receive buffer
LAN 1 not assigned or invalid station nb
16 Retry count Indicates the number of retries (in binary)
17
18 Transmission off Sending is suspended (CTS = L or XOFF)
19
20 NAK response NAK was received
21 No response No response was received after timeout
22 Multiple NAK NAK received after retries
23 TX buffer full No more space in transmit buffer
TS Delay No CTS after the TS Delay
24 Enquiry error No response to ENQ after retries
25 Format error Invalid definition text
Invalid command
26 Partner error A problem has occured with the partner
27 Network error A problem has occured on the network
28 Range error Invalid element address
29
30 Receive error Error occured
31 Program error Attempt to transmit when unauthorised
<rx_buf>
Defines the communication reception buffer limit.
Format:
"RBUF:<rbuf_len>;"
Value Description
<rbuf_len> 1.. 511 Receive buffer length
The Receive Buffer has always space for 512 x 8-bit characters.
For Mode C, the RBUF definition (1-511) indicates when to set the Receive
Buffer Full status (RFUL).
For the other modes, RBUF is not used.
<tx_buf>
Defines the communication transmission buffer limit.
Format:
"TBUF:<tbuf_len>;”
Value Description
<tbuf_len> 1.. 511 Transmission buffer length
Mode MC2 at 4800 Bds, 8 data bits, no parity,1 stop bit, using F0-F7 as diagnostic flags
and register R100 as diagnostic register; a receive buffer length of 25 characters:
TEXT 20 "UART:4800,8,N,1;MODE;MC2;DIAG:F0,R100;"
"RBUF:25;"
Mode SD0 (Slave) at 9600 Bds, 7 data bits, Even parity, 1 stop bit, F1000-F1007 as diagnostic
flags and register R4000 as diagnostic register:
TEXT 30 "UART:9600,7,E,1;MODE:SD0;DIAG:F1000,R4000;"
Mode MD0 (Master) at 9600 Bds, 7 data bits, Even parity, 1 stop bit, F1000-F1007 as
diagnostic flags and register R4000 as diagnostic register; the SAIA LAN1 is used
and a timeout of 3 sec is needed:
TEXT 40 "UART:9600,7,E,1,3000;"
"MODE:MD0,R1;"
"DIAG:F1000,R4000;"
Register R 1 is used to store the connection state of the LAN1.
Mode MM4 at 9600 Bds, 8 data bits, no parity,1 stop bit, Timeout: 300ms, no BCS, Registers
100..104 are used for the remote partner number, ....
F1000-F1007 are used as diagnostic flags and register R1000 as diagnostic
register:
TEXT 50 "UART:9600,8,N,1,300;"
"MODE:MM4,0,R100,R101,R102,R103,R104;"
"DIAG:F1000,R1000;"
Mode SBUS Parity mode (Master) at 9600 Bds, Register 555 is used to hold the partner number,
F8000-F8007 as diagnostic flags and register R4005 as diagnostic register:
TEXT 60 "UART:9600;MODE:SM1,R555;DIAG:F8000,R4005;"
Mode SBUS Paritiy mode (Slave) at 9600 Bds, F8000-F8007 are used as diagnostic flags and
register R4005 as diagnostic register:
TEXT 60 "UART:9600;MODE:SS1;DIAG:F8000,R4005;"
Mode SBUS Data mode(Slave) at 9600 Bds, Register 55 is used to hold the partner number,
F8000-F8007 are used as diagnostic flags and register R4005 as diagnostic
register:
TEXT 60 "UART:9600;MODE:SS2,R55;DIAG:F8000,R4005;"
The value and optionally the type of the symbol is inserted into the text. The
symbol is written outside the ASCII text segment in double quotes, and must be
separated from this or other symbols by a comma. After the symbol, an optional
field width and prefix type can be given.
Format:
Examples:
XOB 16
SASI 1
3999
TEXT 3999"UART:",BAUD,",7,E,1;MODE:MC0;"
"DIAG:",D_FLAGS.T,",",D_REG.T,";"
EXOB
"UART:9600,7,E,1;MODE:MC0;"
"DIAG:F500,R4095;"
New SASI with '$' (SASI text accepts $) see next page
can be used from the following firmware versions only:
$SASI, $ENDSASI
These assembler directives can be used to delimit texts which are used by the
SASI instruction. All texts enclosed within these directives will be checked by the
assembler and any errors detected.
Format:
$SASI
<SASI text definition>
...
$ENDSASI
Example:
XOB 16
...
SASI 0 ; Initialize serial channel 0
100 ; using text 100
...
EXOB
e.g.: "UART:$Ra,$Rb,$Rc,$Rd;MODE:$Re,$Rf;DIAG:F$Rg,R$Rh;"
Channel
Channel number to be initialised
This parameter can be given directly or indirectly:
0..3 Serial channel number
10..99 PROFIBUS channel number
R 0..4095 Register containing the channel number (0..3, 10..99)
Text_definition
This parameter is a register number (R 0..4095)
This register contents the address of a text containing where the interface
parameters are defined. Valid addresses for text:
0..3999 in standard memory
4000..7999 in extension memory
Example SASII 0 ; Initialises serial channel 0
R 1 ; using definition text address contained in R 1
Flags The Error (E) flag is set if the definition text is missing or invalid
See Also SASI texts
Description Loads the next ASCII character present in the Receive Buffer of the channel
given by the 1st operand into the Register given by the 2nd operand.
Up to 512 characters can be in the Receive Buffer. Each time SRXD is executed,
the next character is read.
If the Receive Buffer overruns (more than 512 characters), then there will be a
receive error (the RDIA flag and the corresponding status bit in the channels
Diagnostic Register are set).
Note: In simple applications, the error processing (above between brackets) can
be omitted.
Description The character held in the least significant bits of the Register given in the 2nd
operand is placed in the Transmit Buffer of the serial channel given by the 1st
operand. It is then transmitted automatically.
The Transmit Buffer can hold up to 512 characters. If it is empty (all characters
have been transmitted), the TBSY status flag is set Low. While there are
characters waiting to be transmitted, TBSY remains High.
If the TDIA status is High after executing an STXD, this indicates a problem, and
the Diagnostic Register shoud be examined.
Note: In simple applications, the error processing (above between brackets) can
be omitted.
Description Transmits the Text indicated in the 2nd operand via the serial channel given by the
1st operand (0-3). Status XBSY is set High, and the CPU transmits the Text.
XBSY is set Low when the Text has been transmitted. The text output can take
several seconds for large texts. The normal execution of the program continues
unaffected as the output of the text is executed in the background.
The XBSY flag indicates the completion of the background task. Whilst XBSY is
High no other communications instruction should be performed on this serial
channel. Texts can contain control strings to allow the formatted transmission of
element values, see Text Control Strings. The NEXE diagnostic flag is set if the
Text contains a bad control string.
Texts
Texts can be defined anywhere in an Assembler source program, but are placed in
an allocated area of Text memory in the PCD.
Texts can be written immediately following their referencing instructions;
alternatively, all texts can be written in a separate Assembler source module.
• The text can consist of several lines, each line must be enclosed in double
inverted comas: " ......... ". Texts can be of any length.
• Control characters can be entered enclosed in angle brackets.
For example: <LF>, <CR>, <FF>, <ESC>, …
• Control characters with decimal ASCII codes (1.. 31), or special characters
with codes (127..255) can be entered as decimal values enclosed in angle
brackets: <nnn>.
For example: CR = <13>, LF = <10>, ESC = <27>, BELL = <7>, ...
• Standard ASCII characters (32..126) may be entered directly from the
keyboard.
In the PCD memory, all texts are terminated with a NUL character (ASCII code
0), which is automatically appended to the end of the text by the Assembler.
Therefore, a text cannot contain the character NUL.
Examples:
The two following texts give the same result:
TEXT 10 "The quick brown fox jumps over the lazy dog"
TEXT 11 "The quick brown fox"
"jumps over the lazy dog"
If you have an EPSON printer you can put a part of your text in bold, by sending
special controls characters to the printer.
Assume that you will print the following text:
There is no limit for the SAIA PCD4 programmable controller
TEXT 13 "There is no limit for the"
"<ESC>E SAIA PCD4 <ESC>F"
"programmable controller <LF><CR>
Note: The characters ESC E make your printer print in bold, ESC F returns
it to normal.
$ = DIRECT ADDRESSING
Example of $Annnn:
"$A0999" when R 999 = 00000000 hex 'NUL'
"$A0999" when R 999 = 00000061 hex 'a'
"$A0999" when R 999 = 00006162 hex 'ab'
"$A0999" when R 999 = 00616263 hex 'abc'
"$A0999" when R 999 = 61626364 hex 'abcd'
Preceding zeros are not output. An ASCII zero is only output if the lowest value
byte is equal to 0.
@ = INDIRECT ADDRESSING
Element number is supplied in a Register
@innnn Logical state of a single Input (0, 1) nnnn : Register
number
@onnnn Logical state of a single Output (0, 1) (must be 4 digits)
@fnnnn Logical state of a single Flag (0, 1)
@Innnn Logical state of 8 Inputs (add to add+7)
@Onnnn Logical state of 8 Outputs (add to add+7)
@Fnnnn Logical state of 8 Flags (add to add+7)
@Cnnnn Counter contents
@Rnnnn Register contents
@Lnnnn incLude another text (max 3 level)
@xnnnn Character 'x' is repeated Register contents
times. The character must not be a data
type: (H|D|W|i|o|f|I|O|F|C|R|L|x)
For example, to output a fixed position of X = 40 and Y = 12, the whole sequence
of 4 characters can be written into a single register and output using $A....
Note that all values must be in hex format:
OUTPUT FORMATS
The format of transmitted Register and Counter data can also be specified in the
Text. The field width and number of decimal places can be specified. Format
definitions are introduced by the text "$%xxxx", where 'xxxx' is the required
format, see below. If such a definition is output, all the following Register or
Counter values are output using this format, until another format definition is
encountered.
In the following format definitions, the 'd/D' means 'decimal', x/X = hexadecimal
and b/B = binary. Other number base formats like o = Octal or f = floating point
are not supported. If the value is too large to fit in the defined field, default
formatting is used (no formatting).
NO FORMATTING (DEFAULT):
The field width depends on the size of the number.
TEXT 0 "REGISTER 10: $R0010 <10><13>"
"REGISTER 11: $R0011 <10><13>"
"REGISTER 12: $R0012"
Output:
REGISTER 10: 123456
REGISTER 11: -7890
REGISTER 12: 5
REMOVING FORMATTING:
"$%00d" sets the standard format (no formatting).
Example:
XOB 16
....
TEXT 991 "$%05.1d$s1" ; Format 1 definition (nnn.n)
TEXT 992 "$%04.2d$s2" ; Format 2 definition (n.nn)
TEXT 993 "$%08.3d$s3" ; Format 3 definition (nnnn.nnn)
COB 0
0
....
STXT 1
10
TEXT 10 "Pump Litres Price/L Total <10><13>"
" 1 $1$R0010 $2$R0011 $3$R0012 <10><13>"
" 2 $1$R0013 $2$R0014 $3$R0015 <10><13>"
....
ECOB
Results:
Pump Litres Price/l Total
1 13.8 0.86 11.868
2 158.2 0.95 150.290
Example:
COB 0
0
....
STXT 1 ; Send Text 10
10
TEXT 10 "$L0100 Motor speed too high<10><13>"
....
STXT 1 ; Send Text 11
11
TEXT 11 "$L0100 Oil pressure too low<10><13>"
...
ECOB
TEXT 100 "Diesel engine ALARM:"
Result:
Diesel engine ALARM: Motor speed too high
Diesel engine ALARM: Oil pressure too low
With the PCD Utilities (V1.3 and after), SYMBOLS can be used inside texts.
The value and optionally the type of the symbol is inserted into the text. The
symbol is written outside the ASCII text segment in double quotes, and must be
separated from this or other symbols by a comma. After the symbol, an optional
field width and prefix type can be given.
Format:
symbol [. [ [-] [0] width] [t | T] ]
symbol The symbol name. This can actually be any expression which
includes a symbol, for example: MotorOn + 100, ... .
Symbols with floating point values are not permitted.
. The dot immediately after the symbol indicates that a field width
and/or a prefix is present.
Width The field width: the number of digits or spaces required for the
number. If the width begins with a 0, leading zeros are inserted.
t|T Optional prefix type 't' or 'T'. If 't', the value is prefixed with the
symbol's type in lower case (o, f, r, ...); if 'T', the symbol's type is
in upper case (O, F, R,...)
Examples:
Flag EQU F 123
Output EQU O 32
Reg EQU R 999
TEXT 0 "$",Flag.04T ; Text 0 is "$F0123"
TEXT 1 "",Flag ; Text 1 is "123" (the empty "" is needed)
TEXT 2 "DIAG:",Output.T,",",Reg.T
; Text 2 is "DIAG:O32,R999"
TEXT 3 "55:",Flag.T,"-",Flag+7,":",Output.T,"-",Output+7
; Text 3 is "55:F123-130:O32-39"
TEXT 4 "FLAG Number: *",Flag.-8,"*"
; Text 4 is "FLAG Number: *123 *"
XOB 16
SASI 1
3999
TEXT 3999"UART:9600,7,E,1;MODE:MC0;"
"DIAG:",D_FLAG.T,",",D_REG.T,";"
Note: The symbols (for texts) and texts must be defined in the same file.
Description Reads elements from the Remote PCD, and copies them into destination elements
in the Local PCD. Transfers can be I|O|F to O|F, R|T|C to R|T|C.
The 1st operand is the channel number.
The 2nd operand is the number of elements to be transferred.
The 3rd operand is the lowest address of the source element in the Remote PCD.
The 4th operand is the lowest address of the destination element in the Local PCD.
After executing SRXM, the TBSY flag is set High, it is set Low when the
operation has completed.
Description Copy the receive buffer (received frame) into consecutive registers of the PCD.
When a telegram has been received without errors: RFUL is set to 1; SRXM reset
this flag to 0.
The 1st operand is the channel number.
The 2nd operand is always 0.
The 3rd operand is a Register or a Counter which will contain (after the execution
of the instruction) the number of received characters.
The 4th operand is the address of the first Register where the received characters
will be copied.
Each received character needs 8 bits of a Register: a Register can hold a maximum
of 4 characters.
The characters are placed in the Registers as follow:
reg 1: 11111111 22222222 33333333 44444444 Characters 1 to 4
reg 2: 55555555 66666666 77777777 88888888 Characters 5 to 8
...
If the number of received characters is not a multiple of 4, the rest of the Register
is set to 0.
The address of the partner which has sent the telegram is contained in the
<repartner> Register defined in the SASI text.
where:
reg 1 Register contains (after execution) the number of read characters.
A counter can also be used.
reg 2 Address of the first register into where the information will be
copied (a register holds up to 4 characters)
For further information, consult the "Description of the LAC MM4 Protocol"
Special functions
This register contains the "Count" or number of elements to transfer (range 1...32)
and the "Position" in the Data-Block where to put or get the data. "Count" is given
in the MS Word of the register and "Position" in the LS Word of the register.
Description This instruction works in the same way as the existing SRXM instruction.
The difference is that it works in indirect mode. Indirect mode means that the
number of the media for source and destination is given by the content of a
register. SRXMI are only available for transfer of media. Transfer options like the
Real Time clock, Display-Register,... are not allowed.
Channel
This parameter is used to specify the channel number (range: 0...3).
Count or Count + Position
This parameter is a register number. This register contents the "Count" for
standard medias or "Count" and "Position" for Data-Block.
For Data-Block, "Count" is given in the MS Word of the register and
"Position" in the LS Word of the register and in that case, the initialisation
of this register can be easily done with LDL and LDH instructions.
Source-type and Reg-number
Destination-type and Reg-number
These parameters specify the "Source" and "Destination " of the transfer.
Each of these parameters is composed of a character giving the type of
media (I/O/F/R/T/C/DB) and a register number (0...4095). The source and
the destination must respect the source-destination validity described in the
table for the SRXM/STXM instructions.
Description Reads data (objects) in indirect mode from the remote station and copies them in
the local PCD. It is possible to select direct or indirect addressing of channel
operands.
Description Transmits elements from the Local PCD to elements in the Remote PCD.
Transfers can be I|O|F to O|F, R|T|C to R|T|C.
The 1st operand is the channel number.
The 2nd operand is the number of elements to be transferred.
The 3rd operand is the lowest address of the source element in the Local PCD.
The 4th operand is the lowest address of the destination element in the
Remote PCD.
During the execution of STXM, the TBSY flag is set High; when the operation is
complete, it is set Low.
COB 0
0
STH F 1003 ; If not already busy to communicate (TBSY)
JR H NEXT
STXM 1 ; Then transfer on serial channel 1
16 ; 16 Elements
I 0 ; from Input 0 ( to 15) of local PCD
O 32 ; to Output 32 ( to 47) of remote PCD
NEXT: ECOB
Description Transfers registers over the LAC/LAC2 network using the MM4 protocol.
This transfer can occur via the LAC/LAC2 network or in point to point.
The 1st operand is the channel number.
The 2nd operand defined the transfer function.
The 3rd operand is a Register or a Counter which contains the number of
characters to transfer.
The 4th operand is the address of the first Register containing the characters to
transmit.
A Register can hold a maximum of 4 characters: each character needs 8 bits.
The characters must be placed in the Registers as follow:
reg 1: 11111111 22222222 33333333 44444444 Characters 1 to 4
reg 2: 55555555 66666666 77777777 88888888 Characters 5 to 8
...
The address of the partner is contained in the <trpartner> Register defined in the
SASI text.
After the execution of STXM, the XBSY flag is set High; when the operation is
completed (telegram acknowledged by the partner), XBSY is reset to Low.
where:
fct Function to perform
0 /2 Transmission of data
4 Diffusion
reg 1 Register containing the number of characters to be transmitted.
A counter can also be used.
reg 2 Address of the first register from where the information is to be
transferred (a register holds up to 4 characters)
For further information, consult the "Description of the LAC MM4 Protocol"
Description Transmits elements from the client PCD to elements in a server PCD.
The address of the server station is passed via a register as defined in the SASI text
(see page 8-11). Transfers can be I|O|F to O|F, R|T|C to R|T|C.
The 1st operand is the channel number.
The 2nd operand is the number of elements to be transferred.
The 3rd operand is the lowest address of the source element in the client PCD.
The 4th operand is the lowest address of the destination element in the server PCD.
During the execution of STXM, the TBSY flag is set High; when the operation is
complete, it is set Low .
The following table shows which elements can be copied from the source station
to the appropriate elements in the destination station.
When writing to the clock, two registers are sent. For the data format of registers,
see the WTIME instruction.
Special function
It is possible to provoke the execution of an XOB in a slave station using the
STXM instruction with the following arguments:
STXM 0..3 ; Serial channel number
0 ; (must be 0)
K 4000 ; Used to indicate XOB interrupt
K 171819 ; number of the XOB to execute
It is also possible to use this instruction in broadcast mode; this allows the
synchronisation of events.
STXM Channel
Count Position
Source
Destination
This register contains the "Count" or number of elements to transfer (range 1...32)
and the "Position" in the Data-Block where to put or get the data. "Count" is given
in the MS Word of the register and "Position" in the LS Word of the register.
Description Transmits data (objects) from the remote station and copies them in the
local PCD.
The 1st operand is the channel number.
The 2nd operand is the sub-index from source and destination object.
The 3rd operand is the source object index (own station).
The 4th operand is the destination object index (remote station).
Description This instruction works in the same way as the existing STXM instructions.
The difference is that it works in indirect mode. Indirect mode means that the
number of the media for source and destination is given by the content of a
register. STXMI are only available for transfer of media. Transfer options like the
Real Time clock, Display-Register,... are not allowed
Channel
This parameter is used to specify the channel number (range: 0...3).
Count or Count + Position
This parameter is a register number. This register contents the "Count" for
standard medias or "Count" and "Position" for Data-Block.
For Data-Block, "Count" is given in the MS Word of the register and
"Position" in the LS Word of the register and in that case, the initialisation
of this register can be easily done with LDL and LDH instructions.
Source-type and Reg-number
Destination-type and Reg-number
These parameters specify the "Source" and "Destination" of the transfer
Each of these parameter is composed of a character giving the type of media
(I/O/F/R/T/C/DB) and a register number (0...4095). The source and the
destination must respect the source-destination validity described in the
table for the STXM instruction.
Example STXMI 1
R 100
DB 101
R 102
Flags The Error (E) flag is set if the channel is not correctly initialised, or STXM is
executed when already in communication.
See Also STXM, Communications instructions, Diagnostic flags
Description Transmits data (objects) in indirect mode from the remote station and copies them
in the local PCD. It is possible to select direct or indirect addressing of channel
operands.
Description Reads a control signal from the serial channel given in the 1st operand and stores
its state in the ACCU.
For the Port 0 (PGU) of the PCD1, PCD2, PCD4, PCD6.M3 and PCD6.M540, the
instruction SICL is always allowed (independently, whether the port is assigned or
configured).
For any other port of PCD1, PCD2, PCD4, PCD6.M3 or PCD6.M540, the
instruction SICL is only allowed on a port configured for S-Bus PGU.
Otherwise, the instruction SICL is only allowed after execution of a SASI.
Description Sets a selected control signal of the serial channel given in the 1st operand to the
state of the ACCU (H or L).
For the Port 0 (PGU) of the PCD1, PCD2, PCD4, PCD6.M3 and PCD6.M540, the
instruction SOCL is always allowed (independently, whether the port is assigned
or configured).
For any other port of PCD1, PCD2, PCD4, PCD6.M3 or PCD6.M540, the
instruction SOCL is only allowed on a port configured for S-Bus PGU.
Otherwise, the instruction SOCL is only allowed after execution of a SASI.
Special functions:
Port 0 on PCD2
A SASI for SM1/SS1 in the user program will configure the port 0 to RS485. If the
user wishes to use RS232 on the port 0 then he must perform the following
instructions after the SASI instruction:
ACC L
SOCL 0
2
Mode Type
MC0 .. MC3, MD0 / SD0 RS422
MC4, S-Bus RS485
It is sometimes needed to force the PCD to use S-Bus with RS422; in this case, the
following instructions must be performed after the SASI instruction:
ACC L
SOCL Port_nb
2
It is also possible to force the RS485 mode with MC0..MC3 or MD0/SD0 with:
ACC H
SOCL Port_nb
2
ACC H
SOCL Port_nb
0
ACC L
SOCL Port_nb
0
Description Opens or closes a virtual connection to other stations on the SAIA LAN 1.
The 1st operand is channel number.
The 2nd operand is the station number (1-250).
The 3rd operand is the connection state (0 = Close, 1 = Open).
The connection state is written into the Register defined in the SASI instruction by
the MODE assignment (Example: "MODE:SD0,R4000;").
Value Description
0 Disconnected
1 Connected
2 Queued
3 Destination busy
4 Destination unknown
6 Remote PLC not connected
10..2500 If the connection was made by a remote PLC the register
contains the number of the PLC multiplied by 10
Description Opens or closes a virtual connection to other stations on the SAIA LAN 1 in
indirect mode.
The 1st operand is channel number or a register containing the channel number.
The 2nd operand is a register containing the station number (1-250).
The 3rd operand is a register containing the connection state (0 = Close, 1 =
Open)
The connection state is written into the Register defined in the SASI instruction by
the MODE assignment (Example: "MODE:SD0,R4000;").
Value Description
0 Disconnected
1 Connected
2 Queued
3 Destination busy
4 Destination unknown
6 Remote PLC not connected
10..2500 If the connection was made by a remote PLC the register
contains the number of the PLC multiplied by 10
9. LAN 2 Instructions
The SAIA LAN2 is a Local Area Network working on the token passing principle
which can interconnect up to 255 stations.
The states of any Inputs, Outputs or Flags, and the values in any Registers, Timers
or Counters, or the status of any CPU can be sent or received via the LAN2.
IMPORTANT:
The instructions and functionnality described here are valid for version 004 (and
above) of the LAN2.
LAN 2 instructions:
Notes
When the transfer is complete the EXEC flag is set High. If the LRXD instruction
is executed again, the data transfer is repeated. The state of the EXEC flag is
altered only when the LRXD instruction is executed.
COB 5
0
STH I 1 ; If Input 1 goes High
DYN F 1
ORL F 100 ; EXEC Flag
CPB H 50 ; Then Call PB 50
ECOB
PB 50
LRXD 1 ; Priority
15 ; Text nb.
F 100 ; EXEC Flag
$LAN
TEXT 15 "3:I0-7:O32-39"
$ENDLAN
EPB
When the transfer is complete the EXEC flag is set High. If the LTXD instruction
is executed again, the data transfer is repeated. The state of the EXEC flag is
altered only when the LTXD instruction is executed.
COB 5
0
STH I 8 ; If Input 8 goes High
DYN F 8
ORL F 100 ; EXEC Flag
CPB H 51 ; Then Call PB 51
ECOB
PB 51
LTXD 1 ; Priority
16 ; Text nb.
F 100 ; EXEC Flag
$LAN
TEXT 16 "3:I0-7:O40-47"
$ENDLAN
EPB
Description Reads the status of a remote PCD into the defined status flags or read the statistics
(traffic control) for its own station.
The status can be:
The 1st operand is the number of a Text containing the address of the station from
which the status must be read.
The 2nd operand is the base address of 10 Diagnostic Flags (or Outputs).
The first Diagnostic element is the EXEC flag. It is initially set Low by LRXS, and
remains Low on subsequent executions of the same LRXS instruction, until the
transfer is complete.
The state of the EXEC flag is altered only when the LRXS instruction is executed.
If the status returned is "disconnected", then only the "Disconnected" Flag is set,
since there was no error.
The 1st operand is the number of a Text containing the address of the station
where the status must be changed and the new status.
The 2nd operand is the base address of 10 Diagnostic Flags (or Outputs).
The first Diagnostic element is the EXEC flag. It is initially set Low by LTXS, and
remains Low on subsequent executions of the same LTXS instruction, until the
transfer is complete.
The state of the EXEC flag is altered only when the LTXS instruction is executed.
For each SAIA LAN2 instruction, one operand gives the base address for the 10
diagnostic elements (Outputs or Flags)
EXEC Flag:
The first Diagnostic element is the EXECuted flag. While EXEC is Low, it
indicates that the LAN2 instruction is still executing (receiving or transmitting
data). The EXEC flag is initially set Low when a LAN2 instruction is first
executed, and remains Low on subsequent executions of the same instruction,
until the transfer is complete. When the transfer is complete the EXEC flag is set
High.
If the LAN2 instruction is executed again, the data transfer is repeated. The state
of the EXEC flag is altered ONLY when the LAN2 instruction is executed.
PRIORITY:
The transfer of information in the LAN2 is frame oriented; each frame is 32 bytes
long and therefore can contain 8 R|C|T or 256 I|O|F.
When the station receives the "Token", only one frame is transmitted and the
token goes to the following station. A transfer which is longer than one frame will
be separated in different frames and will always have a low priority (1); if the high
priority is requested flag +2 (Invalid command text) is set and the telegram is not
sent.
A short telegram which is less then a frame can be sent with high priority (0) or
low priority (1). If the priority is high, the frame can be inserted between
successive frames of a long telegram (low priority).
NOTE:
Not all combination of source and destination elements are valid (e.g. Flags cannot
be transferred to Registers).
Source Destination Address
O F T C R Range
I 0..8191
O 0..8191
F 0..8191
T 0..450
C 0..1599
R 0..4095
The number of texts used to define transfers via the LAN2 can be reduced by
using indirect addressing: the effective address is determined by the contents of a
register.
Each part of the LAN2 command text (station number, source and destination)
can be indirected with the '@' character.
FORMAT:
Example:
"@100:@I400:@F600"
The remote station number is in register 100. The Input which address is given by
the register 400 will be transfered to the Flag which address is given by register
600
FORMAT:
Example:
"@200:@C100-@101:@C500"
The remote station number is in register 200. The first counter address is given by
the contents of register 100, the number of counters to be transfered is in register
101. These counters will be copied to counters starting with the contents of
register 500.
Mixed addressing
The direct and indirect addressing can be mixed in the same command text.
Example:
"@5:R100-50:@99"
"25:I0-@55:F1000"
The remote station number is station 25. Inputs between I 0 and the contents of
Register 55 are transferred onto Flags beginning at address 1000.
As the contents of the registers used in the indirect or mixed addressing can not be
tested by the "Assembler", the user must take care to not go beyond the range of
the addressed elements.
Station number
0-254 The command is sent to the specified station
255 The command is sent to all stations connected to the
network except the own station
Command
HALT Set all processors for the specified station in HALT User
program is stopped Diagnostic flag 8 is set
RUN Set all processors for the specified station in RUN
CON Set the LAN2 station in connected state. Diagnostic flag
3 or 5 is set low.
DIS Set the LAN2 station in disconnected state. In this case
no instructions are executed and no data is transferred.
Diagnostic flag 3 or 5 is set high
TOUT:NNN This sets the timeout for the specified station NNN is the
number of stations on the network (2-255)
If the status returned is "disconnected", then only the "Disconnected" Flag is set,
since there was no error.
Note: LAN 2 communication is only complete when the EXEC flag = H
again after executing LRXS
It is possible to check what happens on the SAIA LAN2 network with the LRXS
instruction and a special status text :
FORMAT:
OWN Station number : STAT : Rxxxx
This command text is used to read the LAN2 transmission/reception statistics into
4 registers starting at register xxxx. This command is useful to diagnose hardware
errors on the network.
Note: During the first communication with a station, the number of retries is
incremented: it means that every communicating station has at least 1
retry. Values in the statistic registers are stored in 16 bits format (max
value is 65535)
Example :
Read statistics of own station 100 and store the values in Registers 20 to 23.
The syntax of LAN2 texts written between the $LAN ($LLAN) and $ENDLAN
($NOLAN, $NOLLAN) directives is checked during assembly. Lower case
characters are also converted to the required upper case.
Futhermore, the Assembler converts the LAN2 texts into binary format, which
makes LAN2 communication faster. The time gained is about 15 ms per
command; this is particulary effective for short telegrams.
Examples:
$LAN
TEXT 0 "2:I0-255:F1000-1255"
TEXT 1 "5:r501-510:r101-110"
TEXT 2 "7:f0-31:o96-127"
TEXT 15 "2:con"
TEXT 37 "15"
$ENDLAN
Note: Binary LAN Texts cannot be displayed or edited from the debugger
because they have a different format.
The value and optionally the type of the symbol is inserted into the text. The
symbol is written outside the ASCII text segment in double quotes, and must be
separated from this or other symbols by a comma. After the symbol, an optional
field width and prefix type can be given.
Format:
symbol [. [ [-] [0] width] [t | T] ]
symbol The symbol name. This can actually be any expression which
includes a symbol, for example: MotorOn + 100, ... Symbols
with floating point values are not permitted.
. The dot immediately after the symbol indicates that a field
width and/or a prefix is present.
Width The field width: the number of digits or spaces required for the
number. If the width begins with a 0, leading zeros are inserted.
t|T Optional prefix type 't' or 'T'. If 't', the value is prefixed with the
symbol's type in lower case (o, f, r, ...); if 'T', the symbol's type
is in upper case (O, F, R,...)
Examples:
SOURCE EQU R 55
DEST EQU R 66
$LAN
TEXT 25 "8:" , SOURCE.T , ":" , DEST.T
$ENDLAN
Jumps instructions are causes of errors (infinite loops, ...); these instructions must
therefore be used with care. Jumps will be preferabily used in program blocks or
function blocks rather than in the main program.
JR Jump relative
JPD Jump direct
JPI Jump indirect
Notes
JR JUMP RELATIVE
When programming using the Assembler, it is usual to use labels (symbolic names)
for jump destinations. Labels can be any length, but only the first 8 characters are
significant; the labels must always begin with a letter (A..Z).
When using an editor other than SEDIT, it is necessary to put a ':' after each label.
If the condition is not true, the jump is not made; execution continues with the
instruction following JPD.
If the condition is not true, the jump is not made; execution continues with the
instruction following JPI.
The value of a label can be loaded into a Register using the LD instruction.
Note
Care must be taken that the destination of the jump is not outside of
the current block.
Description Conditionally or unconditionally Halts the CPU. The Halt state is not the same as
the Stop state. After a HALT, the CPU can only be set to Run by a Restart
operation, or by powering the PCD off and on.
If the condition is not true, the HALT is not made; execution continues with the
following instruction.
NOTE: After a HALT of CPU 0, a Restart Cold can be executed only on all
CPUs. The status of the outputs after the HALT is defined by the hardware
configuration (jumpers).
XOB 13
DIAG R 1000
HALT
EXOB
WARNING
Description LOCK in conjunction with UNLOCK, is used to prevent access conflicts when
several CPUs read or write the same elements. 100 Semaphores (special flags) are
available (0-99). The LOCK instruction checks the Semaphore. If it is High
(another CPU has executed a LOCK), then the ACCU is set Low. If it is Low, the
ACCU and the Semaphore are set High.
It is the programmers responsibility to ensure that the CPU does not reference an
element if the associated Semaphore is High (ACCU = L (0) after LOCK).
Description UNLOCK in conjunction with LOCK, is used to prevent access conflicts when
several CPUs read or write the same elements. 100 Semaphores (special flags) are
available (0-99). The UNLOCK instruction clears the Semaphore.
CPU 0 CPU 1
… …
LOCK 1 LOCK 1
CFB H 10 CFB H 100
…. ….
FB 10 FB 100
CMP R 88 DIGI 2
R 89 I 16
UNLOCK 1 R 88
EFB DIGI 2
I 24
R 89
UNLOCK 1
EFB
The use of semaphore 1 ensures that CPU 0 never compares the two registers
while CPU 1 is executing the DIGI instructions, and is altering the contents of the
registers. If CPU 0 were to compare the registers at the same moment that CPU 1
was updating them, it might compare a new value with an old one. Semaphore 1
also prevents CPU1 executing the DIGI instructions until CPU 0 has finished the
CMP instruction.
Notes
Description Defines the area of Flags which are to be non-volatile (battery backed-up).
Non-volatile Flags retain their values even after power to the PCD is lost.
Volatile Flags are all set to 0 on power-up of the PCD. All Flags ABOVE the Flag
indicated in the operand are defined as being non-volatile.
Description Defines the number of Timers for the PCD. Timers and Counters occupy the same
addressing space. All elements BELOW the operand value are Timers, all the
others are Counters.
Timers: 0 - 31
Counters: 32 - 1599.
NOTE: Do not define more Timers than are actually required by the program.
The handling of each Timer affects the program execution speed. The
maximum number of Timers allowed is 450.
Description Defines the timebase for the decrementing of the Timers. The operand indicates the
timebase in 10's of milliseconds. Values of 1 to 1000 are valid (10 ms to 10 sec).
If the timebase is not defined (no DEFTB), the default is 100 ms (1/10 sec).
For the other CPUs, DEFTB defines the timebase for the internal timers used by
the delayed instructions SETD and RESD. Therefore, the internal timers of CPU 0
always have the same timebase as the user Timers; the timebase of the internal
timers of the other CPUs may differ from that of the user Timers.
Note: care should be taken when defining a low timebase (eg. 10 ms) and a
large number of timers (the handling of a large amount of Timers can
slow down the program execution speed).
The advantage of the DEFTR instruction (over the DEFTB) is that the values you
specify when using timers are independant of the timebase or resolution and
always introduced in multiple of 10 ms. For the DEFTR instrcution to have an
influence on the Timers it must be programmed in CPU0. The DEFTR instruction
allows a maximum timer resolution of 10ms which means that the value specified
in the instructions is rounded if necessary .
Example: DEFTR 25: a time base of 20 ms will be set (25 rounded down to 20).
The DEFTR instruction, as with the DEFTB instruction, also acts on the
instructions SETD, RESD and OUTD. If the DEFTR instruction is present in the
user program then the time base of these instructions is fixed to 10ms independent
of the specified value by DEFTR
XOB 16
DEFTR 200
…
EXOB
COB 0
0
….
SETD O 20
15
…
ECO
Description Defines which elements are to be protected from being overwritten by the LAN2.
In both instructions, the operand defines the element type and the top end of the
range to be protected. Elements addressed from 0 up to this value are write
protected. The instructions must be executed once for each element type to be
protected: O, F, T, C, R. If all element types are to be protected, DEFWPR must
be executed five times.
If the instructions are not present, NO elements are write protected in the RUN
state.
Description Defines which elements are to be protected from being written to by the LAN2.
DEFWPH defines elements to be write protected when the CPU has Halted
(DEFWPR defines elements to be write protected if the CPU is in Run).
In both instructions, the operand defines the element type and the top end of the
range to be protected. Elements addressed from 0 up to this value are write
protected. The instructions must be executed once for each element type to be
protected: O, F, T, C, R.
If all element types are to be protected, DEFWPH must be executed five times. If
the instructions are not present, NO elements are write protected in the Halt state.
Example DEFWPH C 79 ; Timers and Counters 0-79 are write protected (in
Halt state)
Flags Unchanged.
See Also DEFWPR, DEFTC, DEFTB, DEFVM, LAN2
Practice In an application using a LAN 2, 1000 local flags and 500 registers must be
protected from being written by another station when the CPU is in RUN
and in HALT.
NOP No operation
The following instructions must no longer be used but are maintained for
compatibility reason:
These two instructions works only with the analogue card PCA2.W1x. To
read or write values to analogue cards PCD2, PCD4 and PCD6, consult the
appropriate hardware manual.
These instructions were used for accessing slow I/O modules such as the
PCA2.W2x / W3x.
Notes
NOP NO OPERATION
Description Reads the contents of the internal hardware clock into two Registers. The first
Register is specified in the instruction. After the RTIME instruction, the Registers
are set as follows:
Digit number 9 8 7 6 5 4 3 2 1 0
Register 0 0 0 0 Hour Hour Min Min Sec Sec
Register + 1 0 Week Week Wday Year Year Month Month Day Day
32 33 34 35 36 37 38 39
Minutes (BCD)
80 40 20 10 8 4 2 1
PB 25
COB 0 RTIME R 20
0 MOV R 20
STH I 3 D 2
DYN F 3 R 99
CPB H 25 D 0
... MOV R 20
ECOB D 3
R 99
D 1
DIGOR 2
R 99
O 32
EPB
Description Writes the contents of two Registers to the internal hardware clock. The first of
the two Registers is specified in the instruction. The format of the Register
contents is as for the RTIME instruction:
BCD values can be loaded into the Registers from Flags etc. using the DIGI
instruction.
Example WTIME R 500 ; Loads the clock from Registers 500 and 501
Flags Unchanged.
See Also RTIME, DIGI
Practice After switching on Input 4, the hours of the clock should be set on a new value.
The new value is to be read from the BCD switches on inputs 16-23.
16 17 18 19 20 21 22 23
Hours (BCD)
80 40 20 10 8 4 2 1
PB 26
COB 0 RTIME R 200
0 DIGIR 2
STH I 4 I 16
DYN F 4 R 199
CPB H 26 MOV R 199
... D 0
ECOB R 200
D 4
MOV R 199
D 1
R 200
D 5
WTIME R 200
EPB
Example PID R 1000 ; Uses R 1000-1012 for the PID control data
Flags Unchanged
Practice A typical PID control loop Start
must consist of the
following:
Read Fp, Fi, Fd, W, X, Zs
PID instruction for Cold start
PID instruction
Fp, Fi, Fd No
modified ?
Yes
Process
W Y
PID
Reference Wn:
The reference (setpoint) is written to the register (R+4) by the user program. The
reference should be maximum 'm' bits.
The value of Ys is automatically reset to 0 by the system program after being used
once and will not be used again.
For a Cold Start with an output value of 0, the Ys register must be set to -1.
When Fi = 0, the Yn value can not be initialised with a Cold Start. A Cold Start is
however recommended to initialise the workspace register. In this case, the Ys
value is ignored, the Zs register is set to 0 and Yn take the value of the proportional
part of the algorythm.
Resolution m:
The maximum values of X, W, Yn and Ys are determinated by the resolution.
If m= 8: 8 bits are used (0..255)
If m= 12: 12 bits are used (0..4095)
If m= 16: 16 bits are used (0..65535)
The resolution is mostly defined by the analog module used for the Result variable
output. If the resolution for the input and output are not the same, the Yn value
must be adapted after the PID instruction.
Sampling Time:
The sampling time To must be done outside the PID instruction with a timer.
In practice: To ≈ 0,1 time constant of the process (To must be at least 80 ms)
Calculation capacity:
The workspace register Zs has a maximum capacity of 231.
When using 16 bits values (m = 16), an overflow can occur; in this case the PID
will not work properly.
To avoid this problem, the factor Fp must be ≥ 2 if m = 16 (There is no problem
when m = 8 or 12).
If any test fails, the test is aborted, and the ACCU is set Low (0).
If all the selected tests pass, the ACCU is set High (1).
For every bit set, the corresponding test is done. Tests 0 and 5 are executed if the
tested CPU is the only one in Run; if any other CPUs are running, these tests are
NOT performed.
Note: Some of the tests are very slow, and should not be done during normal
operation of the PCD, run the tests on startup or during an idling period.
Description Fills a 12-Register block with diagnostic information relating to the last or the
present Exception Organisation Block (XOB) executed. The operand is the lowest
Register number of the block of 12 Registers. DIAG is normally used within an
XOB.
The program line numbers of the block calls (Nesting level information) give the
program line where the previous call (CFB, CPB, etc) took place. From these, it
can be established exactly where the program was when the XOB was executed.
Note: The most important information are provided by register R and R+1
XOB 13
DIAG
R 1000
STXT 1
100
TEXT 100 "$D $ H :"
" Error Flag set at address $R1001 <CR><LF>"
EXOB
Description Read the PCD system parameters like: PCD Device type, CPU type, Firmware
version, User program name, S-Bus parameters, …
Function
K x or R x: Constant or register containing a function code. This
instruction can either be direct, by using a constant for the
function code or indirect by using a register. It permits the
user to have access to useful system information via the
user program.
Result
R 0..4095 Register containing the result or first of 2 registers (see
code 5400) or first of a set of registers (see codes 65xx)
Example SYSRD K 5000 ; Read the PCD type in ASCII
R 20 ; and put the result in R 20
Flags If the function code does not exist, the Error flag is set.
See Also SYSWR
It is possible to read each value separately depending on function code. The return
value is in decimal format. The function codes are between 7050 and 7090. The
function code 7090 allows to know the number of seconds elapsed since midnight
(00:00:00), 01/01/1970, co-ordinated universal time, according to the system
clock.
Examples:
Result: R 0: 120203
Notice:
When the user takes a function code between 7050 and 7090 which is not in this
table, XOB 13 is called and the error flag is set.
Function
K x or R x: Constant or register containing a function code. This
instruction can either be direct, by using a constant for the
function code or indirect by using a register. It permits the
user to have access to useful system information via the
user program.
Value
Ky Value to be written
R 0..4095 Register containing the value to be written
Example SYSWD K 4014 ; Initialize the XOB 14 with a frequency
K 10 ; of 10 ms
Flags If the function code does not exist, the Error flag is set.
See Also SYSRD
Permitted values of R y or K y:
0 Disable the XOB
1 Enable the XOB
2 Clears the Error Flag in the current COB and in the active
XOB (For K 4013 only)
4014 Install XOB 14 /15
4015 Configure periodic XOB with the frequency defined in Ky or Ry.
It is possible to configure two periodic XOBs with a frequency from 5 ms
to 1000s.
The value in Ky or Ry is given in ms, if it is zero then the XOB is
deactivated. This instruction can be executed at any time. If an XOB is
already being executed when an XOB becomes pending then it will be
queued until a time when there is no XOB active and it can be executed.
The XOBs are only executed if the CPU is in RUN or CONDITIONAL
RUN.
Permitted values of R y or K y:
0 .. 6 CPU on which XOB will be provoked
7 Provoke XOB on own CPU
8 Provoke XOB on all CPUs.
It is possible to write each value separately depending on function code and each
value is on 2 digits, for example: 12h, 2 min and 3 sec, it will be written 120203.
The function codes are between 7050 and 7081 as showing the following table.
Examples:
1) LD R 0
120203
2) LD R 0
120203
LD R 1
991130
Notice:
When the user takes a function code between 7050 and 7081 which is not in this
table, XOB 13 is called and the error flag set.
Description The SYSCMP instruction is able to transform any register into a pseudo Timer.
It’s task is to compare the sum of the first and second operands to the System
Counter and set the ACCU according to the result.
If the result of the addition is greater than the System Counter, the ACCU is set
High (1). If the result of the addition is smaller than or equal to the System
Counter, then the ACCU is set Low (0).
The advantage of this instruction coupled to the instruction SYSRD K 7000 is that
it is now possible to have Timers with a resolution of 1 ms. We also can measure
the time between two events to a resolution of 1ms
COB 0
0
…
LD R 100 ; Load the time to wait in ms (1500)
K 1500 ; in R 100
Description Reads a 12-bit value from a PCA2.W1x analogue module, and stores it in the
specified Register.
The 1st operand contains both the A/D channel number (0-7) and the base address
of the module.
The 2nd operand is the destination Register number.
If the first operand is supplied as an FB parameter, both the A/D channel number
and the base address must be supplied on the same line.
Description Outputs a 12-bit binary value from the specified Register to a PCA2.W1x
analogue module.
The 1st operand is the Register to be output.
The 2nd operand contains both the D/A channel number, and the base address of
the module.
Description The ACCU is set to the logical state of the addressed element, usually an Input.
This is the same as the STH instruction, except that the timing on the PCD I/O bus
is slightly slower, and it is therefore suitable for slow I/O modules. Program
execution speed is not significantly affected.
Example STHS I 25
Flags The ACCU is set to the logical state of the specified element
See Also OUTS, STH, Bit instructions
Description The specified element, usually an Output, is set to the state of the ACCU. This is
the same as the OUT instruction, except that the timing on the PCD I/O bus is
slightly slower, and it is therefore suitable for slow I/O modules. The program
execution speed is not significantly affected.
Example OUTS O 32
Flags The ACCU is set to the logical state of the specified element.
See Also OUT, OUTD, STHS
Practice The analogue value of channel 0 from a PCA2.W2x (base address 96) must be
read and stored in Register 100.
After the conversion is made with the OUTS instruction, 8 binary bits can be read
starting from the module base address + 8 (=104)
COB 0
0
...
ACC H ; Be sure that ACCU is High
OUTS 96 ; Select analog channel
... ; Wait ± 100 ms *)
CPB RD_VAL ; Call RD_VAL program block
....
ECOB
PB RD_VAL
BITIR 8 ; Read 8 bits binary in reversed order
I 104 ; from address 104 .. 111
R 100 ; into Register 100
EPB
*) The analogue module PCA2.W2x has a conversion time of ≤ 100 ms. This
wait function can be done by inserting a number of consecutive NOP
instructions. (The number of NOPs is depending from the CPU type).
Notes:
The following errors have a fixed entry in the history table with an error counter
*) System: 1: PCD1
2: PCD2
4: PCD4
5: PCD6.M540
6: PCD6.M1.., M2.., M3..
These errors are written into the HALT REASON register which is read by the
PG3 Debugger when a HALT is detected. They can occur on POWER-UP or
when the PCD is in RUN.
The following errors will be detected whilst the PCD is in RUN, those which put
the PCD in HALT will also write the message in the HALT REASON
Notes
Performance
overview from
PCD1 up to PCD6