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9 views5 pages

Abstracts

Uploaded by

mramyasri13
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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AN EFFICIENT FULL ADDER USING FINFET TECHNOLOGY

ABSTRACT

Due to the recent technology trends all the electronic markets are based on reliable and speed performance
devices. By developing semiconductor industry, all the passive and active components are assembled on a
single chip named as an Integrated chip (IC). Developing this type of technology made all the electronic
devices becomes smarter and reliable in performance. These technology nodes are based on CMOS
technology. The main component in the processor is an ALU. We make survey on Adder type of devices
which gave you addition subtraction and all arithmetical operators performed in circuit level and logic level
implementation. And also we designed new technology named as FinFET based adder circuits which give us
better performance like. Less Leakage power, low power consumption and less propagation delay. We
verify all the parameters in 45nm Technology node to both CMOS and FinFET technology by using spice
tool. The adoption of FinFET technology in full adder design not only meets the demands of modern
electronic devices but also paves the way for future advancements in low-power digital circuit design.
Further research is suggested to explore multi-bit adder architectures and integration with larger circuit
systems.

UNDER THE GUIDANCE OF TEAM MEMBERS

Mrs.B.SRI LATHA G.SAI 225671568L


Assistant Professor, M.RAMYA SRI 21567T1546
Department of ECE MD.ABDUL RASHEED 21567T1543
B.DEEPIKA 21567T1512
D.MOUNIKA 195671561L
COMPARISION AND ANALYSIS OF DYNAMIC COMPARATOR USING
DIFFERENT TECHNOLOGIES

ABSTRACT

A comparative analysis of dynamic comparators implemented using various semiconductor technologies,


including traditional CMOS, FinFET, and emerging devices like tunnel FETs (TFETs). As high-speed, low-
power analog circuits are critical in modern integrated systems, the choice of technology for comparator
design significantly impacts performance metrics such as speed, power consumption, and area efficiency.We
analyze the operational principles and architectures of dynamic comparators across these technologies,
focusing on parameters such as offset voltage, dynamic range, and power-delay product (PDP). Simulation
results demonstrate that while traditional CMOS comparators provide robustness and ease of integration,
FinFET-based designs offer enhanced performance with reduced leakage currents and improved speed
characteristics due to better electrostatic control. Furthermore, TFETs showcase unique advantages in
subthreshold operation, leading to significant power savings in low-voltage applications. The findings
indicate that the choice of technology heavily influences the overall performance of dynamic comparators.
FinFETs emerge as a favorable option for high-speed applications, while TFETs may be preferable for ultra-
low-power designs. The paper concludes by discussing the implications of these technologies for future
comparator designs and potential applications in high-performance analog circuits. Future work will involve
experimental validation and integration of these comparators into larger systems.

UNDER THE GUIDANCE OF TEAM MEMBERS

Mrs. B.SRI LATHA G.SAI 225671568L


Assistant Professor, M.RAMYA SRI 21567T1546
Department of ECE MD.ABDUL RASHEED 21567T1543
B.DEEPIKA 21567T1512
D.MOUNIKA 195671561L
DESIGN OF VENDING MACHINE USING VERILOG HDL

ABSTRACT

The design and implementation of a vending machine system using Verilog Hardware Description Language
(HDL). The objective is to create a digital model that simulates the core functionalities of a vending
machine, including item selection, payment processing, and inventory management.The proposed design
employs a finite state machine (FSM) to manage the different operational states of the vending machine,
such as idle, accepting coins, dispensing items, and providing change. The Verilog code captures the logic
for item selection based on user inputs, the calculation of total payment, and the corresponding actions taken
when sufficient funds are inserted.Simulation results demonstrate that the Verilog implementation
effectively replicates the behavior of a physical vending machine, with features such as coin validation,
multiple item selection, and error handling for insufficient funds. The design's modular architecture allows
for easy modifications and scalability, making it suitable for various vending machine configurations. The
transformative potential of Verilog HDL in creating sophisticated electronic systems like vending machines,
paving the way for future advancements in automated retail solutions. Future work will focus on integrating
advanced features such as remote monitoring and adaptive pricing strategies to further enhance the vending
experience.

UNDER THE GUIDANCE OF TEAM MEMBERS

Mrs. B. SRI LATHA G.SAI 225671568L


Assistant Professor, M.RAMYA SRI 21567T1546
Department of ECE MD.ABDUL RASHEED 21567T1543
B.DEEPIKA 21567T1512
D.MOUNIKA 195671561L

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