Birla Institute of Technology and Science, Pilani, Rajasthan
Analog and Digital VLSI Design (EEE F313/INSTR F313)
1st Semester (2024-2025)
Quiz 9 Date: 11/11/2024 MM: 10 Maximum Time: 15 Minutes
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SOLUTION
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Q1. Consider the circuit shown in Figure 1. The
threshold voltage for NMOS and P-MOS
transistors is 1V and -1V, respectively. Mention
VX and VY in the box provided.
[2 Marks]
Q2. Determine the Boolean logical expression
implemented by the circuit shown in Figure 2 Undefined
VXX=
= 2V (Race)
and mention it in the box provided.
Also, complete the following logic table for the Figure 1 2 Marks
given input combinations only. [3 Marks]
A B S F
AS̅ + BS
0 1 0 0 1 Mark
1 0 1 0 1 Mark
1 Mark
Q3. Determine the Boolean logical expression Figure 2
implemented by the circuit shown in Figure 3 and 22
Figure 2
mention it in the box provided.
Also, complete the following logic table
for the given input combinations only.
[3 Marks]
A S F
1 0 1 Mark
1
1 1
0 1 Mark Figure 3 AS̅ + A
̅S
1 Mark
Q4. If a minimum sized standard CMOS inverter has WN =1 and WP = 2, then the Logical-Effort (LE)
of a three input DYNAMIC NAND GATE is
𝟒𝑪 𝟒 2[2Marks
Marks]
=
𝟑𝑪 𝟑
Logical Effort (g)for every input (A, B, C)
4Wmin (FOR Dynamic NAND)
g = 3Wmin (for CMOS Inverter)
