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Multiplexer and Demultiplexer

Multiplexer and demultiplexer electronic

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anurag9122004
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75 views4 pages

Multiplexer and Demultiplexer

Multiplexer and demultiplexer electronic

Uploaded by

anurag9122004
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Aim: Design and implement 8:1 multiplexer and 1:4 demultiplexer

Required Apparatus: Xilinx Software


i Theory: Multiplexing is the property of combining one or more signals and
transmitting on a single channel. This is achieved by the device multiplexer. A
multiplexer is the most frequently used combinational circuits and important building
block in many in digital systems. This type of multiplexer is referred to as 2n x 1
multiplexer or 2n -to-l multiplexer. An 8-to-l multiplexer consists of eight data
inputs D0 through D7, three input select lines S2 through S0 and a single output line
Y. Depending on the select lines combinations, multiplexer decodes the inputs. The
below figure shows the block diagram of an 8-to-1 multiplexer with enable input that
enable or disable the multiplexer. Since the number data bits given to the MUX are
eight then 3 bits (23-8) are needed to select one of the eight data bits.

Enable E

Inputs 8:1 Output


MUX
+)

Select Lines

Fig 1: 8:1 Mux


Table 1:Truth table of 8:1 Mux
Select Data Inputs Outputs
|S2 S SO Y
0 DO
0 D
D2
D3
D4
DS
1 D6
D7
iii) Programnming:
library IEEE:
use lEEE.std logie ll64.all:

entity mux8 3 is
port (sel : in std logie_vector(2 downto 0):
DO.DID2,D3.D4,D5,D6.D7 enable: in std logic:
Y:outstd logic);
end mux8 3:
architecture behavior of mux8 3 is
begin
if (enable=-0)
then
begin
process (sel, D0,D1,D2,D3,D4,DS,D6,D7)
begin
case sel is
when "000 => Y <-D0;
when "001" => Y <-D1;
when "010" =>Y <=D2;
when "011" => Y <=D3;
when "100" => Y <=D4;
when "101" =>Y <-D5:
when 110" => Y <-D6;
when 111" =>Y<-D7;
when others => Y <-D0;$
end case:;
end process;
else
Y <=0;
end if;
end mux8 3;
1:4Demultiplexer

Ademultiplexer is a combinational logic circuit that receives the information on a single input
and transmitsthe same information over one of 2n possible output lines.
m. hi combinations of the select lines control the selection of
specific output line to be
oonnected to the input at given instant. A l-t0-4 demultiplexer has a single input (D), two
selection lines (SI and S0) and four outputs (YO to Y3). The input data goes to any one of the
four outputs at a given time for a particular combination of select lines.
This demultiplexer is also called as a 2-to-4 demultiplexer which means that two select lines and
4output lines. The block diagram of 1:4 DEMUX is shown below.

Outputs
YO
Input 1:4
Din
DEMUX Y2
Y3

S S0

Fig 2: 1:4 Demultiplexer

Table 2: Truth table of 1:4 Demultiplexer


Data Input Outputs
Din S1 SO Y3 Y2 Y1 YO
D 0 0 0
D 0 1 D
D 0
D D 0
P'rgramming:
library IEE:
LOGC l164.al:
se IEEE.STD
4is
entity denmuxl
port(
Din: in STD LOGIC:
S0,SI:in STD LOGIC:
Y3,Y2.Y1,Y0: out STD LOGIC
):
end demuxl 4:

architecture behavior of demux 4 is


begin
process (Din,S0,S1) is
begin
if (S0 =0' and Sl = 0) then
YO<= Din:
elsif (S0=l' and Sl "0) then
YI <= Din;
elsif (S0=0' and S1='l) then
Y2 <= Din;
else
Y3<= Din:
end if;
end process;
end behavior;
the
Result: Multiplexer and Demultiplexer both are used in communication systems to carry out
multiplexer;
process of data transmission. A De-multiplexer receives the output signals from the
and, at the receiver end, it converts them back to the original form.

Precautions: The system should be handled very carefully.

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