IET Circuits, Devices & Systems

Research Article

Phase-error cancellation technique for ISSN 1751-858X

Received on 18th July 2015
Revised on 16th February 2016
fast-lock phase-locked loop Accepted on 20th February 2016
doi: 10.1049/iet-cds.2015.0201
www.ietdl.org

Zhaoming Ding, Haiqi Liu, Qiang Li ✉

Integrated Systems Lab, University of Electronic Science and Technology of China, Chengdu 610054, People’s Republic of China
✉ E-mail: [email protected]

Abstract: This paper presents a phase-error cancellation (PEC) technique that can be employed to achieve fast lock in
analogue phase-locked loops (PLLs). The PLL works in fast-lock mode during phase and frequency tracking, and is
switched to normal mode after it is almost locked. Unstable system topology is introduced in this system for fast
locking. This PEC technique is proposed to cancel the phase error when the output frequency approaches the target
value. Due to the inherent oscillation nature of the intentionally designed unstable system in fast-lock mode, the time
for PEC can be predicted based on some known parameters. A PLL is simulated in 0.13 µm CMOS process with 1.2 V
supply to verify the proposed PEC technique. Simulation results prove that this technique can reduce at least 87%
settling time as compared with conventional PLLs.

1 Introduction During tracking mode, an auxiliary charge pump is used to obtain a

larger loop bandwidth, while the system is set to oscillate sinusoidally.
Phase-locked loop (PLL)-based frequency synthesiser is an The phase-error cancellation (PEC) technique is employed to cancel
important block in many communication systems [1–7]. Low jitter the phase error at the proper time. With the help of a two-threshold (a
and short locking time are two of the most important requirements coarse threshold and a fine threshold) lock detector, the PLL is
of both analogue PLLs and digital PLLs [8–10]. For analogue switched to normal mode after it almost locks to the input reference
PLLs, to meet the low jitter requirement of signal quality, a signal.
narrow bandwidth is normally necessary to reduce the in-band This paper is organised as follows. The operation principle of the
noise of the reference signal. However, the narrower bandwidth proposed PEC technique is first described in Section 2. Section 3
leads to a longer settling time in PLL [11]. Hence, PLL’s discusses the design considerations of the PLL employing this
bandwidth design is a trade-off between jitter and locking speed. technique. The simulation results are presented in Section
To avoid the conflict between signal quality and settling time, a 4. Finally, Section 5 concludes this paper.
pre-determined PLL is proposed in [12]. In [12], a mixed-signal
voltage controlled oscillator (VCO) is designed where the output
frequency can be set by a digital control signal. The control signal 2 Operation principle
changes with PLL’s division ratio, N, to set the output frequency
to a proper value. However, it is very difficult to design a VCO PLL locks not only the frequency but also the phase of the input
which is insensitive to process, voltage and temperature (PVT) reference signal. During PLL locking process, the phase of output
changes. is not the same as that of the input when the output of PLL is
Dynamic bandwidth control [13–18] is an efficient way to solve getting close to the target frequency. Then extra settling time is
the conflict between signal quality and settling time. To ensure caused here, which is named overshoot. If the PLL can reach the
loop stability, the loop bandwidth is limited to 10% of the input target frequency quickly and the phase error between the input
reference frequency. Hybrid PLL combining fractional-N and signal and the output signal is cancelled, the locking time should
integer-N modes is proposed in [13], in which PLL is switched to be very short. To implement this PEC, two essential problems
fractional-N mode during tracking to allow for a larger input should be solved, i.e. how and when to cancel the phase error.
reference frequency, so that the loop bandwidth can be maximised.
In [15], an adaptive bandwidth control PLL is employed, where
2.1 Sinusoidal oscillation
the charge-pump current is designed to be directly proportional
to the phase error. The bandwidth is large in fast-lock mode when Stability is one of the most important considerations in PLL system
the phase error is large, and is small enough for signal quality design [21, 22]. Designers in this field have developed a large
when the phase error is small. However, PLLs in [13, 15] only amount of methods to avoid oscillation. Fig. 1 shows the
deal with the bandwidth problem. The overshoot, which is not normalised unit step response of the second-order system with
covered in above works, is also a limiting factor for fast locking. different damping factors, while the bandwidth remains the same.
Overshoot is another reason for PLL to take a long time to settle Conclusions can be made that a smaller damping factor leads to
[19, 20]. In order to minimise the overshoot effect on settling time, shorter time to cross the final frequency for the first time despite
the phase error should be removed when the output frequency of the overshoot. If the overshoot can be dealt with, a damping
approaches the target value. A dynamic phase-error compensation factor of 0 will be the best for fast locking.
technique is employed in [20] to compensate phase error during Fig. 2 shows the structure of PLL with a damping factor of 0. The
PLL tracking. However, the damping factor of this system is transfer function of the system in Fig. 2 can be written as
related to the gain of VCO, which causes degradation in settling
time when PVT varies.
This paper presents a novel technique to reduce PLL’s settling time ff out (s) N v2
= H(s) = 2 div n2 , (1)
while maintaining the signal quality with small loop bandwidth. ff ref (s) s + vn

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& The Institution of Engineering and Technology 2016 417
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The reason for overshoot is that the phase error is not zero when the
PLL’s output reaches the target frequency. If the phase error can be
cancelled when PLL’s output frequency is close to the target value,
settling time due to the overshoot can be dramatically reduced.
Fig. 3 shows the conceptual output frequency of PEC. Solid line
with ‘∗’ shows the frequency response of (3). If the phase error of
input and output signal is cancelled at time t, no matter t is larger
or smaller than π/(2ωn1), similar as mentioned in Section 2.1, the
output frequency of the PLL is
 
vfout (t) = N1 v0 − N1 v0 − v1 cos [vn1 (t − t)], t ≥ t, (5)

ω1 is the output frequency at t. From (3) it can be derived that

 
v1 = N1 v0 − N1 v0 − N0 v0 cos (vn1 t), t = t. (6)

According to (5) and (6), we write

 
vfout (t) = N1 v0 − N1 v0 − N0 v0
(7)
cos [vn1 (t − t)] cos (vn1 t), t ≥ t.
Fig. 1 Normalised unit step response of the second-order system with
different damping factors Hence, the output of the PLL can be plotted as solid line with mark
‘◦’. The output frequency at the time of 2t can be written as

v2 = N1 v0 − N1 v0 − N0 v0 cos2 (vn1 t),

 
t = 2t. (8)

Similarly, if the phase error is cancelled at time 2t, we can get

 
vfout (t) = N1 v0 − N1 v0 − v2 cos [vn1 (t − 2t)], t ≥ 2t, (9)

From (8) and (9), we get

 
Fig. 2 Structure of oscillation PLL vfout (t) = N1 v0 − N1 v0 − N0 v0
(10)
cos [vn1 (t − 2t)] cos2 (vn1 t), t ≥ 2t,
where
which is plotted in solid line with mark ‘□’. The output frequency at








the time of 3t can be written as
Icp Kvco
vn = . (2)
Ndiv C v3 = N1 v0 − N1 v0 − N0 v0 cos3 (vn1 t),
 
t = 3t. (11)

Assuming that the phase error is cancelled at every interval of t, the

ωn is called the intrinsic frequency of this unstable system. Assuming output frequency can be derived as see (12)
the PLL in Fig. 2 is locked with a input frequency ω0 and the division
ratio is Ndiv = N0, when Ndiv steps from N0 to N1 and the input The dashed line in Fig. 3 shows the actual output frequency of PLL.
frequency remains at ω0, we have The solid lines with special marks indicate the projected oscillation
output frequencies without further PEC involvement. Conclusion
can be made from (12). The closer ωn1t is close to π/2, the faster ωk
 
vfout (t) = N1 v0 − N1 v0 − N0 v0 cos (vn1 t) (3)
approaches N1ω0, which is the target frequency of PLL.
where
2.3 Comparison between continuous-time ideal models









Icp Kvco To reduce the locking time of PLL, a regular way is to change the
vn1 = . (4)
N1 C bandwidth [14]. A wide bandwidth is needed for fast lock; however,
a larger bandwidth contributes to more in-band noise. A simple way
to meet those requirements is to apply large current of charge pump
The output frequency of the PLL oscillates sinusoidally at an
during tracking, and small current after PLL is locked, which is
intrinsic frequency of ωn1.
called bandwidth switching. Other techniques to reduce lock time
via frequency tracking (coarse tuning) followed by phase tracking
2.2 Theory of PEC (fine tuning) are given in [23–25]. These techniques employ
successive approximation register and flash algorithms.
Overshoot is a common phenomenon in PLL locking process. PLL Fig. 4 shows the system-level model of the PEC PLL. Modules in
often needs extra time before locking when severe overshoot occurs. red dashed line show the realisation of PEC in behavioural model


vfout (t) = N1 v0 − N1 v0 − N0 v0 cos [vn1 (t − (k − 1)t)]cosk−1 (vn1 t), (k − 1)t ≤ t ≤ k t,
 
(12)
vk = N1 v0 − N1 v0 − N0 v0 cosk (vn1 t), t = k t
 

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Fig. 3 Conceptual output frequency
a t < π/(2ωn1)
b t > π/(2ωn1)
c Projected output frequencies without further PEC involvement
d Actual output frequency with PEC involved

(realisation in real circuits will be discussed in the next section). from which we can see that the phase error of the PLL adopting
Signal rst is the enable signal of the PEC. S/H is a sample and PEC technique is cancelled at every fixed period thus the locking
hold module time of our proposed PLL is much shorter than the other two
topologies.
ftemp = fn + ffref − (fdiv out + fn ) = ffref − fdiv out (13)

3 PEC PLL design

fn is the output of S/H after n times of low level rst. When the next
low level of rst occurs Some design considerations for implementing our proposed PEC
technique in PLL are discussed in this section. Simulations in
fn+1 = ftemp = ffref − fdiv (14) Section 2.3 show that PEC technique can greatly accelerate the
out
settling process of PLLs. However, some practical problems
should be addressed: how and when to realise PEC in circuits design.
E = ffref − (fdiv out + fn+1 ) = 0 (15)

When rst is low, phase error is removed from the output of the 3.1 PEC realisation
divider.
To demonstrate the effectiveness of our proposed technique, three Fig. 6a shows the conceptual operation diagram of the divider designed
types of PLL in Matlab model are designed for comparison. Fig. 5 for PEC. The count number of divider (count_num) is reset to 0 and the
shows the three types of PLLs in ideal continuous-time Matlab output signal of divider (div_out) is set to high, when PEC signal (rst) is
model with different locking time. The system parameters of the low. Additionally, rst is synchronous to the rising edge of reference
conventional PLL and the bandwidth-switching PLL are the same signal (fref). The time between two adjacent count_num should be a
except for the charge-pump current during tracking phase. In period of fout. However, the time between count_num of 0 and 1 do
tracking phase, the bandwidth-switching PLL’s change pump not meet this. The count_num of 0 should be at the rising edge of
current is 15 times as much as that of the conventional PLL. The fout, which indicates div_out should be high at where X is. Hence,
solid line represents a PLL employing PEC technique, which has the phase error between fref and div_out is 2π × terr/Tref, where Tref is
the same system parameters as the bandwidth-switching PLL; and the period of the input reference signal. terr is apparently smaller than
ωn1t = 0.9 × π/2 (the calculation of t will be discussed in the next a period of VCO output (fout). If the period of fref is much larger
section). The marks in the figure indicate the locking time of the than that of fout, then we get Tref >>terr. The phase error is
PLLs. Fig. 5b shows the phase-error response of the three PLLs, approximately equal to 0, when rst is low. This signal, rst, is also
used to reset PFD in Fig. 6b. Therefore, the phase error between fref
and div_out is cancelled when rst is low. If rst is low every M cycles
of fref, t = M × Tref. Section 2.2 mentioned that ωn1t should be close
to π/2. Hence, we can get

p p
t = M × Tref ≃ , and M ≃ . (16)
2vn1 2vn1 Tref

3.2 System design

This PEC technique has two modes, fast-lock mode and normal
mode. The PLL works in fast-lock mode when it is out of lock.
PEC technique and sinusoidal oscillation are introduced in this
Fig. 4 System-level model of the PEC PLL mode. Meanwhile, auxiliary charge pump is also utilised to

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& The Institution of Engineering and Technology 2016 419
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Fig. 5 Three types of PLLs with different locking time
a Frequency response
b Phase-error response

to fast-lock mode. Meanwhile, En1 and En2 are set high to bypass
the resistor in the loop filter and to connect the auxiliary charge
pump into the system loop.
From (4), the intrinsic oscillation frequency of fast-lock mode can
be written as




















 
Imain + IAux Kvco
Fig. 6 Details of PEC realisation vn1 = . (17)
N1 (C1 + C2 )
a Conceptual operation diagram of divider
b Block diagram of PFD
Hence, from (16) we can have




















p N (C + C2 )
M≃  1 1  . (18)
2Tref Imain + IAux Kvco

The lock detector has two detection thresholds. If the lock detector
detects that the PLL is locked with coarse threshold (Lock_c
high), the enable generator changes En1 and En2 to low upon the
next falling edge of rst. En1 of logic low disables auxiliary charge
pump, and low En2 connects the resistor into loop filter, which
indicates PLL is working at normal mode. In Fig. 7, a delay
module is added to compensate the delay time for generating rst
Fig. 7 Topology of PEC PLL and clearing phase error, which guarantees that no extra phase
error is caused by the delay of other modules when clearing phase
error. Finally, if the lock detector detects that the PLL is locked
improve fast locking. When PLL is almost locked, it is switched to with fine threshold, it will set Lock_f high.
normal mode for further settling and for low jitter operation. Fig. 7
shows the topology of the proposed PLL with PEC technique. 3.3 Two-threshold lock detector
Detailed timing diagram is presented in Fig. 8. When Ndiv changes
from N0 to N1, lock detector changes Lock_c and Lock_f to low Lock detector plays a very important role in this whole PEC PLL,
level, which indicates that the PLL is out of lock and is switched which determines the work mode of the PLL. Coarse threshold
and fine threshold are both needed in the PEC PLL. Coarse
threshold is used to check whether the PLL should end
the fast-lock mode. Fine threshold indicates the locking state of
the PLL.
Fig. 9 shows the structure of the two-threshold lock detector. The
XOR gate generates signal CLR by the phase error between fref and
div_out, which clears the count number of the counter. Hence, the up
and down signals are the number of the rising or falling edge of fout
during phase error, respectively. If up and down are both larger than
zero, it means the phase error between fref and div_out is larger than
half period of fout. Then rst_f goes low to reset the following
counter. Similarly, up and down are both larger than one, it means
Fig. 8 Detailed timing diagram of PEC PLL the phase error between fref and div_out is larger than one and

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Fig. 9 Structure of the two-threshold lock detector

Table 2 Settling time comparison with different frequency changes

Output frequency Conventional, Bandwidth This
change, GHz µs switching, µs work, µs

2.32–2.56 24.24 9.42 2.48

2.56–2.32 34.28 9.87 2.48
2.32–2.40 21.85 8.27 1.78
2.40–2.56 18.68 6.40 2.48
2.56–2.40 19.22 6.64 1.80
2.40–2.32 21.68 8.82 2.48

Fig. 10 Timing diagram of the two-threshold lock detector

4 Simulation results
Table 1 Control signal of three types of PLLs The PEC technique has been verified in a 0.13 µm Complementary
PLLs rst En1 En2 Metal-Oxide-Semiconductor (CMOS) PLL with 1.2 V supply
voltage. In order to compare the efficiency of the PEC technique,
conventional high low low three types of PLLs are simulated, i.e. conventional PLL, bandwidth
bandwidth switching high high low switching PLL with auxiliary charge pump and PLL with PEC
PEC Fig. 8 technique. Enable generator in Fig. 7 generates different sets of
signals for each type of PLL. Details are summarised in Table 1.
Fig. 11a shows the frequency response of conventional PLL and
half period of fout. Then rst_c goes low. The detailed timing diagram the PLL with PEC technique when division ratio changes.
is presented in Fig. 10. The last two counters count the number of Fig. 11b shows the detailed output frequency of PEC PLL. Due to
rising edge of fref, when Lock_c or Lock_f is low. If rst_c keeps a non-zero parasitic resistance of the switch shown in Fig. 7,
high for 16 period of fref, Lock_c gets high to change the PLL voltage spikes can be seen in Fig. 11b when PLL is in fast-lock
from fast-lock mode to normal mode. If rst_f keeps high for 32 mode. The settling time of several frequency changes are listed in
period of fref, Lock_f is changed from low to high, which means Table 2. According to the simulation results, the PLL employing
the PLL is locked. Hence, the threshold for coarse lock is one and PEC technique can achieve at least 86% reduction in settling time
half period of fout, and the threshold for fine lock is half period of compared with the conventional PLL. Compared with bandwidth
fout. switching PLL, PEC technique can also reduce more than half of
the settling time.

Fig. 11 PLL locking process

a Conventional PLL and PLL with PEC
b Detailed locking process of PLL with PEC

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Table 3 Comparison table
JSSC’08 [13] JSSC’10 [20] EL’10 [16] JSSC’14 [19] This work

technology, nm 180 180 180 65 130

input frequency, MHz 64 10 NA 139–148.5 10
output frequency, GHz 2.368–2.496 5.27–5.6 1 8.9–9.5 2.32–2.56
locking time conventional, µs 80 60 5 4.23 18.68a 11.30b
proposed, µs 20 20 1.4 1.58 2.48a 2.50b
locking time reduction 75% 66% 72% 63% 87% 78%

a
Worst pre-layout simulation result with no PVT variation
b
Worst pre-layout simulation result with PVT variation

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