LPC2129 Datasheet

LPC2119/LPC2129
Single-chip 16/32-bit microcontrollers; 128/256 kB ISP/IAP

Flash with 10-bit ADC and CAN
Rev. 03 Ñ 22 December 2004 Product data
1. General description
The LPC2119/LPC2129 are based on a 16/32 bit ARM7TDMI-S“ CPU with real-time
emulation and embedded trace support, together with 128/256 kilobytes (kB) of
embedded high speed ßash memory. A 128-bit wide memory interface and a unique
accelerator architecture enable 32-bit code execution at maximum clock rate. For
critical code size applications, the alternative 16-bit Thumb¤ Mode reduces code by
more than 30 % with minimal performance penalty.
With their compact 64 pin package, low power consumption, various 32-bit timers,
4-channel 10-bit ADC, 2 advanced CAN channels, PWM channels and 46 GPIO lines
with up to 9 external interrupt pins these microcontrollers are particularly suitable for
automotive and industrial control applications as well as medical systems and
fault-tolerant maintenance buses. With a wide range of additional serial
communications interfaces, they are also suited for communication gateways and
protocol converters as well as many other general-purpose applications.
2. Features
2.1 Key features

n 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
n 16 kB on-chip Static RAM.
n 128/256 kB on-chip Flash Program Memory. 128-bit wide interface/accelerator
enables high speed 60 MHz operation.
n In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
boot-loader software. Flash programming takes 1 ms per 512 byte line. Single
sector or full chip erase takes 400 ms.
n EmbeddedICE-RT interface enables breakpoints and watch points. Interrupt
service routines can continue to execute while the foreground task is debugged
with the on-chip RealMonitor“ software.
n Embedded Trace Macrocell enables non-intrusive high speed real-time tracing of
instruction execution.
n Two interconnected CAN interfaces with advanced acceptance Þlters.
n Four channel 10-bit A/D converter with conversion time as low as 2.44 m s.
n Multiple serial interfaces including two UARTs (16C550), Fast I2C (400 kbits/s)
and two SPIs
n 60 MHz maximum CPU clock available from programmable on-chip
Phase-Locked Loop with settling time of 100 m s.
n Vectored Interrupt Controller with conÞgurable priorities and vector addresses.
n Two 32-bit timers (with four capture and four compare channels), PWM unit (six
outputs), Real Time Clock and Watchdog.
Philips Semiconductors LPC2119/LPC2129
Single-chip 16/32-bit microcontrollers
n Up to forty-six 5 V tolerant general purpose I/O pins. Up to nine edge or level

sensitive external interrupt pins available.
n On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
n Two low power modes, Idle and Power-down.
n Processor wake-up from Power-down mode via external interrupt.
n Individual enable/disable of peripheral functions for power optimization.
n Dual power supply:
u CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ±0.15 V).
u I/O power supply range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O
pads.
3. Ordering information
Table 1: Ordering information
Type number Package
Name Description Version
LPC2119FBD64 LQFP64 plastic low proÞle quad ßat package; 64 leads; SOT314-2
body 10 ´ 10 ´ 1.4 mm
LPC2129FBD64 LQFP64 plastic low proÞle quad ßat package; 64 leads; SOT314-2
body 10 ´ 10 ´ 1.4 mm
3.1 Ordering options

Table 2: Part options
Type number Flash memory RAM CAN Temperature
range (°C)
LPC2119FBD64 128 kB 16 kB 2 channels - 40 to +85
LPC2129FBD64 256 kB 16 kB 2 channels - 40 to +85
9397 750 13146 ' Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data Rev. 03 Ñ 22 December 2004 2 of 34

4. Block diagram
TRST(1)
TMS(1)
TDO(1)
TCK(1)
TDI(1)
RTCK
XTAL1
XTAL2
V1.8
RST
VSS
V3
EMULATION TRACE
TEST/DEBUG
INTERFACE
SYSTEM
MODULE
PLL
FUNCTIONS
ARM7TDMI-S system
clock VECTORED INTERRUPT
AHB BRIDGE CONTROLLER
ARM7 LOCAL BUS AMBA AHB

(Advanced High-performance Bus)
INTERNAL SRAM INTERNAL

CONTROLLER FLASH AHB
CONTROLLER DECODER
16 kB AHB TO VPB VPB

128/256 kB BRIDGE DIVIDER
SRAM
FLASH
EINT0* APB
EINT1* SCL*
EINT2*
EXTERNAL I2C SERIAL
INTERRUPTS INTERFACE SDA*
EINT3*
SCK*
8 x CAP*
CAPTURE/ MOSI*
COMPARE SPI SERIAL
MISO*
8 x MAT* INTERFACE 0 & 1
TIMER0/TIMER1
SSEL*
TxD0,1*
PWM1..6* RxD0,1*
PWM0 UART0/UART1
MODEM CONTROL
(6 PINS)*
P0 (30 PINS)
GENERAL
PURPOSE I/O REAL TIME CLOCK
P1.31:16
Ain3:0* 10-BIT WATCHDOG

A/D CONVERTER TIMER
RD2:1*
CAN INTERFACE 0 & 1 SYSTEM
TD2:1* ACCEPTANCE FILTERS CONTROL
*Shared with GPIO 002aaa662
(1) When test/debug interface is used, GPIO/other function sharing these pins are not available.
Fig 1. Block diagram.

5. Pinning information
5.1 Pinning
54 P0.19/MAT1.2/MOSI1/CAP1.2
53 P0.18/CAP1.3/MISO1/MAT1.3
55 P0.20/MAT1.3/SSEL1/EINT3
58 VSSA_PLL
52 P1.30/TMS
56 P1.29/TCK
64 P1.27/TD0
60 P1.28/TDI
57 RESET
62 XTAL1
61 XTAL2
59 VSSA
63 V18A
50 VSS
49 V18
51 V3
handbook, full pagewidth
P0.21/PWM5/CAP1.3 1 48 P1.20/TRACESYNC
P0.22/CAP0.0/MAT0.0 2 47 P0.17/CAP1.2/SCK1/MAT1.2
P0.23/RD2 3 46 P0.16/EINT0/MAT0.2/CAP0.2
P1.19/TRACEPKT3 4 45 P0.15/RI1/EINT2
P0.24/TD2 5 44 P1.21/PIPESTAT0
VSS 6 43 V3
V3A 7 42 VSS
P1.18/TRACEPKT2 8 41 P0.14/DCD1/EINT1
LPC2119/LPC2129
P0.25/RD1 9 40 P1.22/PIPESTAT1
TD1 10 39 P0.13/DTR1/MAT1.1
P0.27/AIN0/CAP0.1/MAT0.1 11 38 P0.12/DSR1/MAT1.0
P1.17/TRACEPKT1 12 37 P0.11/CTS1/CAP1.1
P0.28/AIN1/CAP0.2/MAT0.2 13 36 P1.23/PIPESTAT2
P0.29/AIN2/CAP0.3/MAT0.3 14 35 P0.10/RTS1/CAP1.0
P0.30/AIN3/EINT3/CAP0.0 15 34 P0.9/RxD1/PWM6/EINT3
P1.16/TRACEPKT0 16 33 P0.8/TxD1/PWM4
V18 17
VSS 18
P0.0/TxD0/PWM1 19
P1.31/TRST 20
P0.1/RxD0/PWM3/EINT0 21
P0.2/SCL/CAP0.0 22
V3 23
P1.26/RTCK 24
VSS 25
P0.3/SDA/MAT0.0/EINT1 26
P0.4/SCK0/CAP0.1 27
P1.25/EXTIN0 28
P0.5/MISO0/MAT0.1 29
P0.6/MOSI0/CAP0.2 30
P0.7/SSEL0/PWM2/EINT2 31
P1.24/TRACECLK 32
002aaa663
Fig 2. Pinning.

5.2 Pin description

Table 3: Pin description
Symbol Pin Type Description
P0.0 to P0.31 19, 21, 22, I/O Port 0: Port 0 is a 32-bit bi-directional I/O port with individual direction
26, 27, controls for each bit. The operation of port 0 pins depends upon the pin
29-31, 33-35, function selected via the Pin Connect Block. Pins 26 and 31 of port 0 are not
37-39, 41, available.
45-47, 53-55,
1-3, 5, 9, 11,
13-15
P0.0 19 O TxD0 Ñ Transmitter output for UART0.
O PWM1 Ñ Pulse Width Modulator output 1.
P0.1 21 I RxD0 Ñ Receiver input for UART0.
I EINT0 Ñ External interrupt 0 input
P0.2 22 I/O SCL Ñ I2C clock input/output. Open drain output (for I2C compliance).
I CAP0.0 Ñ Capture input for Timer 0, channel 0.
P0.3 26 I/O SDA Ñ I2C data input/output. Open drain output (for I2C compliance).
O MAT0.0 Ñ Match output for Timer 0, channel 0.
I EINT1 Ñ External interrupt 1 input.
P0.4 27 I/O SCK0 Ñ Serial clock for SPI0. SPI“ clock output from master or input to
slave.
P0.5 29 I/O MISO0 Ñ Master In Slave OUT for SPI0. Data input to SPI master or data
output from SPI slave.
P0.6 30 I/O MOSI0 Ñ Master Out Slave In for SPI0. Data output from SPI master or data
input to SPI slave.
P0.7 31 I SSEL0 Ñ Slave Select for SPI0. Selects the SPI interface as a slave.
P0.8 33 O TxD1 Ñ Transmitter output for UART1.
P0.9 34 I RxD1 Ñ Receiver input for UART1.
P0.10 35 O RTS1 Ñ Request to Send output for UART1.

Table 3: Pin descriptionÉcontinued

P0.11 37 I CTS1 Ñ Clear to Send input for UART1.
P0.12 38 I DSR1 Ñ Data Set Ready input for UART1.
P0.13 39 O DTR1 Ñ Data Terminal Ready output for UART1.
P0.14 41 I DCD1 Ñ Data Carrier Detect input for UART1.
Note: LOW on this pin while RESET is LOW forces on-chip boot-loader to
take control of the part after reset.
P0.15 45 I RI1 Ñ Ring Indicator input for UART1.
P0.16 46 I EINT0 Ñ External interrupt 0 input.
P0.17 47 I CAP1.2 Ñ Capture input for Timer 1, channel 2.
I/O SCK1 Ñ Serial Clock for SPI1. SPI clock output from master or input to slave.
I/O MISO1 Ñ Master In Slave Out for SPI1. Data input to SPI master or data
output from SPI slave.
P0.19 54 O MAT1.2 Ñ Match output for Timer 1, channel 2.
I/O MOSI1 Ñ Master Out Slave In for SPI1. Data output from SPI master or data
input to SPI slave.
P0.20 55 O MAT1.3 Ñ Match output for Timer 1, channel 3.
I SSEL1 Ñ Slave Select for SPI1. Selects the SPI interface as a slave.
P0.21 1 O PWM5 Ñ Pulse Width Modulator output 5.
P0.23 3 I RD2 Ñ CAN2 receiver input.
P0.24 5 O TD2 Ñ CAN2 transmitter output.
P0.25 39 O RD1 Ñ CAN1 receiver input.
P0.27 11 I AIN0 Ñ A/D converter, input 0. This analog input is always connected to its
pin.


pin.
pin.
I CAP0.3 Ñ Capture input for Timer 0, Channel 3.
pin.
P1.0 to P1.31 16, 12, 8, 4, I/O Port 1: Port 1 is a 32-bit bi-directional I/O port with individual direction
48, 44, 40, controls for each bit. The operation of port 1 pins depends upon the pin
36, 32, 28, function selected via the Pin Connect Block. Pins 0 through 15 of port 1 are
24, 64, 60, not available.
56, 52, 20
P1.16 16 O TRACEPKT0 Ñ Trace Packet, bit 0. Standard I/O port with internal pull-up.
P1.20 48 O TRACESYNC Ñ Trace Synchronization. Standard I/O port with internal
pull-up.
Note: LOW on this pin while RESET is LOW, enables pins P1.25:16 to
operate as Trace port after reset.
P1.21 44 O PIPESTAT0 Ñ Pipeline Status, bit 0. Standard I/O port with internal pull-up.
P1.24 32 O TRACECLK Ñ Trace Clock. Standard I/O port with internal pull-up.
P1.25 28 I EXTIN0 Ñ External Trigger Input. Standard I/O with internal pull-up.
P1.26 24 I/O RTCK Ñ Returned Test Clock output. Extra signal added to the JTAG port.
Assists debugger synchronization when processor frequency varies.
Bi-directional pin with internal pull-up.
Note: LOW on this pin while RESET is LOW, enables pins P1.31:26 to
operate as Debug port after reset.
P1.27 64 O TDO Ñ Test Data out for JTAG interface.
P1.28 60 I TDI Ñ Test Data in for JTAG interface.
P1.29 56 I TCK Ñ Test Clock for JTAG interface.
P1.30 52 I TMS Ñ Test Mode Select for JTAG interface.
P1.31 20 I TRST Ñ Test Reset for JTAG interface.
TD1 10 O TD1 Ñ CAN1 transmitter output.
RESET 57 I External Reset input: A LOW on this pin resets the device, causing I/O ports
and peripherals to take on their default states, and processor execution to
begin at address 0. TTL with hysteresis, 5 V tolerant.


XTAL1 62 I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 61 O Output from the oscillator ampliÞer.
VSS 6, 18, 25, 42, I Ground: 0 V reference.
50
VSSA 59 I Analog Ground: 0 V reference. This should nominally be the same voltage
as VSS, but should be isolated to minimize noise and error.
VSSA_PLL 58 I PLL Analog Ground: 0 V reference. This should nominally be the same
voltage as VSS, but should be isolated to minimize noise and error.
V18 17, 49 I 1.8 V Core Power Supply: This is the power supply voltage for internal
circuitry.
V18A 63 I Analog 1.8 V Core Power Supply: This is the power supply voltage for
internal circuitry. This should be nominally the same voltage as V18 but should
be isolated to minimize noise and error.
V3 23, 43, 51 I 3.3 V Pad Power Supply: This is the power supply voltage for the I/O ports.
V3A 7 I Analog 3.3 V Pad Power Supply: This should be nominally the same
voltage as V3 but should be isolated to minimize noise and error.

6. Functional description
Details of the LPC2119/LPC2129 systems and peripheral functions are described in
the following sections.
6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM¤ architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and
related decode mechanism are much simpler than those of microprogrammed
Complex Instruction Set Computers. This simplicity results in a high instruction
throughput and impressive real-time interrupt response from a small and
cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory
systems can operate continuously. Typically, while one instruction is being executed,
its successor is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
¥ The standard 32-bit ARM set.

¥ A 16-bit Thumb set.
The Thumb setÕs 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARMÕs performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb
code operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
6.2 On-Chip Flash program memory

The LPC2119/LPC2129 incorporate a 128 kB and 256 kB Flash memory system
respectively. This memory may be used for both code and data storage.
Programming of the Flash memory may be accomplished in several ways. It may be
programmed In System via the serial port. The application program may also erase
and/or program the Flash while the application is running, allowing a great degree of
ßexibility for data storage Þeld Þrmware upgrades, etc. When on-chip bootloader is
used, 120/248 kB of Flash memory is available for user code.
The LPC2119/LPC2129 Flash memory provides a minimum of 100,000 erase/write

cycles and 20 years of data retention.
On-chip bootloader (as of revision 1.60) provides Code Read Protection (CRP) for the
LPC2119/LPC2129 on-chip Flash memory. When the CRP is enabled, the JTAG
debug port and ISP commands accessing either the on-chip RAM or Flash memory

are disabled. However, the ISP Flash Erase command can be executed at any time
(no matter whether the CRP is on or off). Removal of CRP is achieved by erasure of
full on-chip user Flash. With the CRP off, full access to the chip via the JTAG and/or
ISP is restored.
6.3 On-Chip static RAM

On-Chip static RAM may be used for code and/or data storage. The SRAM may be
accessed as 8-bits, 16-bits, and 32-bits. The LPC2119/LPC2129 provide 16 kB of
static RAM.
6.4 Memory map

The LPC2119/LPC2129 memory maps incorporate several distinct regions, as shown
in the following Þgures.
In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in
either Flash memory (the default) or on-chip static RAM. This is described in Section
6.20 ÒSystem controlÓ .

4.0 GB 0xFFFF FFFF

AHB PERIPHERALS
0xF000 0000
3.75 GB
0xEFFF FFFF
VPB PERIPHERALS
0xE000 0000
3.5 GB 0xDFFF FFFF
3.0 GB 0xC000 0000
RESERVED ADDRESS SPACE
0x8000 0000
2.0 GB 0x7FFF FFFF
BOOT BLOCK (RE-MAPPED FROM
ON-CHIP FLASH MEMORY 0x7FFF E000
0x7FFF DFFF
0x4001 0000
0x4000 3FFF
16 KBYTE ON-CHIP STATIC RAM
0x4000 0000
1.0 GB 0x3FFF FFFF
0x0004 0000
0x0003 FFFF
256 KBYTE ON-CHIP FLASH MEMORY (LPC2129)
0x0002 0000
0x0001 FFFF
128 KBYTE ON-CHIP FLASH MEMORY (LPC2119)
0x0000 0000
0.0 GB
002aaa664
Fig 3. LPC2119/LPC2129 memory map.
6.5 Interrupt controller

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and
categorizes them as FIQ, vectored IRQ, and non-vectored IRQ as deÞned by
programmable settings. The programmable assignment scheme means that priorities
of interrupts from the various peripherals can be dynamically assigned and adjusted.
Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is
assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the
ARM processor. The fastest possible FIQ latency is achieved when only one request
is classiÞed as FIQ, because then the FIQ service routine can simply start dealing
with that device. But if more than one request is assigned to the FIQ class, the FIQ
service routine can read a word from the VIC that identiÞes which FIQ source(s) is
(are) requesting an interrupt.

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be
assigned to this category. Any of the interrupt requests can be assigned to any of the
16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the
lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to
produce the IRQ signal to the ARM processor. The IRQ service routine can start by
reading a register from the VIC and jumping there. If any of the vectored IRQs are
requesting, the VIC provides the address of the highest-priority requesting IRQs
service routine, otherwise it provides the address of a default routine that is shared by
all the non-vectored IRQs. The default routine can read another VIC register to see
what IRQs are active.
6.5.1 Interrupt sources

Table 4 lists the interrupt sources for each peripheral function. Each peripheral device
has one interrupt line connected to the Vectored Interrupt Controller, but may have
several internal interrupt ßags. Individual interrupt ßags may also represent more than
one interrupt source.
Table 4: Interrupt sources

Block Flag(s) VIC channel #
WDT Watchdog Interrupt (WDINT) 0
- Reserved for software interrupts only 1
ARM Core Embedded ICE, DbgCommRx 2
ARM Core Embedded ICE, DbgCommTx 3
Timer 0 Match 0 - 3 (MR0, MR1, MR2, MR3) 4
Capture 0 - 3 (CR0, CR1, CR2, CR3)
Timer 1 Match 0 - 3 (MR0, MR1, MR2, MR3) 5
Capture 0 - 3 (CR0, CR1, CR2, CR3)
UART0 Rx Line Status (RLS) 6
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
UART1 Rx Line Status (RLS) 7
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI)
PWM0 Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) 8
I2 C SI (state change) 9
SPI0 SPIF, MODF 10
SPI1 SPIF, MODF 11
PLL PLL Lock (PLOCK) 12
RTC RTCCIF (Counter Increment), RTCALF (Alarm) 13

Table 4: Interrupt sourcesÉcontinued

Block Flag(s) VIC channel #
System Control External Interrupt 0 (EINT0) 14
External Interrupt 1 (EINT1) 15
A/D A/D Converter 18
CAN CAN1, CAN2 and Acceptance Filter 19-23
6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than
one function. ConÞguration registers control the multiplexers to allow connection
between the pin and the on chip peripherals. Peripherals should be connected to the
appropriate pins prior to being activated, and prior to any related interrupt(s) being
enabled. Activity of any enabled peripheral function that is not mapped to a related
pin should be considered undeÞned.
The Pin Control Module contains three registers as shown in Table 5.
Table 5:
Address Name Description Access
0xE002C000 PINSEL0 Pin function select register 0 Read/Write
6.7 Pin function select register 0 (PINSEL0 - 0xE002C000)

The PINSEL0 register controls the functions of the pins as per the settings listed in
Table 6. The direction control bit in the IODIR register is effective only when the GPIO
function is selected for a pin. For other functions, direction is controlled automatically.
Settings other than those shown in Table 6 are reserved, and should not be used
Table 6: Pin function select register 0 (PINSEL0 - 0xE002C000)

PINSEL0 Pin name Value Function Value after Reset
1:0 P0.0 0 0 GPIO Port 0.0 0
0 1 TxD (UART0)
1 0 PWM1
1 1 Reserved
3:2 P0.1 0 0 GPIO Port 0.1 0
0 1 RxD (UART0)
1 0 PWM3
1 1 EINT0
5:4 P0.2 0 0 GPIO Port 0.2 0
0 1 SCL (I2C)
1 0 Capture 0.0 (Timer 0)
1 1 Reserved

Table 6: Pin function select register 0 (PINSEL0 - 0xE002C000)Écontinued

7:6 P0.3 0 0 GPIO Port 0.3 0
0 1 SDA (I2C)
1 0 Match 0.0 (Timer 0)
1 1 EINT1
9:8 P0.4 0 0 GPIO Port 0.4 0
0 1 SCK (SPI0)
1 1 Reserved
11:10 P0.5 0 0 GPIO Port 0.5 0
0 1 MISO (SPI0)
1 1 Reserved
13:12 P0.6 0 0 GPIO Port 0.6 0
0 1 MOSI (SPI0)
1 1 Reserved
15:14 P0.7 0 0 GPIO Port 0.7 0
0 1 SSEL (SPI0)
1 0 PWM2
1 1 EINT2
17:16 P0.8 0 0 GPIO Port 0.8 0
0 1 TxD UART1
1 0 PWM4
1 1 Reserved
19:18 P0.9 0 0 GPIO Port 0.9 0
0 1 RxD (UART1)
1 0 PWM6
1 1 EINT3
21:20 P0.10 0 0 GPIO Port 0.10 0
0 1 RTS (UART1)
1 1 Reserved
23:22 P0.11 0 0 GPIO Port 0.11 0
0 1 CTS (UART1)
1 1 Reserved
25:24 P0.12 0 0 GPIO Port 0.12 0
0 1 DSR (UART1)
1 1 Reserved


27:26 P0.13 0 0 GPIO Port 0.13 0
0 1 DTR (UART1)
1 1 Reserved
29:28 P0.14 0 0 GPIO Port 0.14 0
0 1 DCD (UART1)
1 0 EINT1
1 1 Reserved
31:30 P0.15 0 0 GPIO Port 0.15 0
0 1 RI (UART1)
1 0 EINT2
1 1 Reserved

function is selected for a pin. For other functions direction is controlled automatically.
Settings other than those shown in the table are reserved, and should not be used.

PINSEL1 Pin Name Value Function Value after
Reset
1:0 P0.16 0 0 GPIO Port 0.16 0
0 1 EINT0
3:2 P0.17 0 0 GPIO Port 0.17 0
1 0 SCK (SPI1)
5:4 P0.18 0 0 GPIO Port 0.18 0
1 0 MISO (SPI1)
7:6 P0.19 0 0 GPIO Port 0.19 0
1 0 MOSI (SPI1)
9:8 P0.20 0 0 GPIO Port 0.20 0
1 0 SSEL (SPI1)
1 1 EINT3


Reset
11:10 P0.21 0 0 GPIO Port 0.21 0
0 1 PWM5
1 0 Reserved
13:12 P0.22 0 0 GPIO Port 0.22 0
0 1 Reserved
15:14 P0.23 0 0 GPIO Port 0.23 0
0 1 RD2 (CAN controller 2)
1 0 Reserved
1 1 Reserved
17:16 P0.24 0 0 GPIO Port 0.24 0
0 1 TD2 (CAN controller 2)
1 0 Reserved
1 1 Reserved
19:18 P0.25 0 0 GPIO Port 0.25 0
0 1 RD1 (CAN controller 1)
1 0 Reserved
1 1 Reserved
21:20 P0.26 0 0 Reserved 0
0 1 Reserved
1 0 Reserved
1 1 Reserved
23:22 P0.27 0 0 GPIO Port 0.27 1
0 1 AIN0 (A/D input 0)
25:24 P0.28 0 0 GPIO Port 0.28 1
27:26 P0.29 0 0 GPIO Port 0.29 1
29:28 P0.30 0 0 GPIO Port 0.30 1
1 0 EINT3


Reset
31:30 P0.31 0 0 Reserved 0
0 1 Reserved
1 0 Reserved
1 1 Reserved

function is selected for a pin. For other functions direction is controlled automatically.
Settings other than those shown in the table are reserved, and should not be used.

PINSEL2 bits Description Reset value
1:0 Reserved -
2 When 0, pins P1.31:26 are GPIO pins. When 1, 0
P1.31:26 are used as Debug port.
3 When 0, pins P1.25:16 are used as GPIO pins. When 0
1, P1.25:16 are used as Trace port.
31:4 Reserved -
31:30
6.10 General purpose parallel I/O

Device pins that are not connected to a speciÞc peripheral function are controlled by
the GPIO registers. Pins may be dynamically conÞgured as inputs or outputs.
Separate registers allow setting or clearing any number of outputs simultaneously.
The value of the output register may be read back, as well as the current state of the
port pins.
6.10.1 Features
¥ Direction control of individual bits.

¥ Separate control of output set and clear.
¥ All I/O default to inputs after reset.
6.11 10-bit A/D converter

The LPC2119/LPC2129 each contain single 10-bit successive approximation analog
to digital converter with four multiplexed channels.
6.11.1 Features
¥ Measurement range of 0 V to 3 V.
¥ Capable of performing more than 400,000 10-bit samples per second.
¥ Burst conversion mode for single or multiple inputs.
¥ Optional conversion on transition on input pin or Timer Match signal.

6.12 CAN controllers and acceptance Þlter

The LPC2119/LPC2129 each contain two CAN controllers. The Controller Area network
(CAN) is a serial communications protocol which efficiently supports distributed real-time
control with a very high level of security. Its domain of application ranges from high speed
networks to low cost multiplex wiring.
6.12.1 Features
¥ Data rates up to 1 Mbit/s on each bus.

¥ 32-bit register and RAM access.
¥ Compatible with CAN speciÞcation 2.0B, ISO 11898-1.
¥ Global Acceptance Filter recognizes 11 and 29-bit Rx identiÞers for all CAN buses.
¥ Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard identiÞers.
6.13 UARTs
The LPC2119/LPC2129 each contain two UARTs. One UART provides a full modem
control handshake interface, the other provides only transmit and receive data lines.
6.13.1 Features
¥ 16 byte Receive and Transmit FIFOs.

¥ Register locations conform to Ô550 industry standard.
¥ Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
¥ Built-in baud rate generator.
¥ Standard modem interface signals included on UART1.
6.14 I2C serial I/O controller

I2C is a bi-directional bus for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address
and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter
with the capability to both receive and send information (such as memory).
Transmitters and/or receivers can operate in either master or slave mode, depending
on whether the chip has to initiate a data transfer or is only addressed. I2C is a
multi-master bus, it can be controlled by more than one bus master connected to it.
I2C implemented in LPC2119/LPC2129 supports bit rate up to 400 kbit/s (Fast I2C).
6.14.1 Features
¥ Standard I2C compliant bus interface.

¥ Easy to conÞgure as Master, Slave, or Master/Slave.
¥ Programmable clocks allow versatile rate control.
¥ Bidirectional data transfer between masters and slaves.
¥ Multi-master bus (no central master).

¥ Arbitration between simultaneously transmitting masters without corruption of

serial data on the bus.
¥ Serial clock synchronization allows devices with different bit rates to communicate
via one serial bus.
¥ Serial clock synchronization can be used as a handshake mechanism to suspend

and resume serial transfer.
¥ The I2C bus may be used for test and diagnostic purposes.
6.15 SPI serial I/O controller

The LPC2119/LPC2129 each contain two SPIs. The SPI is a full duplex serial
interface, designed to be able to handle multiple masters and slaves connected to a
given bus. Only a single master and a single slave can communicate on the interface
during a given data transfer. During a data transfer the master always sends a byte of
data to the slave, and the slave always sends a byte of data to the master.
6.15.1 Features
¥ Compliant with Serial Peripheral Interface (SPI) speciÞcation.

¥ Synchronous, Serial, Full Duplex, Communication.
¥ Combined SPI master and slave.
¥ Maximum data bit rate of one eighth of the input clock rate.
6.16 General purpose timers

The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally
generate interrupts or perform other actions at speciÞed timer values, based on four
match registers. It also includes four capture inputs to trap the timer value when an
input signal transitions, optionally generating an interrupt. Multiple pins can be
selected to perform a single capture or match function, providing an application with
ÔorÕ and ÔandÕ, as well as ÔbroadcastÕ functions among them.
6.16.1 Features
¥ A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

¥ Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an
interrupt.
¥ Four 32-bit match registers that allow:

—Continuous operation with optional interrupt generation on match.
—Stop timer on match with optional interrupt generation.
—Reset timer on match with optional interrupt generation.
¥ Four external outputs per timer corresponding to match registers, with the following
capabilities:
—Set LOW on match.

—Set HIGH on match.

—Toggle on match.
—Do nothing on match.
6.17 Watchdog timer

The purpose of the Watchdog is to reset the microcontroller within a reasonable
amount of time if it enters an erroneous state. When enabled, the Watchdog will
generate a system reset if the user program fails to ÔfeedÕ (or reload) the Watchdog
within a predetermined amount of time.
6.17.1 Features
¥ Internally resets chip if not periodically reloaded.

¥ Debug mode.
¥ Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to
be disabled.
¥ Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

¥ Flag to indicate Watchdog reset.
¥ Programmable 32-bit timer with internal pre-scaler.
¥ Selectable time period from (tpclk ´ 256 ´ 4) to (tpclk ´ 232 ´ 4) in multiples of
tpclk ´ 4.
6.18 Real time clock

The Real Time Clock (RTC) is designed to provide a set of counters to measure time
when normal or idle operating mode is selected. The RTC has been designed to use
little power, making it suitable for battery powered systems where the CPU is not
running continuously (Idle mode).
6.18.1 Features
¥ Measures the passage of time to maintain a calendar and clock.

¥ Ultra Low Power design to support battery powered systems.
¥ Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
¥ Programmable Reference Clock Divider allows adjustment of the RTC to match

various crystal frequencies.
6.19 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2119/LPC2129. The Timer is designed
to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or
perform other actions when speciÞed timer values occur, based on seven match
registers. The PWM function is also based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to
be used for more applications. For instance, multi-phase motor control typically
requires three non-overlapping PWM outputs with individual control of all three pulse
widths and positions.
Two match registers can be used to provide a single edge controlled PWM output.
One match register (MR0) controls the PWM cycle rate, by resetting the count upon
match. The other match register controls the PWM edge position. Additional single
edge controlled PWM outputs require only one match register each, since the
repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM
outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0
match occurs.
Three match registers can be used to provide a PWM output with both edges
controlled. Again, the MR0 match register controls the PWM cycle rate. The other
match registers control the two PWM edge positions. Additional double edge
controlled PWM outputs require only two match registers each, since the repetition
rate is the same for all PWM outputs.
With double edge controlled PWM outputs, speciÞc match registers control the rising
and falling edge of the output. This allows both positive going PWM pulses (when the
rising edge occurs prior to the falling edge), and negative going PWM pulses (when
the falling edge occurs prior to the rising edge).
6.19.1 Features
¥ Seven match registers allow up to six single edge controlled or three double edge
controlled PWM outputs, or a mix of both types.
¥ The match registers also allow:

—Continuous operation with optional interrupt generation on match.
—Stop timer on match with optional interrupt generation.
—Reset timer on match with optional interrupt generation.
¥ Supports single edge controlled and/or double edge controlled PWM outputs.
Single edge controlled PWM outputs all go HIGH at the beginning of each cycle
unless the output is a constant LOW. Double edge controlled PWM outputs can
have either edge occur at any position within a cycle. This allows for both positive
going and negative going pulses.
¥ Pulse period and width can be any number of timer counts. This allows complete
ßexibility in the trade-off between resolution and repetition rate. All PWM outputs
will occur at the same repetition rate.
¥ Double edge controlled PWM outputs can be programmed to be either positive

going or negative going pulses.
¥ Match register updates are synchronized with pulse outputs to prevent generation
of erroneous pulses. Software must ÔreleaseÕ new match values before they can
become effective.
¥ May be used as a standard timer if the PWM mode is not enabled.

¥ A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

6.20 System control

6.20.1 Crystal oscillator
The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator
output frequency is called fosc and the ARM processor clock frequency is referred to
as cclk for purposes of rate equations, etc. fosc and cclk are the same value unless
the PLL is running and connected. Refer to Section 6.20.2 ÒPLLÓ for additional
information.
6.20.2 PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The
input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current
Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in
practice, the multiplier value cannot be higher than 6 on this family of microcontrollers
due to the upper frequency limit of the CPU). The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO
within its frequency range while the PLL is providing the desired output frequency.
The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock.
Since the minimum output divider value is 2, it is insured that the PLL output has a
50 % duty cycle.The PLL is turned off and bypassed following a chip Reset and may
be enabled by software. The program must conÞgure and activate the PLL, wait for
the PLL to Lock, then connect to the PLL as a clock source. The PLL settling time is
100 m s.
6.20.3 Reset and wake-up timer

Reset has two sources on the LPC2119/LPC2129: the RESET pin and Watchdog
Reset. The RESET pin is a Schmitt trigger input pin with an additional glitch Þlter.
Assertion of chip Reset by any source starts the Wake-up Timer (see Wake-up Timer
description below), causing the internal chip reset to remain asserted until the
external Reset is de-asserted, the oscillator is running, a Þxed number of clocks have
passed, and the on-chip Flash controller has completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0,
which is the Reset vector. At that point, all of the processor and peripheral registers
have been initialized to predetermined values.
The wake-up timer ensures that the oscillator and other analog functions required for
chip operation are fully functional before the processor is allowed to execute
instructions. This is important at power on, all types of Reset, and whenever any of
the aforementioned functions are turned off for any reason. Since the oscillator and
other functions are turned off during Power-down mode, any wake-up of the
processor from Power-down mode makes use of the Wake-up Timer.
The Wake-up Timer monitors the crystal oscillator as the means of checking whether
it is safe to begin code execution. When power is applied to the chip, or some event
caused the chip to exit Power-down mode, some time is required for the oscillator to
produce a signal of sufÞcient amplitude to drive the clock logic. The amount of time
depends on many factors, including the rate of VDD ramp (in the case of power on),
the type of crystal and its electrical characteristics (if a quartz crystal is used), as well
as any other external circuitry (e.g. capacitors), and the characteristics of the
oscillator itself under the existing ambient conditions.

6.20.4 External interrupt inputs

The LPC2119/LPC2129 include up to nine edge or level sensitive External Interrupt
Inputs as selectable pin functions. When the pins are combined, external events can
be processed as four independent interrupt signals. The External Interrupt Inputs can
optionally be used to wake up the processor from Power-down mode.
6.20.5 Memory Mapping Control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x00000000. Vectors may be mapped to the bottom of the
on-chip Flash memory, or to the on-chip static RAM. This allows code running in
different memory spaces to have control of the interrupts.
6.20.6 Power Control

The LPC2119/LPC2129 support two reduced power modes: Idle mode and
Power-down mode. In Idle mode, execution of instructions is suspended until either a
Reset or interrupt occurs. Peripheral functions continue operation during Idle mode
and may generate interrupts to cause the processor to resume execution. Idle mode
eliminates power used by the processor itself, memory systems and related
controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal
clocks. The processor state and registers, peripheral registers, and internal SRAM
values are preserved throughout Power-down mode and the logic levels of chip
output pins remain static. The Power-down mode can be terminated and normal
operation resumed by either a Reset or certain speciÞc interrupts that are able to
function without clocks. Since all dynamic operation of the chip is suspended,
Power-down mode reduces chip power consumption to nearly zero.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.
6.20.7 VPB bus

The VPB divider determines the relationship between the processor clock (CCLK)
and the clock used by peripheral devices (PCLK). The VPB divider serves two
purposes. The Þrst is to provide peripherals with the desired PCLK via VPB bus so
that they can operate at the speed chosen for the ARM processor. In order to achieve
this, the VPB bus may be slowed down to 1¤ 2 to 1¤ 4 of the processor clock rate.
Because the VPB bus must work properly at power-up (and its timing cannot be
altered if it does not work since the VPB divider control registers reside on the VPB
bus), the default condition at reset is for the VPB bus to run at 1¤ 4 of the processor
clock rate. The second purpose of the VPB divider is to allow power savings when an
application does not require any peripherals to run at the full processor rate. Because
the VPB divider is connected to the PLL output, the PLL remains active (if it was
running) during Idle mode.
6.21 Emulation and debugging

The LPC2119/LPC2129 support emulation and debugging via a JTAG serial port. A
trace port allows tracing program execution. Debugging and trace functions are
multiplexed only with GPIOs on Port 1. This means that all communication, timer and

interface peripherals residing on Port 0 are available during the development and
debugging phase as they are when the application is run in the embedded system
itself.
6.21.1 Embedded ICE

Standard ARM EmbeddedICE¤ logic provides on-chip debug support. The debugging
of the target system requires a host computer running the debugger software and an
EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the
Remote Debug Protocol commands to the JTAG data needed to access the ARM
core.
The ARM core has a Debug Communication Channel function built-in. The debug
communication channel allows a program running on the target to communicate with
the host debugger or another separate host without stopping the program ßow or
even entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving
data without affecting the normal program ßow. The debug communication channel
data and control registers are mapped in to addresses in the EmbeddedICE logic.
6.21.2 Embedded trace
Since the LPC2119/LPC2129 have signiÞcant amounts of on-chip memory, it is not

possible to determine how the processor core is operating simply by observing the
external pins. The Embedded Trace Macrocell“ provides real-time trace capability for
deeply embedded processor cores. It outputs information about processor execution
to the trace port.
The ETM is connected directly to the ARM core and not to the main AMBA system
bus. It compresses the trace information and exports it through a narrow trace port.
An external trace port analyzer must capture the trace information under software
debugger control. Instruction trace (or PC trace) shows the ßow of execution of the
processor and provides a list of all the instructions that were executed. Instruction
trace is signiÞcantly compressed by only broadcasting branch addresses as well as a
set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace
information generation can be controlled by selecting the trigger resource. Trigger
resources include address comparators, counters and sequencers. Since trace
information is compressed the software debugger requires a static image of the code
being executed. Self-modifying code can not be traced because of this restriction.
6.21.3 RealMonitor“
RealMonitor is a conÞgurable software module, developed by ARM Inc., which
enables real time debug. It is a lightweight debug monitor that runs in the background
while users debug their foreground application. It communicates with the host using
the DCC (Debug Communications Channel), which is present in the EmbeddedICE
logic. The LPC2119/LPC2129 contain a speciÞc conÞguration of RealMonitor
software programmed into the on-chip Flash memory.

7. Limiting values
Table 9: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter Conditions Min Max Unit
V18 Supply voltage, internal rail - 0.5 +2.5 V
V3 Supply voltage, external rail - 0.5 +3.6 V
V3A Analog 3.3 V pad supply voltage - 0.5 4.6 V
AVIN Analog input voltage on A/D related - 0.5 5.1 V
pins
Vi DC input voltage, 5 V tolerant I/O - 0.5 6.0 V
pins[2][3]
Vi DC input voltage, other I/O pins[2][4] - 0.5 V3 + 0.5 V
I DC supply current per supply pin[5] - 100 mA
I DC ground current per ground pin[5] - 100 mA
Tstg Storage temperature[6] - 65 150 °C
P Power dissipation (based on 1.5 - W
package heat transfer, not device
power consumption)
[1] The following applies to the Limiting values:

a) Stresses above those listed under Limiting values may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any conditions other
than those described in Section 8 ÒStatic characteristicsÓ and Section 9 ÒDynamic characteristicsÓ
of this speciÞcation is not implied.
b) This product includes circuitry speciÞcally designed for the protection of its internal devices from
the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional
precautions be taken to avoid applying greater than the rated maximum.
c) Parameters are valid over operating temperature range unless otherwise speciÞed. All voltages
are with respect to VSS unless otherwise noted.
[2] Including voltage on outputs in 3-state mode.
[3] Only valid when the V3 supply voltage is present.
[4] Not to exceed 4.6 V.
[5] The peak current is limited to 25 times the corresponding maximum current.
[6] Dependent on package type.

8. Static characteristics
Table 10: Static characteristics
Tamb = - 40 °C to +85 °C for commercial, unless otherwise speciÞed.
Symbol Parameter Conditions Min Typ[1] Max Unit
V18 Supply voltage 1.65 1.8 1.95 V
V3 External rail supply voltage 3.0 3.3 3.6 V
V3A Analog 3.3 V pad supply 2.5 3.3 3.6 V
voltage
Standard Port pins, RESET, RTCK
IIL Low level input current, no Vi = 0 - - 3 m A
pull-up
IIH High level input current, no Vi = V3 - - 3 m A
pull down
IOZ 3-state output leakage, no Vo = 0, Vo = V3 - - 3 m A
pull-up/down
Ilatchup I/O latch-up current - (0.5 V3) < V < (1.5 V3) 100 - - mA
Tj < 125 °C
Vi Input voltage[2][3][4] 0 - 5.5 V
Vo Output voltage, output active 0 - V3 V
VIH High level input voltage 2.0 - - V
VIL Low level input voltage - - 0.8 V
Vhys Hysteresis voltage - 0.4 - V
VOH High level output voltage[5] IOH = - 4 mA V3 - 0.4 - - V
VOL Low level output voltage[5] IOL = - 4 mA - - 0.4 V
IOH High level output current[5] VOH = V3 - 0.4 V - 4 - - mA
IOL Low level output current[5] VOL = 0.4 V 4 - - mA
IOH High level short circuit VOH = 0 - - - 45 mA
current[6]
IOL Low level short circuit VOL = V3 - - 50 mA
current[6]
IPD Pull-down current Vi = 5 V[7] 10 50 150 m A
IPU Pull-up current (applies to Vi = 0 - 15 - 50 - 85 m A
P1.16 - P1.25) V3 < Vi< 5 V[7] 0 0 0 m A
I18 Active Mode V18 = 1.8 V, cclk = 60 MHz, - 60 - mA
Tamb = 25 °C, code
while(1){}
executed from FLASH, no active
peripherals
Power-down Mode V18 = 1.8 V, Tamb = +25 °C, - 10 - m A
V18 = 1.8 V, Tamb = +85 °C - 110 500 m A
I2C pins
VIH High level input voltage VTOL is from 4.5 V to 5.5 V 0.7VTOL - - V
VIL Low level input voltage VTOL is from 4.5 V to 5.5 V - - 0.3VTOL V
Vhys Hysteresis voltage VTOL is from 4.5 V to 5.5 V - 0.5VTOL - V

Table 10: Static characteristicsÉcontinued

Tamb = - 40 °C to +85 °C for commercial, unless otherwise speciÞed.
VOL Low level output voltage[5] IOL = 3 mA - - 0.4 V
Ilkg Input leakage to VSS Vi = V3 - 2 4 m A
Vi = 5 V - 10 22 m A
Oscillator pins
X1 input Voltages 0 - V18
X2 output Voltages 0 - V18
On-chip Flash program memory
endurance (write and erase) 100,000 - - cycles
data retention 20 - - years
[1] Typical ratings are not guaranteed. The values listed are at room temperature (+25 ßC), nominal supply voltages. Pin capacitance is
characterized but not tested.
[2] Including voltage on outputs in 3-state mode.
[3] V3 supply voltages must be present.
[4] 3-state outputs go into 3-state mode when V3 is grounded.
[5] Accounts for 100 mV voltage drop in all supply lines.
[6] Only allowed for a short time period.
[7] Minimum condition for Vi = 4.5 V, maximum condition for Vi = 5.5 V.
Table 11: A/D converter DC electrical characteristics

V3A = 2.5 V to 3.6 V unless otherwise speciÞed; T amb = - 40 °C to +85 °C unless otherwise speciÞed; A/D converter frequency
4.5 MHz.
Symbol Parameter Min Max Unit
AVIN Analog input voltage 0 V3A V
CIN Analog input capacitance - 1 pF
DLe Differential non-linearity[1][2][3] - ±1 LSB
ILe Integral non-linearity[1][4] - ±2 LSB
OSe Offset error[1][5] - ±3 LSB
Ge Gain error[1][6] - ±0.5 %
Ae Absolute error[1][7] - ±4 LSB
[1] Conditions: VSSA = 0 V, V3A = 3.3 V.

[2] The A/D is monotonic, there are no missing codes.
[3] The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. See Figure 4.
[4] The integral no-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 4.
[5] The offset error (OSe) is the absolute difference between the straight line which Þts the actual curve and the straight line which Þts the
ideal curve. See Figure 4.
[6] The gain error (Ge) is the relative difference in percent between the straight line Þtting the actual transfer curve after r emoving offset
error, and the straight line which Þts the ideal transfer curve. See Figure 4.
[7] The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the
non-calibrated A/D and the ideal transfer curve. See Figure 4.

offset gain
error error
EO EG
1023
1022
1021
1020
1019
1018
(2)
7
code (1)
out
6
(5)
4
(4)
3
(3)
2
1 1 LSB
(ideal)
0
1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024
VIA (LSBideal)
VDDA - VSSA
offset 1 LSB =
error 1024
EO 002aaa668
(1) Example of an actual transfer curve.

(2) The ideal transfer curve.
(3) Differential non-linearity (DLe).
(4) Integral non-linearity (ILe).
(5) Center of a step of the actual transfer curve.
Fig 4. A/D conversion characteristics.

9. Dynamic characteristics
Table 12: Characteristics
Tamb = 0 °C to +70 °C for commercial, - 40 °C to +85 °C for industrial, V18, V3 over speciÞed ranges [1]

External Clock
fosc Oscillator frequency supplied by an 1 - 50 MHz
external oscillator (signal generator)
External clock frequency supplied by 1 - 30 MHz
an external crystal oscillator
External clock frequency if on-chip 10 - 25 MHz
PLL is used
External clock frequency if ISP is 10 - 25 MHz
used for initial code download
tC Oscillator clock period 20 - 1000 ns
tCHCX Clock HIGH time tc ´ 0.4 - - ns
tCLCX Clock LOW time tc ´ 0.4 - - ns
tCLCH Clock rise time - - 5 ns
tCHCL Clock fall time - - 5 ns
Port Pins
tRISE Port output rise time (except P0.2, - 10 - ns
P0.3)
tFALL Port output fall time (except P0.2, - 10 - ns
P0.3)
I2C pins
tf Output fall time from VIH to VIL 20 + - - ns
0.1 ´ Cb[2]
[1] Parameters are valid over operating temperature range unless otherwise speciÞed.
[2] Bus capacitance Cb in pF, from 10 pF to 400 pF.

9.1 Timing
VDD - 0.5 V
0.2 VDD + 0.9
0.45 V 0.2 VDD - 0.1 V

tCHCX
tCHCL tCLCX tCLCH

tC
002aaa416
Fig 5. External clock timing.

10. Package outline

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2
c
y
48 33
49 32 ZE
e
E HE A
A2
(A 3)
A1
wM
∉
bp Lp
pin 1 index L
64 17
1 16 detail X
ZD v M A
e wM
bp
D B
HD v M B
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y Z D (1) Z E (1) ∉
max.
mm 1.6 0.20 1.45 0.27 0.18 10.1 10.1 12.15 12.15 0.75 1.45 1.45 7o
0.25 0.5 1 0.2 0.12 0.1 o
0.05 1.35 0.17 0.12 9.9 9.9 11.85 11.85 0.45 1.05 1.05 0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
00-01-19
SOT314-2 136E10 MS-026
03-02-25
Fig 6. SOT314-2 (LQFP64).

11. Revision history
Table 13: Revision history

Rev Date CPCN Description
03 20041222 - Product data (9397 750 13146)
ModiÞcations:
¥ Section 6.2 ÒOn-Chip Flash program memoryÓ on page 9 ; updated text.
¥ Section 6.20.2 ÒPLLÓ on page 22 ; updated text.
¥ Section 6.20.7 ÒVPB busÓ on page 23 ; updated text.
¥ Table 9 ÒLimiting valuesÓ on page 25 ; updated text.
¥ Table 10 ÒStatic characteristicsÓ on page 26 ; added On-chip Flash program memory
specs.
02 20040202 - Preliminary data (9397 750 12806)
01 20031118 - Preliminary data (9397 750 12328)

12. Data sheet status
Level Data sheet status[1] Product status[2][3] DeÞnition

I Objective data Development This data sheet contains data from the objective speciÞcation for product development. Philips
Semiconductors reserves the right to change the speciÞcation in any manner without notice.
II Preliminary data QualiÞcation This data sheet contains data from the preliminary speciÞcation. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the speciÞcation without notice, in
order to improve the design and supply the best possible product.
III Product data Production This data sheet contains data from the product speciÞcation. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change NotiÞcation (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
13. DeÞnitions performance. When the product is in full production (status ÔProductionÕ),
relevant changes will be communicated via a Customer Product/Process
Change NotiÞcation (CPCN). Philips Semiconductors assumes no
Short-form speciÞcation Ñ The data in a short-form speciÞcation is responsibility or liability for the use of any of these products, conveys no
extracted from a full data sheet with the same type number and title. For licence or title under any patent, copyright, or mask work right to these
detailed information see the relevant data sheet or data handbook. products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
Limiting values deÞnition Ñ Limiting values given are in accordance with speciÞed.
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
15. Licenses
speciÞcation is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Purchase of Philips I2C components
Application information Ñ Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors Purchase of Philips I2C components conveys a license
make no representation or warranty that such applications will be suitable for under the PhilipsÕ I 2C patent to use the components in the
the speciÞed use without further testing or modiÞcation. I2C system provided the system conforms to the I2C
speciÞcation deÞned by Philips. This speciÞcation can be
ordered using the code 9398 393 40011.
14. Disclaimers
Life support Ñ These products are not designed for use in life support
16. Trademarks
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors ARM Ñ is a registered trademark of ARM, Inc.
customers using or selling these products for use in such applications do so ARM7TDMI-S Ñ is a trademark of ARM, Inc.
at their own risk and agree to fully indemnify Philips Semiconductors for any EmbeddedICE Ñ is a registered trademark of ARM, Inc.
damages resulting from such application. Embedded Trace Macrocell Ñ is a trademark of ARM, Inc.
Right to make changes Ñ Philips Semiconductors reserves the right to RealMonitor Ñ is a trademark of ARM, Inc.
make changes in the products - including circuits, standard cells, and/or SPI Ñ is a trademark of Motorola, Inc.
software - described or contained herein in order to improve design and/or Thumb Ñ is a registered trademark of ARM, Inc.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales ofÞce addresses, send e-mail to: [email protected]. Fax: +31 40 27 24825

Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 6.20.6 Power Control. . . . . . . . . . . . . . . . . . . . . . . . . 23
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6.20.7 VPB bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6.21 Emulation and debugging. . . . . . . . . . . . . . . . 23
6.21.1 Embedded ICE. . . . . . . . . . . . . . . . . . . . . . . . 24
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
6.21.2 Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 24
3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
6.21.3 RealMonitor“ . . . . . . . . . . . . . . . . . . . . . . . . 24
4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 25
5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
8 Static characteristics . . . . . . . . . . . . . . . . . . . 26
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Dynamic characteristics . . . . . . . . . . . . . . . . . 29
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
9.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6 Functional description . . . . . . . . . . . . . . . . . . . 9
10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1 Architectural overview. . . . . . . . . . . . . . . . . . . . 9
6.2 On-Chip Flash program memory . . . . . . . . . . . 9 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . 32
6.3 On-Chip static RAM . . . . . . . . . . . . . . . . . . . . 10 12 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 33
6.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 10 13 DeÞnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 11 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.1 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 12
15 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 13
6.7 Pin function select register 0 (PINSEL0 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
- 0xE002C000). . . . . . . . . . . . . . . . . . . . . . . . 13
6.8 Pin function select register 1 (PINSEL1
- 0xE002C004). . . . . . . . . . . . . . . . . . . . . . . . 15
6.9 Pin function select register 2 (PINSEL2
- 0xE002C014). . . . . . . . . . . . . . . . . . . . . . . . 17
6.10 General purpose parallel I/O. . . . . . . . . . . . . . 17
6.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.11 10-bit A/D converter . . . . . . . . . . . . . . . . . . . . 17
6.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.12 CAN controllers and acceptance Þlter . . . . . . 18
6.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.13 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.14 I2C serial I/O controller . . . . . . . . . . . . . . . . . . 18
6.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.15 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 19
6.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.16 General purpose timers . . . . . . . . . . . . . . . . . 19
6.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.17 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 20
6.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.18 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . 20
6.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.19 Pulse width modulator . . . . . . . . . . . . . . . . . . 20
6.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.20 System control . . . . . . . . . . . . . . . . . . . . . . . . 22
6.20.1 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 22
6.20.2 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.20.3 Reset and wake-up timer . . . . . . . . . . . . . . . . 22
6.20.4 External interrupt inputs . . . . . . . . . . . . . . . . . 23
6.20.5 Memory Mapping Control . . . . . . . . . . . . . . . . 23
' Koninklijke Philips Electronics N.V. 2004.

Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 22 December 2004 Document order number: 9397 750 13146

LPC2129 Datasheet

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LPC2119/LPC2129

Single-chip 16/32-bit microcontrollers; 128/256 kB ISP/IAP

2.1 Key features

n Up to forty-six 5 V tolerant general purpose I/O pins. Up to nine edge or level

3.1 Ordering options

Product data Rev. 03 Ñ 22 December 2004 2 of 34

ARM7 LOCAL BUS AMBA AHB

INTERNAL SRAM INTERNAL

16 kB AHB TO VPB VPB

Ain3:0* 10-BIT WATCHDOG

*Shared with GPIO 002aaa662

Product data Rev. 03 Ñ 22 December 2004 3 of 34

Product data Rev. 03 Ñ 22 December 2004 4 of 34

5.2 Pin description

Product data Rev. 03 Ñ 22 December 2004 5 of 34

Table 3: Pin descriptionÉcontinued

Product data Rev. 03 Ñ 22 December 2004 6 of 34

Table 3: Pin descriptionÉcontinued

Product data Rev. 03 Ñ 22 December 2004 7 of 34

Table 3: Pin descriptionÉcontinued

Product data Rev. 03 Ñ 22 December 2004 8 of 34

6.1 Architectural overview

The ARM7TDMI-S processor also employs a unique architectural strategy known as

¥ The standard 32-bit ARM set.

6.2 On-Chip Flash program memory

The LPC2119/LPC2129 Flash memory provides a minimum of 100,000 erase/write

Product data Rev. 03 Ñ 22 December 2004 9 of 34

6.3 On-Chip static RAM

6.4 Memory map

Product data Rev. 03 Ñ 22 December 2004 10 of 34

4.0 GB 0xFFFF FFFF

3.0 GB 0xC000 0000

RESERVED ADDRESS SPACE

RESERVED ADDRESS SPACE

RESERVED ADDRESS SPACE

Fig 3. LPC2119/LPC2129 memory map.

6.5 Interrupt controller

Product data Rev. 03 Ñ 22 December 2004 11 of 34

Non-vectored IRQs have the lowest priority.

6.5.1 Interrupt sources

Table 4: Interrupt sources

Product data Rev. 03 Ñ 22 December 2004 12 of 34

Table 4: Interrupt sourcesÉcontinued

6.6 Pin connect block

The Pin Control Module contains three registers as shown in Table 5.

6.7 Pin function select register 0 (PINSEL0 - 0xE002C000)

Table 6: Pin function select register 0 (PINSEL0 - 0xE002C000)

Product data Rev. 03 Ñ 22 December 2004 13 of 34

Table 6: Pin function select register 0 (PINSEL0 - 0xE002C000)Écontinued

Product data Rev. 03 Ñ 22 December 2004 14 of 34

Table 6: Pin function select register 0 (PINSEL0 - 0xE002C000)Écontinued

6.8 Pin function select register 1 (PINSEL1 - 0xE002C004)

Table 7: Pin function select register 1 (PINSEL1 - 0xE002C004)

Product data Rev. 03 Ñ 22 December 2004 15 of 34

Table 7: Pin function select register 1 (PINSEL1 - 0xE002C004)Écontinued

Product data Rev. 03 Ñ 22 December 2004 16 of 34

Table 7: Pin function select register 1 (PINSEL1 - 0xE002C004)Écontinued

6.9 Pin function select register 2 (PINSEL2 - 0xE002C014)

Table 8: Pin function select register 2 (PINSEL2 - 0xE002C014)

6.10 General purpose parallel I/O