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Razavi Practice

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272 views4 pages

Razavi Practice

Uploaded by

Shreyas Yewale
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Design Of Analog CMOS Integrated Circuits.

Chapter 3

Unless otherwise stated, in the following problems, use the device data shown in Table 2.1 and
assume that VDD = 3 V where necessary. All device dimensions are e ective values and in
microns.

3.1. For the circuit of Fig. 3.13, calculate the small-signal voltage gain if (W/L)1 = 50/0.5, (W/L)2
= 10/0.5, and ID1 = ID2 = 0.5 mA. What is the gain if M2 is implemented as a diode-connected
PMOS device (Fig. 3.16)?
3.2. In the circuit of Fig. 3.18, assume that (W/L)1 = 50/0.5, (W/L)2 = 50/2, and ID1 = ID2 = 0.5
mA when both devices are in saturation. Recall that λ ∝ 1/L.

(a) Calculate the small-signal voltage gain.

(b) Calculate the maximum output voltage swing while both devices are saturated.

Fig:3.18 Fig: 3.4(a)

3.3. In the circuit of Fig. 3.4(a), assume that (W/L)1 = 50/0.5, RD = 2 k, and λ = 0.

(a) What is the small-signal gain if M1 is in saturation and ID = 1 mA?

(b) What input voltage places M1 at the edge of the triode region? What is the small-signal gain
under this condition?

(c) What input voltage drives M1 into the triode region by 50 mV? What is the small-signal gain
under this condition?

3.4. Suppose the common-source stage of Fig. 3.4(a) is to provide an output swing from 1 V to
2.5 V. Assume that (W/L)1 = 50/0.5, RD = 2 k, and λ = 0.

(a) Calculate the input voltages that yield Vout = 1 V and Vout = 2.5 V.

(b) Calculate the drain current and the transconductance of M1 for both cases.

(c) How much does the small-signal gain, gm RD, vary as the output goes from 1 V to 2.5 V?
(Variation of small-signal gain can be viewed as nonlinearity.)
3.5. Calculate the intrinsic gain of an NMOS device and a PMOS device operating in saturation
with W/L = 50/0.5 and |ID| = 0.5 mA. Repeat these calculations if W/L = 100/1

3.6. Assuming a constant L, plot the intrinsic gain of a saturated device versus the gate-source
voltage if (a) the drain current is constant, (b) W is constant.

3.7. Assuming a constant L, plot the intrinsic gain of a saturated device versus W/L if (a) the
gate-source voltage is constant, (b) the drain current is constant.

3.8. An NMOS transistor with W/L = 50/0.5 is biased with VG = +1.2 V and VS = 0. The drain
voltage is varied from 0 to 3 V.

(a) Assuming the bulk voltage is zero, plot the intrinsic gain versus VDS.

(b) Repeat part (a) for a bulk voltage of −1 V.

3.9. For an NMOS device operating in saturation, plot gm, rO, and gmrO as the bulk voltage goes
from 0 to −∞ while other terminal voltages remain constant.

3.10. Consider the circuit of Fig. 3.13 with (W/L)1 = 50/0.5 and (W/L)2 = 10/0.5. Assume that λ =
γ = 0.
(a) At what input voltage is M1 at the edge of the triode region? What is the small-signal gain
under this condition?

(b) What input voltage drives M1 into the triode region by 50 mV? What is the small-signal gain
under this condition?

3.11. Repeat Problem 3.10 if the body e ect is not neglected.

3.12. In the circuit of Fig. 3.17, (W/L)1 = 20/0.5, I1 = 1 mA, and IS = 0.75 mA. Assuming λ = 0,
calculate (W/L)2 such that M1 is at the edge of the triode region. What is the small-signal
voltage gain under this condition?
3.13. Plot the small-signal gain of the circuit shown in Fig. 3.17 as Is goes from 0 to (0.75)I1.
Assume that M1 is always saturated, and neglect channel-length modulation and body e ect.

3.14. The circuit of Fig. 3.18 is designed to provide an output voltage swing of 2.2 V with a bias
current of 1 mA and a small-signal voltage gain of 100. Calculate the dimensions of M1 and M2.

Fig: 3.18

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