PN Simulation

Download as pdf or txt
Download as pdf or txt
You are on page 1of 7

1.

Simulation of PN Junction using Silvaco Atlas


Name: Sodisetty Rahul Koushik
Roll Number: 23EC10097

Assignments:
1. Plot the I-V characteristics of the forward-biased PN Junction diode in log
scale and explain the reason behind such behaviour.

Description:
This is the plot of Anode Current vs. Anode Voltage(V) for a silicon p-n junction
diode Junction Transistor. Here, we have the anode current being related to the
anode voltage as follows:

ID = IS(e(VF/VT) - 1)
Where ID = Diode Current/Anode Current
IS = Reverse Saturation Current
VF = Anode Voltage
VT = Thermal Voltage(~26mV)
Observations and Conclusions:
As observed in the plot, there is an exponential relation between the anode
current and anode voltage which has been represented in the log scale in the
plot. For a PN Junction Diode, according to the equation given above, the
current increases exponentially as the forward bias voltage increases. Once, the
forward bias voltage increases beyond the cut-in voltage of silicon, 0.7V, then
the increase becomes drastic and continues in the same pattern.
2. Change the doping concentration of the p-type region to 1017 cm-3 and the
n-type region to 1016 cm-3. Plot band diagram for these doping
concentrations. Also, mark the depletion regions (both n and p sides) and
show built-in potential in the band diagram. Verify the obtained values of
depletion region widths and built-in potential with theoretically obtained
results (ni= 1.5⨯1010 cm-3)
For the given doping concentration, where p > n theoretically the depletion
width is inversely proportional to the doping concentrations. Hence,
NA/ND = WN/WP
Where NA = Acceptor Doping Concentration (p-type)
ND = Donor Doping Concentration (n-type)
WN = Width of Depletion Layer on the n-side
WP = Width of Depletion layer on the p-side
Therefore, the width of the depletion region on the n-side would be 10 times
the p-side width.
The Built-In Potential value can be obtained from the graph itself as the range
of the conduction band energy. That is the difference between the maximum
and minimum values of the conduction band energies which is:
VO = 0.855 – 0.1V = 0.755V
Theoretically,

VO = VT * ln(NA*ND/ni2)
Where ni = 1.5⨯1010 cm-3
So, we have VO = 26mV * ln(1017 x 1016/(1.5 x 1010)2)
Vo = 757.18mV
Conclusions:
Graphical Value of Built-in Voltage: 0.755V
Theoretical Value of Built-in Voltage: 0.757V
3. Plot the band diagram of the diode at -0.2 V, 0.4 V and 0.9 V and check
whether any difference is observed in the structures. If yes, then explain the
reason behind that.

Applied Biasing = -0.2V

Applied Biasing = 0.4V


Applied Biasing = 0.9V
Explanation for variation:
1. Reverse Bias (-0.2V):
• It increases the depletion region width.
• The band diagram is similar to the equilibrium diagram as the current
flow has not started in the diode across the p-n junction.
• However, the built-in potential increases as the reverse-bias voltage adds
up to it increasing the potential barrier.
2. Forward Bias (0.4V):
• It decreases the depletion region width.
• It allows significant current flow by the majority carriers and hence a
large fraction of the electrons are in the conduction band moving the
fermi level closer to the conduction band and valence band farther.
• Also, the built-in potential is seen to reduce as the forward-bias voltage
is opposite to the built-in potential, decreasing the built-in voltage.
3. High Forward Bias (0.9V):
• This bias further decreases the depletion region width.
• It allows maximum current flow by the majority carriers and hence
almost all of the electrons are in the conduction band moving the fermi
level closer to the conduction band and valence band even farther.
• Also, the built-in potential almost flattens as the forward-bias voltage
crosses the built-in potential, making it almost zero.

4. Plot the electric field at the junction for the p-n junction diode and explain
why such behaviour is observed. Also, calculate the built-in potential from
the electric field profile.

This graph shows the electric field developed in a p-n junction diode due to the
accumulation of charges at the p-type and n-type junctions. The peak electric
field value at the junction is approximately 45,000 V/cm. This variation is
because, at the anode, there is a high potential and hence a high electric field.
Then until we reach the junction there is no variation in the electric field as the
charge polarity remains the same. Then the electric field spikes up at the
junction due to the oppositely charged ions. Then it decreases and remains
constant until we reach the cathode as there is no change in the charge
polarity. Finally, it increases at the cathode due to the applied potential.
Built-in Potential Calculation:

By integrating the area under the graph, we can determine the built-in
potential across the junction. As shown in the graph, the peak electric field at
the junction is around 45,000 V/cm. The area under the graph, which
represents the built-in potential of the diode, is calculated to be 0.771164V.
Thus, the built-in potential of the diode obtained from the electric field profile
is 0.771V.

You might also like