International Journal of Electronics and Electical Engineering

Volume 2 Issue 4 Article 1

April 2014

DESIGN OF AN ERROR DETECTION AND DATA RECOVERY

ARCHITECTURE FOR MOTION ESTIMATION TESTING
APPLICATIONS
V. SWARNALATHA
VLSI System Design A.I.T.S, Rajampet Kadapa (Dt), A.P., India, [email protected]

K. SRINIVASA RAO
Dept of E.C.E, A.I.T.S, Rajampet Kadapa (Dt), A.P., India, [email protected]

Follow this and additional works at: https://www.interscience.in/ijeee

Part of the Power and Energy Commons

Recommended Citation
SWARNALATHA, V. and RAO, K. SRINIVASA (2014) "DESIGN OF AN ERROR DETECTION AND DATA
RECOVERY ARCHITECTURE FOR MOTION ESTIMATION TESTING APPLICATIONS," International Journal
of Electronics and Electical Engineering: Vol. 2 : Iss. 4 , Article 1.
DOI: 10.47893/IJEEE.2014.1103
Available at: https://www.interscience.in/ijeee/vol2/iss4/1

This Article is brought to you for free and open access by the Interscience Journals at Interscience Research
Network. It has been accepted for inclusion in International Journal of Electronics and Electical Engineering by an
authorized editor of Interscience Research Network. For more information, please contact
[email protected].
 DESIGN OF AN ERROR DETECTION AND DATA RECOVERY
ARCHITECTURE FOR MOTION ESTIMATION TESTING
APPLICATIONS
V. SWARNA LATHA1 & K. SRINIVASA RAO2
1
VLSI System Design A.I.T.S, Rajampet Kadapa (Dt), A.P., India &
2
Dept of E.C.E, A.I.T.S, Rajampet Kadapa (Dt), A.P., India
E-mail : [email protected] & [email protected]

Abstract - Motion estimation (ME) in a video coding system is the critical role, so testing such a module is of priority
concern. While focusing on the testing of ME in a video coding system, this work presents an error detection and data
recovery (EDDR) design based on residue -and- quotient (RQ) code. An error in processing elements (PEs) can be detected
and recovered effectively by using the proposed EDDR design. Importantly, the proposed EDDR design performs
satisfactorily in terms of throughput and reliability for motion estimation (ME) testing applications.

Keywords: Motion Estimation, Processing elements, TCG, RQ code, EDC

exploring the feasibility of an embedded testing

I. INTRODUCTION approach to detect errors and recover data of a ME is
of worthwhile interest. Additionally, the reliability
Advances in semiconductors, digital signal issue of numerous processing elements (PEs) in a ME
processing, and communication technologies have can be improved by enhancing the capabilities of
made multimedia applications more flexible and concurrent error detection (CED). The CED approach
reliable. can detect errors through conflicting and undesired
A good example is the H.264 video standard, results generated from operations on the same
also known as MPEG-4 Part 10 Advanced Video operands. CED can also test the circuit at full
Coding, which is widely regarded as the next operating speed without interrupting a system. Thus,
generation video compression standard Video based on the CED concept, this work develops an
compression is necessary in a wide range of EDDR architecture based on the RQ code to detect
applications to reduce the total data amount required errors and recovery data in PEs of a ME.
for transmitting or storing video data. This paper is organized as follows. Section 2
Among the coding systems, a ME in a video gives the circuit design of RQ code generator. Section
coder is the critical role so testing such a module is of 3 introduces the EDDR architecture and test method.
priority concern. Additionally, the visual quality and Conclusions are offered in section 4.
peak signal-to-noise ratio (PSNR) at a given bit rate
are influenced if an error occurred in ME process. II. RQ CODE GENERATION
In the advance of VLSI technologies facilitate
the integration of a large number of PEs of a ME into Coding approaches such as parity code, Berger
a chip; the logic-per-pin ratio is subsequently code, and residue code have been considered for
increased, thus decreasing significantly the efficiency design applications to detect circuit errors. Residue
of logic testing on the chip. code is generally separable arithmetic codes by
As a commercial chip, it is absolutely necessary estimating a residue for data and appending it to data.
for the ME to introduce design for testability (DFT) Error detection logic for operations is typically
.DFT focuses on increasing the ease of device testing, derived by a separate residue code, making the
thus guaranteeing high reliability of a system. DFT detection logic is simple and easily implemented.
methods rely on reconfiguration of a circuit under test Error detection logic for operations is typically
(CUT) to improve testability. While DFT approaches derived using a separate residue code such that
enhance the testability of circuits, advances in sub- detection logic is simply and easily implemented.
micron technology and resulting increases in the However, only a bit error can be detected based on
complexity of electronic circuits and systems have the residue code. Additionally, an error can’t be
meant that built-in self-test (BIST) schemes have recovered effectively by using the residue codes.
rapidly become necessary in the digital world. Therefore, this work presents a quotient code, which
BIST schemes not only detect faults but also is derived from the residue code, to assist the residue
specify their location for error correcting. BIST can code in detecting multiple errors and recovering
generate test simulation and test responses without errors. the corresponding circuit design of the RQCG
outside support. The extended BIST schemes is easily realized by using the simple adders (ADDs).
generally focus on memory circuit; testing-related Namely, the RQ code can be generated with a low
issues of video coding have been addressed. Thus, complexity and little hardware cost. . The

International Journal of Electrical and Electronics Engineering (IJEEE) ISSN (PRINT): 2231 –5284, Vol-2, Issue-4

225
 Design of An Error Detection And Data Recovery Architecture For Motion Estimation Testing Applications

mathematical model of RQ code is simply described generated with a low complexity and little hardware
as follows. Assume that binary data X is expressed as cost.

III. EDDR ARCHITECTURE

The RQ code of X modulo m expressed as

R=|X|m Q=[X/m], respectively. Notably [i] denotes
the largest integer not exceeding i.
According to the above RQ code expression, the
corresponding circuit design of the RQCG can be
realized. In order to simplify the complexity of circuit
design, the implementation of the module is generally
dependent on the addition operation. Additionally,
based on the concept of residue code, the following
definitions shown can be applied to generate the RQ Fig. 1. Conceptual view of the EDDR Architecture
code for circuit design.
Definition 1: Fig. 1 shows the conceptual view of the proposed
|N1+N2|m = ||N1|m + |N2|m|m. (2) EDDR scheme, which comprises two major circuit
Definition 2: Let Nj = n1+n2+…+|nj, then designs, i.e. error detection circuit (EDC) and data
|Nj|m = ||n1|m + |n2|m…+|nj|m|m. (3 ) recovery circuit (DRC), to detect errors and recover
To accelerate the circuit design of RQCG, the binary the corresponding data in a specific CUT. The test
data shown in (1) can generally be divided into two code generator (TCG) in Fig. 1 utilizes the concepts
parts: of RQ code to generate the corresponding test codes
for error detection and data recovery. In other words,
the test codes from TCG and the primary output from
CUT are delivered to EDC to determine whether the
CUT has errors. DRC is in charge of recovering data
from TCG. Additionally, a selector is enabled to
export error-free data or data-recovery results.
Importantly, an array-based computing structure,
such as ME, discrete cosine transform (DCT),
iterative logic array (ILA), and finite impulse filter
(FIR), is feasible for the proposed EDDR scheme to
Significantly, the value of k is equal to[n/2] and detect errors and recover the corresponding data.
the data formation of Y0 and Y1 are a decimal This work adopts the systolic ME [19] as a CUT
system. If the modulus m = 2k - 1, then the residue to demonstrate the feasibility of the proposed EDDR
code of modulo is given by architecture. A ME consists of many PEs
R = |X|m incorporated in a 1-D or 2-D array for video encoding
=|Y0+Y1|m = |Z0 + Z1|m = (Z0+Z1)α (5) applications. A PE generally consists of two ADDs
(i.e. an 8-b ADD and a 12-b ADD) and an
accumulator (ACC). Next, the 8-b ADD (a pixel has
8-b data) is used to estimate the addition of the
current pixel (Cur_pixel) and reference pixel
(Ref_pixel). Additionally, a 12-b ADD and an ACC
are required to accumulate the results from the 8-b
ADD in order to determine the sum of absolute
difference (SAD) value for video encoding
applications. Notably, some registers and latches may
exist in ME to complete the data shift and storage.
Fig. 2 shows an example of the proposed EDDR
circuit design for a specific PEi of a ME. The fault
Notably, since the value of Y0 + Y1 is model definition, RQCG-based TCG design,
generally greater than that of modulus m, the operations of error detection and data recovery, and
equations in (5) and (6) must be simplified further to the overall test strategy are described carefully as
replace the complex module operation with a simple follows.
addition operation by using the parameters Z0,Z1, α A. SAD Tree
and β . PEs utilizing the concept of the proposed SAD
Based on (5) and (6), the corresponding circuit Tree architecture.
design of the RQCG is easily realized by using the
simple adders (ADDs). Namely, the RQ code can be
International Journal of Electrical and Electronics Engineering (IJEEE) ISSN (PRINT): 2231 –5284, Vol-2, Issue-4

226
 Design of An Error Detection And Data Recovery Architecture For Motion Estimation Testing Applications

error(e) and the magnitude of (e) are assumed here to

be equal to SAD|-SAD, where SAD| denotes the
computed SAD value with SA faults.
C. TCG Design
According to Fig. 2, TCG is an important
component of the proposed EDDR architecture.
Notably, TCG design is based on the ability of the
RQCG circuit to generate corresponding test codes in
order to detect errors and recover data. The specific in
Fig. 2 estimates the absolute difference between the
Cur_pixel of the search area and the Ref_pixel of the
current macro block Thus, by utilizing PEs, SAD
shown in as follows, in a macro block with size of N
X N can be evaluated:

The proposed SAD Tree is a 2-D intra-level

architecture and consists of a 2-D PE array and one 2-
D adder tree with propagation registers Current pixels where rxij, qxij and ryij, qyij denote the corresponding
are stored in each PE, and reference pixels are stored RQ code of Xij and Yij modulo m . Importantly, Xij
in propagation registers for data reuse. In each cycle, and Yij represent the luminance pixel value of
current and reference pixels are inputted to PEs. Cur_pixel and Ref_pixel, respectively. Based on the
Simultaneously, continuous reference pixels in a row residue code, the definitions shown in (2) and (3) can
are inputted into propagation registers to update be applied to facilitate generation of the RQ code (RT
reference pixels. In propagation registers, reference and QT ) form TCG. Namely, the circuit design of
pixels are propagated in the vertical direction row by TCG can be easily achieved (see Fig. 3) by using
row. In SAD Tree architecture, all distortions of a
searching candidate are generated in the same cycle,
and by an adder tree, distortions are accumulated to
derive the SAD in one cycle.
B. Fault Model
The PEs are essential building blocks and are
connected regularly to construct a ME. Generally,
PEs are surrounded by sets of ADDs and
accumulators that determine how data flows through
them. PEs can thus be considered the class of circuits
called ILAs, whose testing assignment can be easily
achieved by using the fault model, cell fault model
(CFM). Using CFM has received considerable
interest due to accelerated growth in the use of high-
level synthesis, as well as the parallel increase in
complexity and density of integration circuits (ICs).
Using CFM makes the tests independent of the
adopted synthesis tool and vendor library. Arithmetic
modules, like ADDs (the primary element in a PE),
due to their regularity, are designed in an extremely
dense configuration.
Moreover, a more comprehensive fault model,
i.e. the stuck-at (SA) model, must be adopted to cover
actual failures in the interconnect data bus between
PEs. The SA fault is a well known structural fault
model, which assumes that faults cause a line in the
circuit to behave as if it were permanently at logic
“0” (stuck-at 0 (SA0)) or logic “1” [stuck-at 1 (SA1)].
The SA fault in a ME architecture can incur errors in Fig. 2. A specific Pei testing processes of the proposed EDDR
computing SAD values. A distorted computational architecture

International Journal of Electrical and Electronics Engineering (IJEEE) ISSN (PRINT): 2231 –5284, Vol-2, Issue-4

227
 Design of An Error Detection And Data Recovery Architecture For Motion Estimation Testing Applications

respectively. Notably, the proposed EDDR design

executes the error detection and data recovery
operations simultaneously. Additionally, error-free
data from the tested PEi or the data recovery that
results from DRC is selected by a multiplexer (MUX)
to pass to the next specific PEi+1 for sub sequent
testing.
E. Overall Test Strategy
By extending the testing processes of a specific
PEi in Fig. 2, Fig. 4 illustrates the overall EDDR
architecture design of a ME. First, the input data of
Cur_pixel and Ref_pixel are sent simultaneously to
PEs and TCGs in order to estimate the SAD values
and generate the test RQ code RT and QT. Second,
the SAD value from the tested object PEi , which is
selected by MUX1, is then sent to the RQCG circuit
Fig. 3. Circuit design of the TCG in order to generate RPEi and QPEi codes. Meanwhile,
the corresponding test codes RTi and QTi from a
D. EDDR Process specific TCGi are selected simultaneously by MUXs
Error detection in a specific PE is achieved by 2 and 3, respectively. Third, the RQ code from TCGi
using EDC, which is utilized to compare the outputs and RQCG circuits are compared in EDC to
between TCG and RQCG in order to determine determine whether the tested object PEi have errors.
whether errors have occurred. The EDC output is The tested object PEi is error-free if and only if RPEi =
then used to generate a 0/1 signal to indicate that the RTi and QPEi = QTi. Additionally, DRC is used to
tested is error-free/errancy. This work presents a recover data encoded by TCGi , i.e. the appropriate
mathematical statement to verify the operations of RTi and QTi codes from TCGi are selected by MUXs 2
error detection. Based on the definition of the fault and 3, respectively, to recover data. Fourth, the error-
model, the SAD value is influenced if either SA1 free data or data recovery results are selected by
and/or SA0 errors have occurred in a specific PE. In MUX . Notably, control signal S4 is generated from
other words, the SAD value is transformed to EDC, indicating that the comparison result is error-
if an error occurred. Notably, free (S4 = 0) or errancy (S4 = 1) . Finally, the error-
the error signal is expressed as free data or the data-recovery result from the tested
e = qe.m + re object PEi is passed to a De-MUX, which is used to
During data recovery, the circuit DRC plays a test the next specific PEi+1; otherwise, the final result
significant role in recovering RQ code from TCG. is exported.
The data can be recovered by implementing the
mathematical model as CONCLUSION

This work presents EDDR architecture for

detecting the errors and recovering the data of PEs in
a ME. Based on the RQ code, a RQCG-based TCG
design is developed to generate the corresponding test
To realize the operation of data recovery in, a codes to detect errors and recover data. The RQ code
Barrel shift and a corrector circuits are necessary to generation, test code generation was also discussed
achieve the functions of
REFERENCE

[1]. D. K. Park, H. M. Cho, S. B. Cho, and J. H. Lee, “A fast

motion estimation algorithm for SAD optimization in sub-
pixel,” in Proc. Int. Symp. Integr. Circuits, Sep. 2007, pp.
528–531.

[2]. J. F. Li and C. C. Hsu, “Efficient testing methodologies for

conditional sum adders,” in Proc. Asian Test Symp., 2004,
pp. 319–324.

[3]. D. P. Vasudevan, P. K. Lala, and J. P. Parkerson, “Self-

checking carryselect adder design based on two-rail
encoding,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54,
no. 12, pp. 2696–2705, Dec. 2007.
Fig.4. EDDR Architecture design for a ME
International Journal of Electrical and Electronics Engineering (IJEEE) ISSN (PRINT): 2231 –5284, Vol-2, Issue-4

228
 Design of An Error Detection And Data Recovery Architecture For Motion Estimation Testing Applications

[4]. X. Yu, T. Meng, Z. Dai, and X. Yang, “Design and normal basis multiplier over GF , IEEE Trans. Comput., vol.
implementation of reconfigurable shift unit using FPGAs,” in 58, no. 6, pp. 851–857, Jun. 2009.
Proc. IEEE Int. Symp. Pervasive Comput. Applic., Aug.
2006, pp. 543–545. [8]. L. Breveglieri, P. Maistri, and I. Koren, “A note on error
detection in an RSA architecture by means of residue codes,”
[5]. K. Neubeck, Practical Reliability Analysis. Englewood Cliffs, in Proc. IEEE Int. Symp. On-Line Testing, Jul. 2006, 176
NJ: Pearson Prentice-Hall, 2004. 177.

[6]. X. Li, J. Qin, B. Huang, X. Zhang, and J. B. Bernstein, “A [9]. S. J. Piestrak, D. Bakalis, and X. Kavousianos, “On the
new SPICE reliability simulation method for deep design of selftestingcheckers for modified Berger codes,” in
submicrometerCMOSVLSI circuits,” IEEE Trans. Device Proc. IEEE Int. WorkshopOn- Line Testing, Jul. 2001, pp.
Mater. Reliabil., vol. 6, no. 2, pp. 247–257,Jun. 2006. 153–157.

[7]. C. W. Chiou, C. C. Chang, C. Y. Lee, T. W. Hou, and J. M. [10]. S. Surin and Y. H. Hu, “Frame-level pipeline motion
Lin, “Concurrent error detection and correction in Gaussian estimation array processor,” IEEE Trans. Circuits Syst. Video
Technol., vol. 11, no. 2, pp. 248–251, Feb. 2001.



International Journal of Electrical and Electronics Engineering (IJEEE) ISSN (PRINT): 2231 –5284, Vol-2, Issue-4

229