IAES International Journal of Artificial Intelligence (IJ-AI)

Vol. 13, No. 2, June 2024, pp. 1479~1488

ISSN: 2252-8938, DOI: 10.11591/ijai.v13.i2.pp1479-1488  1479

Evaluation of genetic algorithm in network-on-chip based

architecture

Doraisamy Radha1, Minal Moharir2

1
Department of Computer Science and Engineering, School of Computing, Amrita Vishwa Vidyapeetham, Bengaluru, India
2
Department of Computer Science and Engineering, RV College of Engineering, Bengaluru, India

Article Info ABSTRACT

Article history: An increase in the number of cores gives a significant bounce in
performance than an improvement in any of the factors or hardware. Many
Received Apr 25, 2023 core systems use network-on-chip (NoC) for efficient communications
Revised Oct 5, 2023 among the cores in the system. However, the problem with NoC-based
Accepted Nov 16, 2023 communication is that it significantly consumes a large amount of power and
energy because the number of routers increases with the increase in the
number of cores in the system. Power consumed by such components leads
Keywords: to degradation of the performance. The placement of cores in the topology is
non-deterministic polynomial-time hardness (NP-Hard) problem. The
Booksim optimal placement of cores in NoC is essential as it minimizes latency and
Genetic algorithm communication costs. Thus, the NP-Hard problem of placing cores is solved
Latency using genetic algorithm (GA) based quadtree topology. The proposed work
Network-on-chip shows the analysis of GA-based quadtree topology, which outperforms other
Power topologies in most aspects. The performance evaluation of GA-based
Throughput quadtree topology is based on latency, throughput, power, area, bisection
bandwidth, and diameter. Comparing these parameters with other topologies
shows the prominence of the quadtree topology. The evaluation is performed
in the Booksim simulator, and the experimental results revealed that the
proposed GA-based quad tree-based topology is efficient for NoC-based
communications.
This is an open access article under the CC BY-SA license.

Corresponding Author:
Doraisamy Radha
Department of Computer Science and Engineering, School of Computing, Amrita Vishwa Vidyapeetham
Bengaluru, India
Email: [email protected]

1. INTRODUCTION
Technological development and the requirement for fast response in every field emerge in many
processing cores. Intel provides an era with supercomputing speed, performance, and compatibility.
Emerging technologies like big data analytics, artificial intelligence, and growth in multimedia, the internet
of things (IoT) require a high-end system for processing. According to Karl Rupp, according to Moore’s law,
all factors go through a flat curve, whereas the number of cores only increases [1]. However, doing parallel
programming for every problem in multicore/many-core is challenging for programmers. Therefore, there is
a high need to utilize the cores effectively and improve performance. Topology, routers, flow control,
switches, traffic pattern, routing algorithms, packet size, and buffer size are the contributors to the evaluation
of the network of cores, which in turn plays a vital role in the performance of the whole architecture. Based
on the arrangements of these routers, cores, and other hardware associated with the network-on-chip (NoC),
there are different topologies framed like mesh, ring, and quad, each one has its advantages and
disadvantages.

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Mesh topology is one of the simplest and most commonly used topologies in the arrangement of
cores, and a good amount of research about the performance has been done using mesh networks [2]. But in
search of better performance across various factors, including less power consumption, low latency, and high
performance. This has led to the discovery of other topologies such as torus, spidergon, quadtree, and
Dragonfly. The various simulators allow an analysis of the performance of different topologies by varying
the different aspects or components of the architecture like the number of nodes, buffer size, and routing
algorithm being used. Routing algorithms play a vital role in using the cores effectively. For each topology,
routing algorithms with and without adaptiveness make a notable difference in the evaluation parameters of
the performance of the NoC architecture.
A few simulators used for NoC to carry out experiments to measure performance by varying the
architecture configuration are Noxim, NocTweak, Nirgam, Booksim, Orion, Garnet, Dsent, Wormsim,
Gem5, and a few others are meant for field programmable gate arrays (FPGA) related [3]. Booksim2
simulator is a popular NoC simulator for modeling the interconnection network for many cores. This
simulator provides options to work for different topologies, routing algorithms, and different sizes. The
configuration can be set accordingly, and the performance can be analyzed. Various modules are available
for analyzing flit latency, packet latency, network latency, and throughput. Power and area modules are also
available for evaluating power and area for the components used for the configuration settings.
Communication among the cores is also crucial to improve the performance of the multi/many-core
systems. In many-core processors, NoC-based communication is considered a better solution for
communication among cores when compared with bus-based communication. NoC-based chip-
multiprocessors (CMP) consume considerable power for a core, private level 1 instruction, and data caches, a
second level cache that could be shared or made private, a router and logic block, links, buffers, and
crossbars [1]. Leakage power can also be a NoC’s power consumption. The advancements place demands for
high performance and low power consumption in embedded systems. Objectives have shifted from high peak
performance to power efficiency [4]. Therefore, embedded systems challenge designers because of their
power and performance budgets. Thus, processing power is one of the significant demands for applications in
which power consumption for other components like high-resolution sensors is also high. The microgrid’s
performance is completely based on power consumption [5].
The total number of links, routers, and buffers required is dependent on the number of cores N, the
number of local buffers, and the virtual channels 𝑁𝑉𝐶 to be used. It is calculated as given in (1)-(3). C-Mesh is
a concentrated mesh like a Mesh with wrap-around links to reduce the diameter of the Mesh topology. For C-
Mesh, the requirements are calculated as given in (4) and (5). Dragonfly is a hierarchical network with three
levels: router, group, and system. At the bottom level, each router has connections to cores, local routers in
the current group, and global routers in other groups. Where 𝑁𝑔 represents the number of groups and 𝑛𝑔𝑟
represents the number of routers in group g. This can be mathematically represented as given in (6) and (7):

𝑁𝑙 = 2√𝑁√𝑁 − 1 ∗ 𝑁𝑉𝐶 (1)

𝑁𝑟 = 𝑛 (2)

𝑁𝑏 = 5 ∗ 𝑁𝑏 ∗ 𝑁𝑉𝐶 ∗ 𝑁 (3)

𝑁
𝑁𝑙 = 2√𝑁√ − 1 ∗ 𝑁𝑉𝐶 (4)
2

𝑛
𝑁𝑟 = (5)
4

𝑁𝑟 = 𝑛𝑔𝑟 ∗ 𝑁𝑔 (6)

𝑁𝑙 = 𝑁𝑝 (7)

Dragonflies are constructed for a minimal number of endpoints. The parameter ‘p’ denotes the
number of terminals per router untouched. p is, however, a key factor in the Dragonfly construction, as it
determines not only the final scalability of the topology but also the required router radix [6]. Moreover, the
total number of links employed in the Dragonflies greatly varies with d and b, and consequently, so does the
bandwidth that is made available. If a substantial amount of bandwidth is available within the topology, e.g.,

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when the Dragonfly is electrically balanced, it is interesting to populate the S routers with more terminals to
exploit the available bandwidth ideally [7].
Quadtree topology is based on a spatial data structure that stores elements in a partitioned 2D space.
The 2D space is recursively subdivided into four quadrants. This type of hierarchical arrangement of cores
helps to place the elements of the exact location in the same partition. The closest point for the given
coordinates can be made using quadtrees. The quadtree has various applications like image processing,
geographical distancing, and networking. The quadtree data structure is widely used in digital image
processing and computer graphics for modeling spatial segmentation of images and surfaces. An efficient
indexing scheme is proposed for a linear (pointerless) quadtree data structure. Such a quadtree is stored using
a uni-dimensional array of nodes. The indexing scheme has the property that the navigation between any pair
of nodes can be computed in constant time.
Moreover, navigation across multiple quadtrees can also be achieved at the same cost [8]. A
distributed quadtree index that adapts the quadtree is described as that enables more robust access to data in
peer-to-peer (P2P) networks. The indexing usage is easy, scalable, and has good load-balancing properties
[9]. A design, implementation, and performance evaluation of NoC-based multicore architecture for
accelerating the median breakpoint problem in phylogeny has been designed. On the network architecture
front, the superiority of a quadtree over a mesh in energy efficiency is demonstrated for this application class.
The proposed work is to analyze the quadtree topology in NoC architecture for better performance in terms
of throughput, power, area, and bisection bandwidth [10]. The quad has been applied over various domains to
solve many problems and is presented in many of the author’s works comprising greedy-quadtree-greedy
routing algorithm on quadtree for guaranteed delivery, lower hops, and load balancing for geographic
routing. A node represents a multi-quadtree network with one or more squares, and each square can have one
or more representative nodes. This representation helps load balancing and shortest paths in routing [11].
Fault tolerance is required for the optimal functioning of NoC architecture. A mesh of 2*2 routers has been
arranged with a spare router placed at the center—the designed quad-spare mesh [12]. NoC seems to replace
traditional bus-based communications as it provides high reliability and scalability. Reconfigurable network
on chip has been designed to provide encryption, authentication, and denial of service attacks [13].
A genetic algorithm (GA) has been used to construct the decision tree for classifying mobile users.
The crossover and mutation operators are prominent in building optimal decision trees. Traditional
algorithms consume more time and complex mechanisms to make a decision [14]. The designed GA-based
decision tree was compared with support vector machine (SVM) on the breast cancer dataset is 78.50% [15].
The GA has been combined with classification and regression tree (CART) to boost the performance while
performing classification. Random CART trees have been generated to make the initial population, and in
each iteration, the performance of the CART tree has been boosted using various genetic operators such as
crossover and mutation [16].
A GA has been used to construct the distance matrix for phylogenetic tree construction. As the GA
uses the natural genetic operator’s crossover and mutation, the tree generated is highly trustworthy as the
distance matrix is generated by GA [17]. The decision trees generated using C4.5 are subjected to undergo
crossover, and mutation still converges to produce an optimal decision tree [18]. The application mapping in
NoC is non-deterministic polynomial-time hardness (NP-Hard) problem solved using GA. GA has been used
to minimize the communication cost of NoC and improve the convergence of network partitioning [19]. The
placement of cores on the device has been solved using adaptive GA to minimize the communication cost.
The adaptive GA does not rely on fixed probability to converge towards the minimum global optimal
solution. The balance between crossover and mutation has been controlled for the optimal placement of cores
[20]–[22]. To snoop data from the adjacent wavelength channels in a shared photonic waveguide, which
introduces a severe security threat [23], [24]. The GA is one of the first population stochastic algorithms [25].

2. METHOD
2.1. Genetic algorithm-based quad tree topology
The GA is a meta-heuristic algorithm inspired by the behavior of genetic chromosomes. The
population-based GA could act over trees and provide optimal global solutions. Given these advantages, GA
is proven to be the best solution for solving problems in which solutions are represented as trees. Regarding
GA, a population of a potential solution is taken randomly for the given problem, where each solution is
referred to as a chromosome. The objective of GA is to find the chromosome that best evaluates the given
fitness function.
This section describes constructing the quadtree organization of chips using GA. Each chromosome
is represented as a tree, which is shown in Figure 1. Let 𝑐𝑖 , represents the ith chip. The link between the chips
represents communication. Thus, the population represents a collection of chromosomes for the cores. The
fitness function considered for validating the chromosomes is latency and throughput. The GA-based
Evaluation of genetic algorithm in network-on-chip based architecture … (Doraisamy Radha)
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quadtree has been constructed to minimize latency and maximize throughput. The population in GA has been
represented with various quadtrees, and in each iteration, the population members are selected using rank-
based selection. The selected parents are subjected to reproduction using a recombination operator, uniform
crossover to produce offspring for the next generation. This has been repeated until convergence. At each
iteration, the performance of the quadtree is evaluated in terms of fitness, which has minimum latency and
maximum throughput. The working of GA-based quadtree is shown in Algorithm 1.

Figure 1. Chromosome in the population

Algorithm 1. GA_Based_Quad_Tree( )
Input: Cores 𝑐1 , 𝑐2 , … 𝑐𝑛
Ouptut: Optimal Quad Tree 𝑄𝑇
Initialize random Quad Trees as 𝑃 ← 𝑅𝑄𝑇1 , 𝑅𝑄𝑇2 , … , 𝑅𝑄𝑇𝑛
While convergence
For each𝑅𝑄𝑇𝑖 ∈ 𝑅𝑄𝑇
Compute fitness using Equation
End For
Sort the fitness and assign a rank
Select the parent random quadtrees for crossover
Randomly select a crossover point
𝑜𝑓𝑓𝑘 , 𝑜𝑓𝑓𝑙 = 𝑐𝑟𝑜𝑠𝑠𝑜𝑣𝑒𝑟(𝑅𝑄𝑇𝑖 , 𝑅𝑄𝑇𝑗 )
𝑃 ← 𝑃 − {𝑅𝑄𝑇𝑖 , 𝑅𝑄𝑇𝑗 }
𝑃 ← 𝑃 ∪ {𝑜𝑓𝑓𝑘 , 𝑜𝑓𝑓𝑙 }
End While
Return 𝑅𝑄𝑇𝐵𝑒𝑠𝑡

2.2. Fitness function

The fitness function evaluates the individual random quadtree according to the criteria of minimal
latency and minimum communication cost. The random quadtree with minimal fitness value is considered
the best quadtree construction of a NoC. Fitness is represented in (8). Latency refers to the amount of time
taken from starting the job until the completion of the request. Long latency incurs a huge network
communication bottleneck, which is a severe threat. Thus, the first objective considered is minimizing
latency. In addition, when the chips are communicated when transferring data to get the job done, it is
expected to have the minimum communication cost. Thus, the second objective considered is minimizing
communication costs, as shown in (10). 𝑤1 , 𝑤2 represents the weight associated with latency and
communication cost. Where ℎ𝑜𝑝𝑖,𝑗 represents the path length between ith core and jth core present in the path
from source to destination core. 𝑏𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ𝑖,𝑗 represents the bandwidth acquired in the link between i th core
and jth core.

𝑀𝑖𝑛𝑓(𝑅𝑄𝑇) = 𝑤1 ∗ 𝑙𝑎𝑡𝑒𝑛𝑐𝑦 + 𝑤2 ∗ 𝐶𝑜𝑠𝑡_𝐶𝑜𝑚𝑚 (8)

Subject to

𝑤1 + 𝑤2 = 1 (9)

𝐶𝑜𝑠𝑡_𝐶𝑜𝑚𝑚 ← ∑𝑛𝑖=1 ℎ𝑜𝑝𝑖,𝑗 ∗ 𝑏𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ𝑖,𝑗 (10)

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2.3. Rank based selection

The chromosomes in the population are sorted according to the fitness value and rank assigned to
each chromosome. Then the probability that the chromosome is selected is done according to the rank. Using
rank-based selection, the crowding phenomenon has been avoided; thus, the individuals in the population
tend to converge faster with an optimal solution. In addition, the problem of stagnation and premature
convergence of GA has been eliminated by using this rank-based selection. The sum of the rank has been
computed using (11). The probability of selecting the individual based on the rank is given in (12). Where 𝑟𝑖 ,
denotes the rank of the ith chromosome. 𝑃𝑟𝑖 , denotes the probability of selecting the ith chromosome.

𝑠𝑢𝑚_𝑟𝑎𝑛𝑘 ← ∑𝑛𝑖=1 𝑟𝑖 (11)

𝑟𝑖
𝑃𝑟𝑖 ← (12)
𝑠𝑢𝑚_𝑟𝑎𝑛𝑘

2.4. Crossover
After selecting the individual for recombination using rank-based selection, the individuals are
subjected to reproduction. Arbitrarily, a subtree has been chosen from each individual subjected for
reproduction, and they are interchanged, as illustrated in Figure 2. After being subjected to reproduction, the
individuals in the current generation are replaced with new offspring. This process is repeated until
convergence. The diagrammatic representation of the working of Algorithm 1 is shown in Figure 3.

Figure 2. Crossover of individuals in the population

Figure 3. Working of GA-based quadtree

3. RESULTS AND DISCUSSION

The results produced by the simulations on Booksim are shown in the following figures. The results
are obtained by varying the several associated parameters related to overall NoC architecture, including
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traffic, number of routers, and number of virtual channels. A comparison of these results across various
topologies like mesh, C-Mesh, Dragonfly, and fat trees is discussed in this section. In this section, other
factors besides latency and processing power are also considered for determining a good architecture. These
factors include power consumption and area. By the end of the section, the most powerful architecture could
be determined by analyzing various factors.
The experiment set up for our comparison is that there are 16*16=256 nodes, an injection rate is
0.01, and there are 8 virtual channels per router. The traffic followed is uniform so that each core in the
Network is performing an equal amount of work as that of the other and it is equally busy as like others.
Figure 4 is evident from the fact that the areas of quadtree topology are much less than the other compared
architectures, like Mesh, C-Mesh, and Dragonfly. Of all those, C-Mesh performs the worst in all the
compared areas, like switch area, channel area, and other components area. The quadtree topology beats all
its components in all aspects of the area. It is seen that it occupies only about sq. units of area for fitting all
the 256 cores along with their related components like routers, channels, and other connecting components.
The details make us consider putting quadtree to use when space is a concern and opening its doors for their
use in portable and handheld devices.
Here Figure 4 shows the switch area of topology, Figure 5 shows the channel area of topology, Figure
6 shows the other areas of topology, and Figure 7 shows the total areas of various topologies. In addition, we
could see that there is only a linear increase in the area, i.e., for 64 cores, it is 1 square unit, and for 64×64=256
cores, the total area is only 1×4=4 square units, which is impressive. Figure 8 shows the comparison of the total
area with an increase in cores in 16 nodes. Figure 9 shows the comparison of the total area with an increase in
cores in 256 nodes. The area factor is scalable across various sizes, and it is good with much bigger
architectures. Thus, the quadtree is perfect in terms of space and is significantly better than the other topologies,
and the increase in space is linear, making it eligible to be used even with bigger core sizes.
As we discussed, power consumption is also an essential factor to consider. Figure 10 shows the
consumptions of channel wire power of topologies for 256 nodes, injection rate =0.01, vcs =8, and uniform
traffic. Figure 11 shows the consumptions of switch power of topologies for 256 nodes, injection rate =0.01,
vcs =8, and uniform traffic. Figure 12 shows the consumptions of other components' power of topologies for
256 nodes, injection rate =0.01, vcs=8, and uniform traffic.

Figure 4. Switch area of various topologies Figure 5. Channel area of various topologies

Figure 6. Other areas of various topologies Figure 7. Total area of various topologies

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Figure 13 shows the consumptions of the total power of topologies for 256 nodes, injection rate
=0.01, vcs =8, and uniform traffic. As we can see in Figure 13, the quadtree topology uses less power than
the other topologies. Hence, it uses only around 25 watts when compared to the worst performing C-Mesh
using about 400 watts also, we could see this trend is maintained with the increase in the injection rate as
there has been only steady growth so therefore it is reasonable to use the quadtree topology for efficient and
better power consumption.

Figure 8. Comparison of total area in topologies Figure 9. Comparison of total area in topologies

Figure 10. Channel wire power consumption of Figure 11. Switch power consumption of topologies
topologies

Figure 12. Other components power consumption Figure 13. Total consumption of topologies

Figure 14 shows the total power consumption of various topologies with for 64 nodes with 0.01
injection rate. Figure 15 shows the total power consumption of various topologies for 64 nodes with 0.10
injection rate. The comparison of some of the latency-related factors is shown in Figures 16-18 in terms of

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latency, hop average, and throughput of various topologies for 16×16 nodes=256 with injection rate =0.01,
vcs=8, and uniform traffic. The quadtree performs very much better over the traditional architecture like
Mesh, C-Mesh for the given experimental setup with 256 cores and the number of hops taken to travel from
the source to destination routed is significantly small in the case of the quadtree. Regarding the above factors,
the quadtree is one of the suitable topologies that need to be considered. The throughput is the same for all
the topologies, and it remains unaffected by the topology change. In addition, we could see that the
Dragonfly topology may perform slightly better in the latency and hop count over the quadtree, but it has its
limitations regarding power and area.

Figure 14. Total power consumption with 0.01 Figure 15. Total power consumption with 0.10
injection rate injection rate

Figure 16. Latency of topologies Figure 17. Hop average of topologies

Figure 18. Throughput of topologies

4. CONCLUSION
This paper discusses topologies in the NoC architecture like Mesh, C-Mesh, quadtree, and
Dragonfly. In addition, power, area, and other factors are shown as necessary, along with the latency and

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computing power in determining a good NoC architecture. Moreover, it is shown that the quadtree topology
performs much better in terms of area and power consumption over the other topologies without any
comprise in the latency and hop count. The analysis shows that in the power and space-limited world, the
quadtree topology is an essential topology to be considered today with the growth of many handheld devices
like smartphones and other IoT devices that are power and space-limited in nature. The quadtree topology in
their architecture is a good solution for overcoming the problem by minimizing latency and better
throughput. Further studies can be done with quadtree topology for the heterogeneous arrangement of cores
and their performances.

ACKNOWLEDGEMENTS
I would like to express our sincere gratitude to all those who have supported and contributed to this
research project. Primarily, I extend our heartfelt thanks to our guide for his unwavering guidance, invaluable
insights, and encouragement throughout the research process. No funding is raised for this research.

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BIOGRAPHIES OF AUTHORS

Doraisamy Radha is currently working as an assistant professor, Department of

Computer Science and Engineering at Amrita School of Engineering, Amrita Vishwa
Vidyapeetham. She has completed her Ph.D. in Computer Science and Engineering at
Visvesvaraya Technological University, M.Tech. (CSE) at Dr. MGR University, and B.E.
(CSE) at Madurai Kamaraj University. Her 22 years of teaching experience include teaching
and research. Her areas of interest are data structures, cryptography, high-performance
computing, multicore architecture, image processing, and web technology. She has published
around 30 technical papers in national/ international journals and conferences. She can be
contacted at email: [email protected].

Prof. Minal Moharir is presently working as a professor, Department of

Computer Science and Engineering at R V College of Engineering. Her Academic
Qualification includes Ph.D. in Information and Network Security (Avinashilingam
University, Coimbatore), M.Tech. (VTU) in Computer Network Engineering, and B.E. in
Computer Science and Engineering (GECA). Her 20 years of experience includes teaching,
training, and research. Her professional expertise includes computer networks, data
communication, information security, wireless sensor networks, IoTs, high-performance
computing, and GPU Computing. She can be contacted at email: [email protected].

Int J Artif Intell, Vol. 13, No. 2, June 2024: 1479-1488