a Micropower, Single and Dual Supply

Rail-to-Rail Instrumentation Amplifier

AD627
FEATURES FUNCTIONAL BLOCK DIAGRAM
Micropower, 85 ␮A Max Supply Current 8-Lead Plastic DIP (N) and SOIC (R)
Wide Power Supply Range (+2.2 V to ⴞ18 V)
Easy to Use RG 1 8 RG
Gain Set with One External Resistor
–IN 2 7 +VS
Gain Range 5 (No Resistor) to 1,000
+IN 3 6 OUTPUT
Higher Performance than Discrete Designs
–VS 4 5 REF
Rail-to-Rail Output Swing AD627
High Accuracy DC Performance
0.10% Gain Accuracy (G = +5) (AD627A)
10 ppm Gain Drift (G = +5) Wide supply voltage range (+2.2 V to ± 18 V), and micropower
125 ␮V Max Input Offset Voltage (AD627B) current consumption make the AD627 a perfect fit for a wide
200 ␮V Max Input Offset Voltage (AD627A) range of applications. Single supply operation, low power con-
1 ␮V/ⴗC Max Input Offset Voltage Drift (AD627B) sumption and rail-to-rail output swing make the AD627 ideal for
3 ␮V/ⴗC Max Input Offset Voltage Drift (AD627A) battery powered applications. Its rail-to-rail output stage maxi-
10 nA Max Input Bias Current mizes dynamic range when operating from low supply voltages.
Noise: 38 nV/√Hz RTI Noise @ 1 kHz (G = +100) Dual supply operation (± 15 V) and low power consumption make
Excellent AC Specifications the AD627 ideal for industrial applications, including 4 mA-to-
77 dB Min CMRR (G = +5) (AD627A) 20 mA loop-powered systems.
83 dB Min CMRR (G = +5) (AD627B)
The AD627 does not compromise performance, unlike other
80 kHz Bandwidth (G = +5)
micropower instrumentation amplifiers. Low voltage offset, offset
135 ␮s Settling Time to 0.01% (G = +5, 5 V Step)
drift, gain error, and gain drift keep dc errors to a minimum in
APPLICATIONS the users system. The AD627 also holds errors over frequency
4 mA-to-20 mA Loop Powered Applications to a minimum by providing excellent CMRR over frequency.
Low Power Medical Instrumentation—ECG, EEG Line noise, as well as line harmonics, will be rejected, since
Transducer Interfacing the CMRR remains high up to 200 Hz.
Thermocouple Amplifiers The AD627 provides superior performance, uses less circuit board
Industrial Process Controls area and does it for a lower cost than micropower discrete designs.
Low Power Data Acquisition
Portable Battery Powered Instruments 100
AD627
90
PRODUCT DESCRIPTION
80
The AD627 is an integrated, micropower, instrumentation
amplifier that delivers rail-to-rail output swing on single and 70

dual (+2.2 V to ± 18 V) supplies. The AD627 provides the user

CMRR – dB

60
with excellent ac and dc specifications while operating at only 50
85 µA max. TRADITIONAL
40 LOW POWER
The AD627 offers superior user flexibility by allowing the user DISCRETE DESIGN
30
to set the gain of the device with a single external resistor, and
by conforming to the 8-lead industry standard pinout configura- 20
tion. With no external resistor, the AD627 is configured for a 10
gain of 5. With an external resistor, it can be programmed for
0
gains of up to 1000. 1 10 100 1k 10k
FREQUENCY – Hz

Figure 1. CMRR vs. Frequency, ± 5 VS, Gain = +5

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD627–SPECIFICATIONS
SINGLE SUPPLY (Typical @ 25ⴗC Single Supply, V = 3 V and 5 V and R = 20 k⍀, unless otherwise noted.)
S L

Model AD627A AD627B

Specification Conditions Min Typ Max Min Typ Max Unit
GAIN G = +5 + (200 kΩ/RG)
Gain Range 5 1000 5 1000 V/V
Gain Error1 VOUT = (–VS) + 0.1 to (+VS) – 0.15
G = +5 0.03 0.10 0.01 0.06 %
G = +10 0.15 0.35 0.10 0.25 %
G = +100 0.15 0.35 0.10 0.25 %
G = +1000 0.50 0.70 0.25 0.35 %
Nonlinearity
G = +5 10 100 10 100 ppm
G = +100 20 100 20 100 ppm
Gain vs. Temperature1
G = +5 10 20 10 20 ppm/°C
G>5 –75 –75 ppm/°C
VOLTAGE OFFSET
Input Offset, VOSI2 50 250 25 150 µV
Over Temperature VCM = VREF = +VS/2 445 215 µV
Average TC 0.1 3 0.1 1 µV/°C
Output Offset, VOSO 1000 500 µV
Over Temperature 1650 1150 µV
Average TC 2.5 10 2.5 10 µV/°C
Offset Referred to the Input
vs. Supply (PSRR)
G = +5 86 100 86 100 dB
G = +10 100 120 100 120 dB
G = +100 110 125 110 125 dB
G = +1000 110 125 110 125 dB
INPUT CURRENT
Input Bias Current 3 10 3 10 nA
Over Temperature 15 15 nA
Average TC 20 20 pA/°C
Input Offset Current 0.3 1 0.3 1 nA
Over Temperature 2 2 nA
Average TC 1 1 pA/°C
INPUT
Input Impedance
Differential 20储2 20储2 GΩ储pF
Common-Mode 20储2 20储2 GΩ储pF
Input Voltage Range3 VS = 2.2 V to 36 V (–VS) – 0.1 (+VS) – 1 (–VS) – 0.1 (+VS) – 1 V
Common-Mode Rejection3
Ratio DC to 60 Hz with VREF = VS/2
1 kΩ Source Imbalance
G = +5 VS = 3 V, VCM = 0 V to 1.9 V 77 90 83 96 dB
G = +5 VS = 5 V, VCM = 0 V to 3.7 V 77 90 83 96 dB
OUTPUT
Output Swing RL = 20 kΩ (–VS) + 25 (+VS) – 70 (–VS) + 25 (+VS) – 70 mV
RL = 100 kΩ (–VS) + 7 (+VS) – 25 (–VS) + 7 (+VS) – 25 mV
Short-Circuit Current Short-Circuit to Ground ± 25 ± 25 mA
DYNAMIC RESPONSE
Small Signal –3 dB Bandwidth
G = +5 80 80 kHz
G = +100 3 3 kHz
G = +1000 0.4 0.4 kHz
Slew Rate +0.05/–0.07 +0.05/–0.07 V/µs
Settling Time to 0.01% VS = 3 V, 1.5 V Output Step
G = +5 65 65 µs
G = +100 290 290 µs
Settling Time to 0.01% VS = 5 V, 2.5 V Output Step
G = +5 85 85 µs
G = +100 330 330 µs
Overload Recovery 50% Input Overload 3 3 µs
NOTES
1
Does not include effects of external resistor R G.
2
See Table III for total RTI errors.
3
See Applications section for input range, gain range and common-mode range.
Specifications subject to change without notice .

–2– REV. B
 AD627
DUAL SUPPLY (Typical @ 25ⴗC Dual Supply, VS = ⴞ5 V and ⴞ15 V and RL = 20 k⍀, unless otherwise noted.)
Model AD627A AD627B
Specification Conditions Min Typ Max Min Typ Max Unit
GAIN G = +5 + (200 kΩ/RG)
Gain Range 5 1000 5 1000 V/V
Gain Error1 VOUT = (–VS) + 0.1 to (+VS) – 0.15
G = +5 0.03 0.10 0.01 0.06 %
G = +10 0.15 0.35 0.10 0.25 %
G = +100 0.15 0.35 0.10 0.25 %
G = +1000 0.50 0.70 0.25 0.35 %
Nonlinearity
G = +5 VS = ± 5 V/± 15 V 10/25 100 10/25 100 ppm
G = +100 VS = ± 5 V/± 15 V 10/15 100 10/15 100 ppm
Gain vs. Temperature1
G = +5 10 20 10 20 ppm/°C
G>5 –75 –75 ppm/°C
VOLTAGE OFFSET Total RTI Error = VOSI + VOSO/G
Input Offset, VOSI2 25 200 25 125 µV
Over Temperature VCM = VREF = 0 V 395 190 µV
Average TC 0.1 3 0.1 1 µV/°C
Output Offset, VOSO 1000 500 µV
Over Temperature 1700 1100 µV
Average TC 2.5 10 2.5 10 µV/°C
Offset Referred to the Input
vs. Supply (PSRR)
G = +5 86 100 86 100 dB
G = +10 100 120 100 120 dB
G = +100 110 125 110 125 dB
G = +1000 110 125 110 125 dB
INPUT CURRENT
Input Bias Current 2 10 2 10 nA
Over Temperature 15 15 nA
Average TC 20 20 pA/°C
Input Offset Current 0.3 1 0.3 1 nA
Over Temperature 5 5 nA
Average TC 5 5 pA/°C
INPUT
Input Impedance
Differential 20储2 20储2 GΩ储pF
Common-Mode 20储2 20储2 GΩ储pF
Input Voltage Range3 VS = ± 1.1 V to ± 18 V (–VS) – 0.1 (+VS) – 1 (–VS) – 0.1 (+VS) – 1 V
Common-Mode Rejection3
Ratio DC to 60 Hz with
1 kΩ Source Imbalance
G = +5–1000 VS = ± 5 V, VCM = –4 V to +3.0 V 77 90 83 96 dB
G = +5–1000 VS = ± 15 V, VCM = –12 V to +10.9 V 77 90 83 96 dB
OUTPUT
Output Swing RL = 20 kΩ (–VS) + 25 (+VS) – 70 (–VS) + 25 (+VS) – 70 mV
RL = 100 kΩ (–VS) + 7 (+VS) – 25 (–VS) + 7 (+VS) – 25 mV
Short-Circuit Current Short Circuit to Ground ± 25 ± 25 mA
DYNAMIC RESPONSE
Small Signal –3 dB Bandwidth
G = +5 80 80 kHz
G = +100 3 3 kHz
G = +1000 0.4 0.4 kHz
Slew Rate +0.05/–0.06 +0.05/–0.06 V/µs
Settling Time to 0.01% VS = ± 5 V, +5 V Output Step
G = +5 135 135 µs
G = +100 350 350 µs
Settling Time to 0.01% VS = ± 15 V, +15 V Output Step
G = +5 330 330 µs
G = +100 560 560 µs
Overload Recovery 50% Input Overload 3 3 µs
NOTES
1
Does not include effects of external resistor R G.
2
See Table III for total RTI errors.
3
See Applications section for input range, gain range and common-mode range.
Specifications subject to change without notice.

REV. B –3–
AD627–SPECIFICATIONS
BOTH DUAL AND SINGLE SUPPLIES
Model AD627A AD627B
Specification Conditions Min Typ Max Min Typ Max Unit

NOISE

Voltage Noise, 1 kHz Total RTI Noise = (eni)2 + (eno/G )2

Input, Voltage Noise, eni 38 38 nV/√Hz
Output, Voltage Noise, eno 177 177 nV/√Hz
RTI, 0.1 Hz to 10 Hz
G = +5 1.2 1.2 µV p-p
G = +1000 0.56 0.56 µV p-p
Current Noise f = 1 kHz 50 50 fA/√Hz
0.1 Hz to 10 Hz 1.0 1.0 pA p-p
REFERENCE INPUT
RIN RG = ∞ 125 125 kΩ
Gain to Output 1 1
Voltage Range1
POWER SUPPLY
Operating Range Dual Supply ± 1.1 ± 18 ± 1.1 ± 18 V
Single Supply 2.2 36 2.2 36 V
Quiescent Current 60 85 60 85 µA
Over Temperature 200 200 nA/°C
TEMPERATURE RANGE
For Specified Performance –40 +85 –40 +85 °C
NOTES
1
See Applications section for input range, gain range and common-mode range.
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS 1 NOTES

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V 1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
Internal Power Dissipation2 nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
Plastic Package (N) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W section of this specification is not implied. Exposure to absolute maximum rating
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . 0.8 W conditions for extended periods may affect device reliability.
2
–IN, +IN . . . . . . . . . . . . . . . . . . . . –VS – 20 V to +VS + 20 V Specification is for device in free air:
Common-Mode Input Voltage . . . –VS – 20 V to +VS + 20 V 8-Lead Plastic DIP Package: θJA = 90°C/W.
8-Lead SOIC Package: θJA = 155°C/W.
Differential Input Voltage (+IN – (–IN)) . . . . . . . +VS – (–VS)
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range N, R . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C

ORDERING GUIDE

Model Temperature Range Package Descriptions Package Options

AD627AN –40°C to +85°C Plastic DIP N-8
AD627AR –40°C to +85°C Small Outline (SOIC) SO-8
AD627AR-REEL –40°C to +85°C 8-Lead SOIC 13" Reel SO-8
AD627AR-REEL7 –40°C to +85°C 8-Lead SOIC 7" Reel SO-8
AD627BN –40°C to +85°C Plastic DIP N-8
AD627BR –40°C to +85°C Small Outline (SOIC) SO-8
AD627BR-REEL –40°C to +85°C 8-Lead SOIC 13" Reel SO-8
AD627BR-REEL7 –40°C to +85°C 8-Lead SOIC 7" Reel SO-8

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD627 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. B
 AD627
Typical Performance Characteristics (@ 25ⴗC VS = ⴞ5 V, RL = 20 k⍀ unless otherwise noted.)

100 –5.5

90
–5.0
80
–4.5

INPUT BIAS CURRENT – nA

70
NOISE – nV/ Hz, RTI

–4.0 VS = +5V
60
GAIN = +5
50 –3.5 VS = ⴞ5V

40
–3.0
30
GAIN = +100 –2.5 VS = ⴞ15V
20
GAIN = +1000
10 –2.0

0 –1.5
1 10 100 1k 10k 100k –60 –40 –20 0 20 40 60 80 100 120 140
FREQUENCY – Hz TEMPERATURE – ⴗC

TPC 1. Voltage Noise Spectral Density vs. Frequency TPC 4. Input Bias Current vs. Temperature

100 65.5

90
64.5
POWER SUPPLY CURRENT – ␮A
80
CURRENT NOISE – fA/ Hz

70
63.5
60

50 62.5

40
61.5
30

20
60.5
10

0 59.5
1 10 100 1k 10k 0 5 10 15 20 25 30 35 40
FREQUENCY – Hz TOTAL POWER SUPPLY VOLTAGE – Volts

TPC 2. Current Noise Spectral Density vs. Frequency TPC 5. Supply Current vs. Supply Voltage

–3.200 V+

VS = ⴞ15V
–3.000 (V+) –1
OUTPUT VOLTAGE SWING – Volts
INPUT BIAS CURRENT – nA

VS = ⴞ1.5V
–2.800 (V+) –2 VS = ⴞ5V
VS = ⴞ2.5V
SOURCING
–2.600 (V+) –3

–2.400 (V–) +2
SINKING

VS = ⴞ5V
–2.200 (V–) +1 VS = ⴞ2.5V
VS = ⴞ1.5V
VS = ⴞ15V
–2.000 V–
–15 –10 –5 0 5 10 15 0 5 10 15 20 25
COMMON-MODE INPUT – Volts OUTPUT CURRENT – mA

TPC 3. IBIAS vs. CMV, VS = ± 15 V TPC 6. Output Voltage Swing vs. Output Current

REV. B –5–
AD627
120

110

100 G = +1000
500mV 1s

100 90
90 G = +100
80

PSRR – dB
70

60 G = +5

10
50
0%
40

30

20
10 100 1k 10k 100k
FREQUENCY – Hz

TPC 7. 0.1 Hz to 10 Hz Current Noise (0.71 pA/DIV) TPC 10. Positive PSRR vs. Frequency, ± 5 V

100

90
20mV 1s
80
100
90 70
G = +1000
PSRR – dB

60

50
G = +100
40
10
0% 30
G = +5
20

10

0
10 100 1k 10k 100k
FREQUENCY – Hz

TPC 8. 0.1 Hz to 10 Hz RTI Voltage Noise (400 nV/DIV), TPC 11. Negative PSRR vs. Frequency, ± 5 V
G = +5

120

110
2V 1s
100
100 G = +1000
90 90
PSRR – dB

80 G = +100

70

60 G = +5
10
0% 50

40

30

20
10 100 1k 10k 100k
FREQUENCY – Hz

TPC 9. 0.1 Hz to 10 Hz RTI Voltage Noise (200 nV/DIV), TPC 12. Positive PSRR vs. Frequency (VS = 5 V, 0 V)
G = +1000

–6– REV. B
 AD627
10 400

300

SETTLING TIME – ␮s
SETTLING TIME – ms

1 200

100

0.1 0
5 10 100 1k 0 ⴞ2 ⴞ4 ⴞ6 ⴞ8 ⴞ10
GAIN – V/V OUTPUT PULSE – Volts

TPC 13. Settling Time to 0.01% vs. Gain for a 5 V Step at TPC 16. Settling Time to 0.01% vs. Output Swing,
Output, RL = 20 kΩ, CL = 100 pF, VS = ± 5 V G = +5, RL = 20 kΩ, CL = 100 pF

TPC 14. Large Signal Pulse Response and Settling TPC 17. Large Signal Pulse Response and Settling
Time, G = –5, RL = 20 kΩ, CL = 100 pF (1.5 mV = 0.01%) Time, G = –100, RL = 20 kΩ, CL = 100 pF (100 µ V = 0.01%)

TPC 15. Large Signal Pulse Response and Settling TPC 18. Large Signal Pulse Response and Settling
Time, G = –10, RL = 20 kΩ, CL = 100 pF (1.0 mV = 0.01%) Time, G = –1000, RL = 20 kΩ, CL = 100 pF (10 µ V = 0.01%)

REV. B –7–
AD627
120
110

100
90
G = +1000
80
CMRR – dB

70
G = +100
60
50
G = +5
40
30
20
10
0
1 10 100 1k 10k 100k
FREQUENCY – Hz

TPC 19. CMRR vs. Frequency, ±5 VS, (CMV = 200 mV p-p) TPC 22. Small Signal Pulse Response, G = +10,
RL = 20 kΩ, CL = 50 pF

70
G = +1000
60

50
G = +100
40

30
GAIN – dB

G = +10
20

10 G = +5

–10

–20

–30
100 1k 10k 100k
FREQUENCY – Hz

TPC 20. Gain vs. Frequency (VS = 5 V, 0 V), VREF = 2.5 V TPC 23. Small Signal Pulse Response, G = +100,
RL = 20 kΩ, CL = 50 pF

TPC 21. Small Signal Pulse Response, G = +5, TPC 24. Small Signal Pulse Response,
RL = 20 kΩ, CL = 50 pF G = +1000, RL = 20 kΩ, CL = 50 pF

–8– REV. B
 AD627
20␮V/DIV 200␮V/DIV

VOUT VOUT
0.5V/DIV 3V/DIV

TPC 25. Gain Nonlinearity, VS = ± 2.5 V, G = +5 TPC 28. Gain Nonlinearity, VS = ± 15 V, G = +100
(4 ppm/DIV) (7 ppm/DIV)

40␮V/DIV 200␮V/DIV

VOUT VOUT
0.5V/DIV 3V/DIV

TPC 26. Gain Nonlinearity, VS = ± 2.5 V, G = +100 TPC 29. Gain Nonlinearity, VS = ±15 V, G = +5 (7 ppm/DIV)
(8 ppm/DIV)

40␮V/DIV 200␮V/DIV

VOUT VOUT
3V/DIV 3V/DIV

TPC 27. Gain Nonlinearity, VS = ± 15 V, G = +5 TPC 30. Gain Nonlinearity, VS = ±15 V, G = +100 (7 ppm/DIV)
(1.5 ppm/DIV)

REV. B –9–
AD627
THEORY OF OPERATION Laser trims are performed on R1 through R4 to ensure that
The AD627 is a true “instrumentation amplifier” built using their values are as close as possible to the absolute values in the
two feedback loops. Its general properties are similar to those of gain equation. This ensures low gain error and high common-
the classic “two op amp” instrumentation amplifier configuration, mode rejection at all practical gains.
and can be regarded as such, but internally the details are some-
what different. The AD627 uses a modified “current feedback” USING THE AD627
scheme which, coupled with interstage feedforward frequency Basic Connections
compensation, results in a much better CMRR (Common- Figure 3 shows the basic connection circuit for the AD627.
Mode Rejection Ratio) at frequencies above dc (notably the line The +VS and –VS terminals are connected to the power supply.
frequency of 50 Hz–60 Hz) than might otherwise be expected of The supply can either be bipolar (VS = ± 1.1 V to ± 18 V) or
a low power instrumentation amplifier. single supply (–VS = 0 V, +VS = +2.2 V to +36 V). The power
Referring to the diagram, (Figure 2), A1 completes a feedback supplies should be capacitively decoupled close to the devices
loop which, in conjunction with V1 and R5, forces a constant power pins. For best results, use surface mount 0.1 µF ceramic
collector current in Q1. Assume that the gain-setting resistor chip capacitors.
(RG) is not present for the moment. Resistors R2 and R1 com- The input voltage, which can be either single ended (tie either
plete the loop and force the output of A1 to be equal to the –IN or +IN to ground) or differential. The difference between
voltage on the inverting terminal with a gain of (almost exactly) the voltage on the inverting and noninverting pins is amplified
1.25. A nearly identical feedback loop completed by A2 forces a by the programmed gain. The programmed gain is set by the
current in Q2 which is substantially identical to that in Q1, and gain resistor (see below). The output signal appears as the volt-
A2 also provides the output voltage. When both loops are bal- age difference between the output pin and the externally applied
anced, the gain from the noninverting terminal to VOUT is equal voltage on the REF pin (see below).
to 5, whereas the gain from the output of A1 to VOUT is equal to Setting the Gain
–4. The inverting terminal gain of A1, (1.25) times the gain The AD627s gain is resistor programmed by RG, or more pre-
of A2, (–4) makes the gain from the inverting and noninverting cisely, by whatever impedance appears between Pins 1 and 8.
terminals equal. The gain is set according to the equation:

EXTERNAL GAIN RESISTOR

Gain = 5 + (200 kΩ/RG)
R1 RG R4 or
100k⍀ 100k⍀
REF RG = 200 kΩ/(Gain – 5)
R2 R3
+VS
+VS 25k⍀ 25k⍀
It follows that the minimum achievable gain is 5 (for RG = ∞).
2k⍀
2k⍀ Q2 +IN With an internal gain accuracy of between 0.05% and 0.7%
–IN Q1
depending on gain and grade, a 0.1% external gain resistor
–VS
–VS would seem appropriate to prevent significant degradation of the
A1
overall gain error. However, 0.1% resistors are not available in a
A2 OUTPUT
wide range of values and are quite expensive. Table I shows
R5 V1 R6 recommended gain resistor values using 1% resistors. For all
200k⍀ 200k⍀ gains, the size of the gain resistor is conservatively chosen as the
–VS
closest value from the standard resistor table that is higher than
Figure 2. Simplified Schematic the ideal value. This results in a gain that is always slightly less
than the desired gain. This prevents clipping of the signal at the
The differential mode gain is equal to 1 + R4/R3, nominally five
output due to resistor tolerance.
and is factory trimmed to 0.01% final accuracy. Adding an external
gain setting resistor (RG) increases the gain by an amount equal The internal resistors on the AD627 have a negative temperature
to (R4 + R1)/RG. The output voltage of the AD627 is given by the coefficient of –75 ppm/°C max for gains > 5. Using a gain resistor
following equation. that also has a negative temperature coefficient of –75 ppm/°C or
less will tend to reduce the overall circuit’s gain drift.
VOUT = [VIN(+) – VIN(–)] × (5 + 200 kΩ/RG) + VREF

+VS +VS
+1.1V TO +18V +2.2V TO +36V
0.1␮F 0.1␮F
+IN +IN

RG RG
VIN RG OUTPUT VOUT VIN RG OUTPUT VOUT
RG REF RG REF
–IN REF (INPUT) –IN REF (INPUT)
0.1␮F

–1.1V TO –18V
–VS GAIN = 5 + (200k⍀/RG)

Figure 3. Basic Connections for Single and Dual Supplies

–10– REV. B
 AD627
V+

+IN EXTERNAL GAIN RESISTOR

VDIFF
2 100k⍀ RG 100k⍀
25k⍀ 25k⍀
REF
VCM +VS +VS
VDIFF
2 2k⍀ +IN
–IN –IN 2k⍀
Q2
Q1
V–
–VS
–VS A1
A2 OUTPUT

200k⍀ 0.1V VA 200k⍀

–VS

Figure 4. Amplifying Differential Signals with a Common-Mode Component

Table I. Recommended Values of Gain Resistors Input Range Limitations in Single Supply Applications
In general, the maximum achievable gain is determined by the
Desired 1% Std Table Resulting available output signal range. However, in single supply applica-
Gain Value of RG, ⍀ Gain tions where the input common-mode voltage is close to or equal
5 ∞ 5.00 to zero, some limitations on the gain can be set. While the Input,
6 200 k 6.00 Output and Reference Pins have ranges that are nominally defined
7 100 k 7.00 on the specification pages, there is a mutual interdependence
8 68.1 k 7.94 between the voltage ranges on these pins. Figure 4 shows the
9 51.1 k 8.91 simplified schematic of the AD627, driven by a differential
10 40.2 k 9.98 voltage VDIFF which has a common-mode component, VCM. The
15 20 k 15.00 voltage on the output of op amp A1 is a function of VDIFF, VCM,
20 13.7 k 19.60 the voltage on the REF pin and the programmed gain. This
25 10 k 25.00 voltage is given by the equation:
30 8.06 k 29.81
40 5.76 k 39.72 VA1 = 1.25 (VCM + 0.5 V) – 0.25 VREF – VDIFF (25 kΩ/RG – 0.625)
50 4.53 k 49.15 We can also express the voltage on A1 as a function of the actual
60 3.65 k 59.79 voltages on the –IN and +IN pins (V– and V+)
70 3.09 k 69.72 VA1 = 1.25 (V– + 0.5 V) – 0.25 VREF – (V+ – V–) 25 kΩ/RG
80 2.67 k 79.91
90 2.37 k 89.39 A1’s output is capable of swinging to within 50 mV of the nega-
100 2.1 k 100.24 tive rail and to within 200 mV of the positive rail. From either of
200 1.05 k 195.48 the above equations, it is clear that an increasing VREF, (while it
500 412 490.44 acts as a positive offset at the output of the AD627), tends to
1000 205 980.61 decrease the voltage on A1. Figures 5 and 6 show the maximum
voltages that can be applied to the REF pin, for a gain of five for
Reference Terminal both the single and dual supply cases. Raising the input com-
The reference terminal potential defines the zero output voltage mon-mode voltage will increase the voltage on the output of A1.
and is especially useful when the load does not share a precise However, in single supply applications where the common-
ground with the rest of the system. It provides a direct means of mode voltage is low, a differential input voltage or a voltage on
injecting a precise offset to the output. The reference terminal is REF that is too high can drive the output of A1 into the ground
also useful when bipolar signals are being amplified as it can be rail. Some low side headroom is added by virtue of both inputs
used to provide a virtual ground voltage. being shifted upwards by about 0.5 V (i.e., by the VBE of Q1
Since the AD627 output voltage is developed with respect to the and Q2). The above equations can be used to check that the
potential on the reference terminal, it can solve many grounding voltage on amplifier A1 is within its operating range.
problems by simply tying the REF pin to the appropriate “local Table II gives values for the maximum gains for various single
ground.” The REF pin should however be tied to a low imped- supply input conditions. The resulting output swings shown
ance point for optimal CMR. refer to 0 V. The voltages on the REF pins has been set to either
Table II. Maximum Gain for Low Common-Mode Single Supply Applications

REF Supply RG (1% Resulting Output Swing

VIN Pin Voltage Tolerance) Max Gain WRT 0 V
± 100 mV, VCM = 0 V 2V 5 V to 15 V 28.7 kΩ 12.0 0.8 V to 3.2 V
± 50 mV, VCM = 0 V 2V 5 V to 15 V 10.7 kΩ 23.7 0.8 V to 3.2 V
± 10 mV, VCM = 0 V 2V 5 V to 15 V 1.74 kΩ 119.9 0.8 V to 3.2 V
V– = 0 V, V+ = 0 V to 1 V 1V 10 V to 15 V 78.7 kΩ 7.5 1 V to 8.5 V
V– = 0 V, V+ = 0 mV to 100 mV 1V 5 V to 15 V 7.87 kΩ 31 1 V to 4.1 V
V– = 0 V, V+ = 0 mV to 10 mV 1V 5 V to 15 V 7.87 Ω 259.1 1 V to 3.6 V

REV. B –11–
AD627
2 V or 1 V to maximize the available gain and output swing. INPUT AND OUTPUT OFFSET ERRORS
Note that in most cases, there is no advantage to increasing the The low errors of the AD627 are attributed to two sources, input
single supply to greater than 5 V (the exception being an input and output errors. The output error is divided by G when
range of 0 V to 1 V). referred to the input. In practice, the input errors dominate at
high gains and the output errors dominate at low gains. The
5
total offset error for a given gain is calculated as:
4
Total Error RTI = Input Error + (Output Error/Gain)
3 Total Error RTO = (Input Error × G) + Output Error
2
MAXIMUM VREF
RTI offset errors and noise voltages for different gains are
shown below in Table III.
VREF – Volts

0
Table III. RTI Error Sources
–1
MINIMUM VREF
–2
Max Total Max Total
RTI Offset Error RTI Offset Drift Total RTI Noise
–3
␮V ␮V ␮V/ⴗC ␮V/ⴗC nV/√Hz
–4
Gain AD627A AD627B AD627A AD627B AD627A & AD627B
–5
–6 –5 –4 –3 –2 –1 0 1 2 3 4 +5 450 250 5 3 95
VIN(–) – Volts +10 350 200 4 2 66
Figure 5. Reference Input Voltage vs. Negative Input Volt- +20 300 175 3.5 1.5 56
age, VS = ± 5 V, G = +5 +50 270 160 3.2 1.2 53
+100 270 155 3.1 1.1 52
5 +500 252 151 3 1 52
+1000 251 151 3 1 52
MAXIMUM VREF
4 Make vs. Buy: A Typical Application Error Budget
The example in Figure 8 serves as a good comparison between
the errors associated with an integrated and a discrete in amp
VREF – Volts

3
implementation. A ± 100 mV signal from a resistive bridge
(common-mode voltage = 2.5 V) is to be amplified. This example
2 compares the resulting errors from a discrete two op amp in
amp and from the AD627. The discrete implementation uses a
MINIMUM VREF four-resistor precision network (1% match, 50 ppm/°C tracking).
1
The errors associated with each implementation are detailed in
Table IV and show the integrated in amp to be more precise,
0 both at ambient and over temperature. It should be noted that
–0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
VIN(–) – Volts
the discrete implementation is also more expensive. This is pri-
marily due to the relatively high cost of the low drift precision
Figure 6. Reference Input Voltage vs. Negative Input Volt- resistor network.
age, VS = 5 V, G = +5
Note, the input offset current of the discrete in amp implemen-
Output Buffering tation is the difference in the bias currents of the two op amps,
The AD627 is designed to drive loads of 20 kΩ or greater but not the offset currents of the individual op amps. Also, while the
can deliver up to 20 mA to heavier loads at lower output voltage values of the resistor network are chosen so that the inverting
swings (see TPC 6). If more than 20 mA of output current is and noninverting inputs of each op amp see the same impedance
required at the output, the AD627’s output should be buffered (about 350 Ω), the offset current of each op amp will add an
with a precision op amp such as the OP113 as shown in Figure 7 additional error which must be characterized.
(shown for the single supply case). This op amp can swing from
0 V to 4 V on its output while driving a load as small as 600 Ω. Errors Due to AC CMRR
In Table IV, the error due to common-mode rejection is the
+VS
error that results from the common-mode voltage from the
0.1␮F
bridge 2.5 V. The ac error due to nonideal common-mode
0.1␮F
rejection cannot be calculated without knowing the size of the ac
VIN RG AD627 common-mode voltage (usually interference from 50 Hz/60 Hz
REF OP113 VOUT mains frequencies).
0.1␮F 0.1␮F A mismatch of 0.1% between the four gain setting resistors will
determine the low frequency CMRR of a two op amp in amp.
–VS –VS The plot in Figure 8 shows the practical results, at ambient
temperature, of resistor mismatch. The CMRR of the circuit in
Figure 7. Output Buffering Figure 9 (Gain = +11) was measured using four resistors which

–12– REV. B
 AD627
5V 5V 5V

350⍀ 350⍀ LT1078IS8

LT1078IS8 1/2 VOUT

RG
350⍀ 350⍀ 40.2k⍀
ⴞ100mV AD627A VOUT 1/2
1%
+10ppm/ C
2.5V

3.15k⍀* 350⍀* 350⍀* 3.15k⍀*

2.5V
AD627A GAIN = 9.98 (5+(200k⍀/RG)) "HOMEBREW" IN AMP, G = 10
*1% REGISTER MATCH, 50ppm/ⴗC TRACKING

Figure 8. Make vs. Buy

Table IV. Make vs. Buy Error Budget

“Homebrew” Total Error Total Error

Error Source AD627 Circuit Calculation Circuit Calculation AD627-ppm Homebrew–ppm
ABSOLUTE ACCURACY at TA = 25°C
Total RTI Offset Voltage, mV (250 µV + (1000 µV/10))/100 mV (180 µV × 2)/100 mV 3500 3600
Input Offset Current, nA 1 nA × 350 Ω/100 mV 20 nA × 350 Ω/100 mV 3.5 70
Internal Offset Current (Homebrew Only) Not Applicable 0.7 nA × 350 Ω/100 mV 2.45
CMRR, dB 77 dB→141 ppm × 2.5 V/100 mV (1% Match × 2.5 V)/10/100 mV 3531 25000
Gain 0.35% + 0.1% 1% Match 13500 10000

Total Absolute Error 20535 38672

DRIFT TO 85°C
Gain Drift, ppm/°C (–75 + 10) ppm/°C × 60°C 50 ppm/°C × 60°C 3900 3000
Total RTI Offset Voltage, mV/°C (3.0 µV/°C + (10 µV/°C/10)) (2 × 3.5 µV/°C × 60°C)/100 mV
× 60°C/100 mV 2600 4200
Input Offset Current, pA/°C (16 pA/°C × 350 Ω × 60°C)/100 mV (33 pA/°C × 350 Ω × 60°C)/100 mV 3.5 7
Total Drift Error 6504 7207

Grand Total Error 27039 45879

had a mismatch of almost exactly 0.1% (R1 = 9999.5 Ω, R2 = 120

999.76 Ω, R3 = 1000.2 Ω, R4 = 9997.7 Ω). As expected the
110
CMRR at dc was measured at about 84 dB (calculated value
is 85 dB). However, as the frequency increases, the CMRR 100

quickly degrades. For example, a 200 mV peak-peak harmonic 90

of the mains frequency at 180 Hz would result in an output
CMRR – dB

80
voltage of about 800 µV. To put this in context, a 12-bit data
70
acquisition system with an input range of 0 V to 2.5 V, has an
LSB weighting of 610 µV. 60

By contrast, the AD627 uses precision laser trimming of internal 50

resistors along with patented CMR trimming to yield a higher 40
dc CMRR and a wider bandwidth over which the CMRR is flat
30
(see TPC 19).
20
1 10 100 1k 10k 100k
+5V FREQUENCY – Hz

A2
VIN–
1/2
Figure 10. CMRR Over Frequency of Discrete In Amp in
A1 OP296 VOUT Figure 9
VIN+
1/2
OP296 Ground Returns for Input Bias Currents
Input bias currents are those dc currents that must flow in
–5V
order to bias the input transistors of an amplifier. These are
R1 R2 R3 R4 usually transistor base currents. When amplifying “floating”
9999.5⍀ 999.76⍀ 1000.2⍀ 9997.7⍀
input sources such as transformers, or ac-coupled sources,
there must be a direct dc path into each input in order that the
Figure 9. 0.1% Resistor Mismatch Example bias current can flow. Figure 11 shows how a bias current
path can be provided for the case of transformer coupling,
capacitive ac-coupling and for a thermocouple application.

REV. B –13–
AD627
In dc-coupled resistive bridge applications, providing this path Layout and Grounding
is generally not necessary as the bias current simply flows from The use of ground planes is recommended to minimize the
the bridge supply, through the bridge and into the amplifier. impedance of ground returns (and hence the size of dc errors).
However, if the impedance that the two inputs see are large, and In order to isolate low level analog signals from a noisy digital
differ by a large amount (>10 kΩ), the offset current of the environment, many data-acquisition components have separate
input stage will cause dc errors compatible with the input offset analog and digital ground returns (Figure 12). All ground pins
voltage of the amplifier. from mixed signal components such as analog-to-digital converters
should be returned through the “high quality” analog ground
+VS plane. Digital ground lines of mixed signal components should
–INPUT
also be returned through the analog ground plane. This may
seem to break the rule of keeping analog and digital grounds
RG AD627 VOUT separate. However, in general, there is also a requirement to keep
+INPUT the voltage difference between digital and analog grounds on
REFERENCE
a converter as small as possible (typically <0.3 V). The increased
LOAD
–VS noise, caused by the converter’s digital return currents flowing
TO POWER
SUPPLY through the analog ground plane, will generally be negligible.
GROUND
Maximum isolation between analog and digital is achieved by
Figure 11a. Ground Returns for Bias Currents with Trans- connecting the ground planes back at the supplies.
former Coupled Inputs If there is only a single power supply available, it must be shared
by both digital and analog circuitry. Figure 13 shows the how
+VS
to minimize interference between the digital and analog cir-
–INPUT cuitry. As in the previous case, separate analog and digital
ground planes should be used (reasonably thick traces can be
RG
used as an alternative to a digital ground plane). These ground
AD627 VOUT
planes should be connected at the power supply’s ground pin.
+INPUT
REFERENCE Separate traces (or power planes) should be run from the power
LOAD supply to the supply pins of the digital and analog circuits. Ideally
–VS each device should have its own power supply trace, but these
TO POWER
SUPPLY
GROUND can be shared by a number of devices as long as a single trace is
not used to route current to both digital and analog circuitry.
Figure 11b. Ground Returns for Bias Currents with Ther-
mocouple Inputs INPUT PROTECTION
As shown in the simplified schematic (Figure 2), both the inverting
and noninverting inputs are clamped to the positive and nega-
+VS
–INPUT
tive supplies by ESD diodes. In addition to this a 2 kΩ series
resistor on each input provides current limiting in the event of
an overvoltage. These ESD diodes can tolerate a maximum
RG AD627 VOUT
continuous current of 10 mA. So an overvoltage, (that is the
+INPUT
REFERENCE amount by which input voltage exceeds the supply voltage), of
LOAD ± 20 V can be tolerated. This is true for all gains, and for power
100k⍀ 100k⍀
–VS
TO POWER on and off. This last case is particularly important since the
SUPPLY
GROUND signal source and amplifier may be powered separately.
Figure 11c. Ground Returns for Bias Currents with AC If the overvoltage is expected to exceed 20 V, additional external
Coupled Inputs series resistors current limiting resistors should be used to keep
the diode current to below 10 mA.

ANALOG POWER SUPPLY DIGITAL POWER SUPPLY

+5V –5V GND GND +5V

0.1␮F 0.1␮F 0.1␮F 0.1␮F

AD627 VIN1 VDD AGND DGND 12 AGND VDD

VIN2 ADC AD7892-2 ␮PROCESSOR

Figure 12. Optimal Grounding Practice for a Bipolar Supply Environment with Separate Analog and Digital Supplies

–14– REV. B
 AD627
POWER SUPPLY
5V GND

0.1␮F
0.1␮F
0.1␮F

VDD AGND DGND 12 VDD DGND

AD627 VIN
ADC AD7892-2 ␮PROCESSOR

Figure 13. Optimal Ground Practice in a Single Supply Environment

RF INTERFERENCE of this circuit may be increased by reducing the value of resistors

All instrumentation amplifiers can rectify high frequency out-of- R1 and R2. The performance is similar to that using 20 kΩ
band signals. Once rectified, these signals appear as dc offset resistors, except that the circuitry preceding the in amp must
errors at the output. The circuit of Figure 14 provides good RFI drive a lower impedance load.
suppression without reducing performance within the in amp’s
The circuit of Figure 14 should be built using a PC board with a
passband. Resistor R1 and capacitor C1 (and likewise, R2 and
ground plane on both sides. All component leads should be as
C2) form a low pass RC filter that has a –3 dB BW equal to:
short as possible. Resistors R1 and R2 can be common 1% metal
F = 1/(2 π R1C1). Using the component values shown, this
film units but capacitors C1 and C2 need to be ± 5% tolerance
filter has a –3 dB bandwidth of approximately 8 kHz. Resistors
devices to avoid degrading the circuit’s common-mode rejec-
R1 and R2 were selected to be large enough to isolate the circuit’s
tion. Either the traditional 5% silver mica units or Panasonic
input from the capacitors, but not large enough to significantly
± 2% PPS film capacitors are recommended.
increase the circuit’s noise. To preserve common-mode rejec-
tion in the amplifier’s pass band, capacitors C1 and C2 need to
APPLICATIONS CIRCUITS
be 5% mica units, or low cost 20% units can be tested and
A Classic Bridge Circuit
“binned” to provide closely matched devices.
Figure 15 shows the AD627 configured to amplify the signal
+VS
from a classic resistive bridge. This circuit will work in either
dual or single supply mode. Typically the bridge will be excited
C1 0.33␮F 0.01␮F
R1 1000pF
by the same voltage as is used to power the in amp. Connecting
20k⍀ 5% the bottom of the bridge to the negative supply of the in amp (usu-
1%
+IN ally either 0, –5 V, –12 V or –15 V), sets up an input common-
R2 C3 RG AD627 VOUT
mode voltage that is optimally located midway between the
20k⍀ 0.022␮F
1%
supply voltages. It is also appropriate to set the voltage on the
REFERENCE
–IN REF pin to midway between the supplies, especially if the input
C2
1000pF
0.33␮F 0.01␮F
signal will be bipolar. However the voltage on the REF pin can be
5%
varied to suit the application. A good example of this is when
LOCATE C1–C3 AS CLOSE TO –VS the REF pin is tied to the VREF pin of an Analog-to-Digital
THE INPUT PINS AS POSSIBLE Converter (ADC) whose input range is (VREF ± VIN). With an
Figure 14. Circuit to Attenuate RF Interference available output swing on the AD627 of (–VS + 100 mV) to
(+VS – 150 mV) the maximum programmable gain is simply
Capacitor C3 is needed to maintain common-mode rejection at this output range divided by the input range.
the low frequencies. R1/R2 and C1/C2 form a bridge circuit
whose output appears across the in amp’s input pins. Any mis- +VS
match between C1 and C2 will unbalance the bridge and reduce
0.1␮F
common-mode rejection. C3 insures that any RF signals are
common mode (the same on both in amp inputs) and are not
applied differentially. This second low pass network, R1 + R2 VDIFF RG = 200k⍀ AD627 VOUT
and C3, has a –3 dB frequency equal to: 1/(2 π (R1 + R2) (C3)). GAIN-5

Using a C3 value of 0.022 µF as shown, the –3 dB signal BW of 0.1␮F

VREF

this circuit is approximately 200 Hz. The typical dc offset shift

over frequency will be less than 1 mV and the circuit’s RF signal –VS
rejection will be better than 57 dB. The 3 dB signal bandwidth
Figure 15. A Classic Bridge Circuit

REV. B –15–
AD627
5V 5V 5V

0.1␮F 0.1␮F

0.1␮F
VREF AVDD DVDD

4–20mA LINE 4–20mA AIN 0–7 AD␮C812

24.9⍀ G = +5 AD627
TRANSDUCER IMPEDANCE MicroConverterTM

C00782a–0–4/01(B)
REF
AGND DGND

MicroConverter is a trademark of Analog Devices, Inc.

Figure 16. A 4 mA-to-20 mA Receiver Circuit

A 4 mA-to-20 mA Single Supply Receiver Over a temperature range from –200°C to +200°C, the J-type
Figure 16 shows how a signal from a 4 mA-to-20 mA transducer thermocouple delivers a voltage ranging from –7.890 mV to
can be interfaced to the ADµC812, a 12-bit ADC with an embed- 10.777 mV. A programmed gain on the AD627 of 100 (RG =
ded microcontroller. The signal from a 4 mA-to-20 mA transducer 2.1 kΩ) and a voltage on the AD627 REF pin of 2 V, results in
is single ended. This initially suggests the need for a simple shunt the AD627’s output voltage ranging from 1.110 V to 3.077 V
resistor, to convert the current to a voltage at the high imped- relative to ground. For a different input range or different volt-
ance analog input of the converter. However, any line resistance age on the REF pin, it is important to check that the voltage on
in the return path (to the transducer) will add a current depen- internal node A1 (see Figure 4) is not driven below ground).
dent offset error. So the current must be sensed differentially. This can be checked using the equations in the section entitled
Input Range Limitations in Single Supply Applications.
In this example, a 24.9 Ω shunt resistor generates a maximum
differential input voltage to the AD627 of between 100 mV (for +5V
4 mA in) and 500 mV (for 20 mA in). With no gain resistor 0.1␮F
present, the AD627 amplifies the 500 mV input voltage by a
factor of 5, to 2.5 V, the full-scale input voltage of the ADC.
J-TYPE RG
The zero current of 4 mA corresponds to a code of 819 and the THERMOCOUPLE 2.1k⍀ AD627 VOUT
LSB size is 4.9 mA. REF
2V
A Thermocouple Amplifier
Because the common-mode input range of the AD627 extends
0.1 V below ground, it is possible to measure small differential
Figure 17. Amplifying Bipolar Signals with Low Common-
signals which have low, or no, common-mode component. Fig-
Mode Voltage
ure 17 shows a thermocouple application where one side of the
J-type thermocouple is grounded.

OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

8-Lead Plastic DIP 8-Lead SOIC

(N-8) (SO-8)
0.430 (10.92) 0.1968 (5.00)
0.348 (8.84) 0.1890 (4.80)

8 5
0.280 (7.11) 8 5
0.1574 (4.00) 0.2440 (6.20)
PIN 1 0.240 (6.10)
1 4 0.1497 (3.80) 1 4 0.2284 (5.80)
0.325 (8.25)

PRINTED IN U.S.A.
0.300 (7.62)
0.060 (1.52)
PIN 1
0.015 (0.38) 0.195 (4.95)
0.210 (5.33) 0.0500 (1.27) 0.0196 (0.50)
0.115 (2.93) BSC ⴛ 45ⴗ
MAX 0.130 0.0099 (0.25)
0.160 (4.06) (3.30) 0.0688 (1.75)
MIN 0.0098 (0.25) 0.0532 (1.35)
0.115 (2.93) 0.0040 (0.10)
0.015 (0.381) 8ⴗ
0.022 (0.558) 0.100 0.070 (1.77) SEATING
0.0192 (0.49) 0.0500 (1.27)
PLANE 0.008 (0.204) SEATING 0.0098 (0.25) 0ⴗ
0.014 (0.356) (2.54) 0.045 (1.15) PLANE 0.0138 (0.35) 0.0160 (0.41)
BSC 0.0075 (0.19)

AD627–Revision History
Location Page
Data Sheet changed from REV. A to REV. B.
Changes to Figure 4 and Table I, Resulting Gain column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Change to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
–16– REV. B