DLCO
DLCO
DLCO
REFERENCES:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian, “Computer Organization and Embedded
Systems”, Sixth Edition, Tata McGraw-Hill, 2012.
2. William Stallings, “Computer Organization and Architecture – Designing for Performance”, Tenth Edition, Pearson
Education, 2016.
3. M. Morris Mano, “Digital Logic and Computer Design”, Pearson Education, 2016.
COURSE OUTCOMES
202.3 State the fundamentals of computer systems and analyze the execution of an instruction
S. Knowledge Course
Course Content
No. Level Outcomes
1. R/U Combinational Circuits 202.1
2. R/U Karnaugh Map
3. R/U/An Analysis and Design Procedures
4. R/U Binary Adder, Subtractor
5. R/U/An Decimal Adder
6. R/U Magnitude Comparator
7. R/U Decoder – Encoder
8. R/U/An/Ap Multiplexers - Demultiplexers
S. Knowledge Course
Course Content
No. Level Outcomes
1. R/U Introduction to Sequential Circuits 202.2
2. R/U/An/Ap Flip-Flops
3. R/U/An/Ap Operation and excitation tables
4. R/U/An/Ap Triggering of FF
5. R/U/An/Ap Analysis and design of clocked sequential circuits
6. R/U/An/Ap Design – Moore/Mealy models
7. R/U/An/Ap State minimization,
8. R/U/An/Ap State assignment
9. R/U/An/Ap Circuit implementation
10. R/U Registers
11. R/U/An/Ap Counters.
S. Knowledge Course
Course Content
No. Level Outcomes
12. R/U Functional Units of a Digital Computer 202.3
13. R/U Von Neumann Architecture
14. R/U/An/Ap Operation and Operands of Computer Hardware Instruction
15. R/U/An/Ap Instruction Set Architecture (ISA)
16. R/U Memory Location, Address and Operation
17. R/U/An Instruction and Instruction Sequencing
18. R/U/An/Ap Addressing Modes, Encoding of Machine Instruction
19. R/U Interaction between Assembly and High Level Language.
S. Knowledge Course
Course Content
No. Level Outcomes
20. R/U/An/Ap Instruction Execution 202.4
21. R/U/An/Ap/E Building a Data Path
22. R/U/An/Ap Designing a Control Unit
23. R/U/An/Ap Hardwired Control
24. R/U/An/Ap Microprogrammed Control
25. R/U/An/Ap/E/C Pipelining
26. R/U/An/Ap Data Hazard
27. R/U/An/Ap Control Hazards
S. Knowledge Course
Course Content
No. Level Outcomes
28. R/U Memory Concepts and Hierarchy 202.5
29. R/U Memory Management
30. R/U Cache Memories
31. R/U/An/Ap Mapping and Replacement Techniques
32. R/U Virtual Memory
33. R/U DMA
34. R/U I/O – Accessing I/O
35. R/U Parallel and Serial Interface
36. R/U/An/Ap Interrupt I/O
37. R/U Interconnection Standards: USB, SATA
1 With reference to a JK flip-flop, what is racing? (Nov/Dec ‘14) (May/June ‘14) BL1
2 Give the truth table for J-K flip-flop BL1
3 Draw the diagram of T flip flop and discuss its working. (Nov/Dec ‘15) BL1
4 State the excitation table of JK Flip Flop. (May/June ‘16) BL1
5 Mention the uses of shift registers. BL4
6 What are Mealy and Moor machines? (or) Distinguish Moore and Mealy circuit. (Nov/Dec 14) BL1
7 Why D FF is known as Delay FF? BL1
8 Draw the logic diagram and write the function table of D Latch. (Apr./May.’19) BL3
9 Show the T- Flip flop implementation from SR flip flop
10 Define the hold time requirement of a clocked FF? BL1
11 What is meant by triggering of Flip flop? BL1
12 Give the truth table of T flip flop. BL1
13 Name the two problems that may arise in ripple counters or asynchronous counters. BL1
14 When is a counter said to suffer from lockout? BL1
15 Mention why the decoding gates for an asynchronous counter may have glitches on their BL1
outputs?
16 Draw a Mod 6 counter using feedback technique. BL3
2 Design a synchronous counter that counts the sequence 000,001,010,011,100,101,110,111,000 using D BL1
flip flop. (May/June ‘14)
3 Implement T flipflop and JK flipflop using D flipflop. (May/June ‘14) (Apr/May ‘17) BL4
4 Design a BCD counter using JK flip-flops. (or) Design a MOD-10 Synchronous counter using JK flip- BL6
flops. Write execution table and state table. (Nov/Dec ‘14)
5 (i) A sequential circuit with two D flip-flops A and B, one input x and one output z is specified by the BL5
following next-state and output equations: (April/May ‘15)
A(t+1)= A′+B, B(t+1)=B′x, z=A+B′
(1) Draw the logic diagram of the circuit
(2) Draw the state table
(3) Draw the state diagram of the circuit
(ii) Explain the difference between a state table, characteristics table and excitation table.
6 Consider the design of 4-bit BCD counter that counts in the following way: (April/May ‘15) BL6
0000,0010,0011,….,1001 and back to 0000
(i) Draw the state diagram
(ii) List the next state table
Draw the logic diagram of the circuit
7 Design a binary counter using T flip flops to count in the following sequences: (May/June ‘16) BL6
(i) 000, 001, 010, 011, 100, 101, 111, 000
(ii) 000, 100, 111, 010, 011, 000
8 (i) Implement JK filp-flop using D flip flop. (Nov/ Dec ‘16) BL4
(ii) How race condition can be avoided in a flip flop.
9 Explain the operation of JK FF, SR FF, T-FF and D-FF with a neat diagram. Also discuss their BL5
characteristic equation and excitation table. (Nov/ Dec ‘17)
11 Draw logic circuit diagram for 3-bit synchronous up-down counter with clear input, start input and BL3
‘done’ output. The counter should produce ‘done’ output after completion of counter in either
direction.
12 Design a sequential circuit using RS flip flop for the state table with minimum flip flop. BL6
Present
Next State Output
State
x=0 x=1 x=0 x=1
A A B 0 0
B C D 0 0
C A D 0 0
D E F 0 1
E A F 0 1
F G F 0 1
G A F 0 1
13 What is the difference serial and parallel transfer? Explain how to convert parallel data to serial and BL1
serial data to parallel. What type of register is needed?
14 BL6
Design and implementation of SR Flip-Flop using NOR gate. (Nov/ Dec ‘18)
15 BL2
Explain in detail about 4 bit Johnson Counter. (Nov/ Dec ‘18)
16 BL6
Design Synchronous Mod 10 counter using D flipflop. (Apr/May ‘18)
17 (i) Describe the operations of R-S flip flop with a neat sketch. (Apr./May.’19) BL6
(ii) Design a sequential circuit with two D flip- flops A and B and one input X. When X=0, the state
of the circuit remains the same. When X=1, the circuit goes through the state transitions from 00 to10
to 11 to 01, back to 00 and then repeats.
18 (i)Construct a clocked Master Slave J.-K Flip flop and explain. (Apr./May.’19) BL3
(ii) A sequential circuit with two D flip-flops A and B, two inputs X and Y, and one output Z is
specified by the following input equation
A(t+1)=x'y+xA,
B(t+1)=x'B+xA, z=B
Draw the logic diagram of the circuit. Derive the state table and state diagram and state whether it is a
Mealy or a Moore machine.
19 Design a 3-bit binary counter using T flip flops. BL6
(Nov./Dec.’19)
20 (i) What are registers? Construct a 4-bit register using D flip-flops and explain the operations on the BL1
register. (Nov./Dec.’19)
(ii) With diagram explain how two binary numbers are added serially using shift registers:
21 A sequential circuit with two Dflip flops A and B, two inputs x and y; and one output z is specified by BL3
the following next-state and output equations:
A(t+1)=xy'+xB,
B(t+1)=xA+xB', z=A (Nov./Dec.’19)
(i) Draw the logic diagram of the circuit.
(ii) List the state table for the sequential circuit.
(iii) Draw the corresponding state diagram.
22 Explain the operations of a 4-bit bi directional Shift Register. (Apr./May.’19) BL2
UNIT IV PROCESSOR
Instruction Execution – Building a Data Path – Designing a Control Unit – Hardwired Control, Microprogrammed
Control – Pipelining – Data Hazard – Control Hazards.
PART A
1 What is instruction cycle? BL1
BL1- Remembering; BL2- Understanding; BL3- Applying; BL4- Analyzing; BL5- Evaluating; BL6- Creating