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CS4351 Digital Logic and Computer Organization Department of CSE 2024-2025

CS4351 DIGITAL LOGIC AND COMPUTER ORGANIZATION LPTC


300 3
OBJECTIVES:
• To analyze and design combinational circuits.
• To analyze and design sequential circuits
• To understand the basic structure and operation of a digital computer.
• To study the design of data path unit, control unit for processor and to familiarize with the hazards.
• To understand the concept of various memories and I/O interfacing.

UNIT I COMBINATIONAL LOGIC 9


Combinational Circuits – Karnaugh Map - Analysis and Design Procedures – Binary Adder – Subtractor – Decimal
Adder - Magnitude Comparator – Decoder – Encoder – Multiplexers - Demultiplexers
UNIT II SEQUENTIAL LOGIC 9
Introduction to Latches – Difference: Combinational and sequential circuits- Flip-Flops– operation and excitation
tables, Triggering of FF, Analysis and design of clocked sequential circuits - Registers – Counters.
UNIT III COMPUTER FUNDAMENTALS 9
Functional Units of a Digital Computer: Von Neumann Architecture – Operation and Operands of Computer
Hardware Instruction – Instruction Set Architecture (ISA): Memory Location, Address and Operation – Instruction
and Instruction Sequencing – Addressing Modes, Encoding of Machine Instruction – Interaction between
Assembly and High-Level Language.
UNIT IV PROCESSOR 9
Instruction Execution – Building a Data Path – Designing a Control Unit – Hardwired Control, Microprogrammed
Control – Pipelining – Data Hazard – Control Hazards.
UNIT V MEMORY AND I/O 9
Memory Concepts and hierarchy- Memory Management- Cache Memories: Mapping and Replacement Techniques-
Virtual memory- DMA- I/O- Accessing I/O: Parallel and Serial Interface- Interrupt I/O- Interconnection Standards:
USB, SATA.
45 PERIODS
TEXT BOOKS:
1. M. Morris Mano, Michael D. Ciletti, “Digital Design : With an Introduction to the Verilog HDL, VHDL, and
System Verilog”, Sixth Edition, Pearson Education, 2018.
2. David A. Patterson, John L. Hennessy, “Computer Organization and Design, The Hardware/Software Interface”,
Sixth Edition, Morgan Kaufmann/Elsevier, 2020.

REFERENCES:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian, “Computer Organization and Embedded
Systems”, Sixth Edition, Tata McGraw-Hill, 2012.
2. William Stallings, “Computer Organization and Architecture – Designing for Performance”, Tenth Edition, Pearson
Education, 2016.
3. M. Morris Mano, “Digital Logic and Computer Design”, Pearson Education, 2016.

COURSE OUTCOMES

Upon completion of the course, the student should be able to:

202.1 Design various combinational digital circuits using logic gates


202.2 Design sequential circuits and analyze the design procedures

202.3 State the fundamentals of computer systems and analyze the execution of an instruction

202.4 Analyze different types of control design and identify hazards


202.5 Identify the characteristics of various memory systems and I/O communication

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CS4351 Digital Logic and Computer Organization Department of CSE 2024-2025
MAPPING BETWEEN CO AND PO, PSO WITH CORRELATION LEVEL 1/2/3

Course PO PO P P P P P PO PO PO1 PO1 PO1 PSO PSO P PS


Outcomes 1 2 O O O O O 8 9 0 1 2 1 2 S O4
3 4 5 6 7 O
3
202.1 3 3 3 3 2 - - - - - - - 3 3 3 2
202.2 3 3 3 3 2 - - - - - - - 3 3 3 2
202.3 3 3 3 2 2 - - - - - - - 3 3 3 2
202.4 3 3 3 3 2 - - - - - - - 3 3 3 2
202.5 3 3 3 2 2 - - - - - - - 3 3 3 2

RELATION BETWEEN COURSE CONTENT WITH COS


UNIT-I COMBINATIONAL LOGIC

S. Knowledge Course
Course Content
No. Level Outcomes
1. R/U Combinational Circuits 202.1
2. R/U Karnaugh Map
3. R/U/An Analysis and Design Procedures
4. R/U Binary Adder, Subtractor
5. R/U/An Decimal Adder
6. R/U Magnitude Comparator
7. R/U Decoder – Encoder
8. R/U/An/Ap Multiplexers - Demultiplexers

UNIT-II SYNCHRONOUS SEQUENTIAL LOGIC

S. Knowledge Course
Course Content
No. Level Outcomes
1. R/U Introduction to Sequential Circuits 202.2
2. R/U/An/Ap Flip-Flops
3. R/U/An/Ap Operation and excitation tables
4. R/U/An/Ap Triggering of FF
5. R/U/An/Ap Analysis and design of clocked sequential circuits
6. R/U/An/Ap Design – Moore/Mealy models
7. R/U/An/Ap State minimization,
8. R/U/An/Ap State assignment
9. R/U/An/Ap Circuit implementation
10. R/U Registers
11. R/U/An/Ap Counters.

UNIT-III COMPUTER FUNDAMENTALS

S. Knowledge Course
Course Content
No. Level Outcomes
12. R/U Functional Units of a Digital Computer 202.3
13. R/U Von Neumann Architecture
14. R/U/An/Ap Operation and Operands of Computer Hardware Instruction
15. R/U/An/Ap Instruction Set Architecture (ISA)
16. R/U Memory Location, Address and Operation
17. R/U/An Instruction and Instruction Sequencing
18. R/U/An/Ap Addressing Modes, Encoding of Machine Instruction
19. R/U Interaction between Assembly and High Level Language.

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CS4351 Digital Logic and Computer Organization Department of CSE 2024-2025
UNIT-IV PROCESSOR

S. Knowledge Course
Course Content
No. Level Outcomes
20. R/U/An/Ap Instruction Execution 202.4
21. R/U/An/Ap/E Building a Data Path
22. R/U/An/Ap Designing a Control Unit
23. R/U/An/Ap Hardwired Control
24. R/U/An/Ap Microprogrammed Control
25. R/U/An/Ap/E/C Pipelining
26. R/U/An/Ap Data Hazard
27. R/U/An/Ap Control Hazards

UNIT-V MEMORY AND I/O

S. Knowledge Course
Course Content
No. Level Outcomes
28. R/U Memory Concepts and Hierarchy 202.5
29. R/U Memory Management
30. R/U Cache Memories
31. R/U/An/Ap Mapping and Replacement Techniques
32. R/U Virtual Memory
33. R/U DMA
34. R/U I/O – Accessing I/O
35. R/U Parallel and Serial Interface
36. R/U/An/Ap Interrupt I/O
37. R/U Interconnection Standards: USB, SATA

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CS4351 Digital Logic and Computer Organization Department of CSE 2024-2025

UNIT I COMBINATIONAL LOGIC


Combinational Circuits – Karnaugh Map - Analysis and Design Procedures – Binary Adder – Subtractor –
Decimal Adder - Magnitude Comparator – Decoder – Encoder – Multiplexers - Demultiplexers
PART-A
1 Draw the 4 bit Binary to Gray code converter . BL1
2 Draw the 4 bit Gray to Binary code converter. BL1
3 State the differences between combinational logic and sequential logic.(2022) BL1
4 Design a half subtractor. BL1
5 Define Combinational circuit. BL4
6 What is an ALU? BL1
7 Give the truth table for half adder and write the expression for sum and carry. BL1
8 Implement half Adder using NAND Gates. BL2
9 Give the expression for sum and carry output of a full adder and implement the same. BL1
10 Obtain an expression for difference and borrow outputs of a full subtractor. BL2
11 Draw the logic circuit for the expression F=A’B+AB’C’ (2022) BL2
12 Draw the logic circuit for the expression F=x’y’z+x’yz’+xy’. BL2
13 What is a priority encoder? (Apr/May ‘17) BL1
14 What is half-subtractor and full-subtractor? BL1
15 Using a single IC 7485, draw the logic diagram of a 4-bit comparator. BL3
16 What is a half-adder and Full Adder circuit? BL1
17 Give some of the major applications of multiplexers. BL1
18 List the applications of decoders. BL1
19 Define logic synthesis and simulation. BL1
20 Draw the logic diagram of a one to four demultiplexer. BL1
21 Define Tristate gates. BL1
22 Define Combinational circuits. (May/June ‘16) BL1
23 Draw the circuit for 2 to 1 multiplexer circuit. and Give functional block diagram of 2 * 1 MUX BL1
(May/June ‘14/’17) (Nov/Dec ‘16)
24 Construct a full adder using two half adders and OR' gate. (Apr./May.’19) BL3
25 Implement a 4 bit even parity checker. BL3
26 Write HDL behavioral description of 4 bit comparator with 6 bit output y[5:0]. BL1
27 Write the stimulus for 2 to 1 line Mux. BL1
28 Deign the combinational circuit with 3 inputs and 1 output. The output is 1 when the binary BL6
value of the input is less than 3. The output is 0 otherwise. (May/June ‘16)
29 Draw 1:8 Demultiplexer using two 1:4 Demultiplexers. (Nov/Dec’18) BL1
30 What is propagation delay? (Nov/Dec’18) BL1
31 Draw the Truth Table of Full adder. (Apr/May ’18) BL1
32 State the different modeling techniques used in HDL. (Apr/May ’18) BL1
33 Write the truth table of 2 to 4 line decoder and draw its logic diagram. (Apr./May.’19) BL1
34 What is multiplexer? Show the block diagram of 4x1 multiplexer. (Nov./Dec.’19) BL1
A
35 What is magnitude comparator? (Nov./Dec.’19) BL1
PART B
1 Design and Implement a 8421 to gray code converter. (Nov/Dec ‘14) BL6
Realize the converter using only NAND gates.
2 Design 2-bit Magnitude Comparator and write a Verilog HDL code. (Nov/Dec ‘14) BL6
3 (i) Implement the following Boolean functions with a multiplexer: (Apr/May ’15 & ‘18) BL3
F(w,x,y,z) = ∑ (2,3,5,6,11,14,15)
(ii) Construct a 5 to 32 line decoder using 3 to 8 line decoders and 2 to 4 line decoder.
4 Design a full subtractor and derive expression for difference and borrow. (Nov/Dec. ’15, 22) BL6
Realize using gates.
5 Design a code converter that converts a 8421 to BCD code. (Nov/Dec. ‘15) BL6

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CS4351 Digital Logic and Computer Organization Department of CSE 2024-2025
6 Design a full adder with x, y, z and two outputs S and C. The circuits performs x+y+z, z is the input BL6
carry, C is the output carry and S is the Sum. (May/June ‘16)
7 Design a combinational circuit that converts a four-bit Gray code to a four-bit binary number using BL6
exclusive-OR gates. (May/June ‘16) (Nov/Dec ’19)
8 Implement the following Boolean function with 4 X 1 multiplexer and external gates. Connect inputs A BL3
and B to the selection lines. The input requiremnts for the four data lines will be a function of variables
C and D these values are obatined by expressing F as a function of C and D for each four cases when
AB = 00, 01, 10 and 11. These functions may have to be implemented with external gates. F(A, B, C,
D) = Σ (1, 2, 5, 7, 8, 10, 11, 13, 15). (May/June ‘16
9 (i)Compare and contrast between encoder and multiplexer. (Nov/Dec ‘16) BL1
(ii) Design a combinational circuit to convert binary to gray code. BL6
10 (i) Design a combinational circuit that converts 8421 BCD code to excess-3 code. (Apr./May.’19) BL6
(ii) With a neat diagram explain 4-bit adder with carry look ahead. (Nov/Dec ‘16) BL1
11 Construct a BCD adder circuit and write a HDL program module for the same. (Apr/May ‘17) BL6
12 Implement the Boolean function using 8:1 multiplexer F(W,X,Y,Z) = W′XZ′ +WYZ + X′YZ + W′Y′Z BL3
(Apr/May ’17)
13 Explain in detail about Encoders and Decoders. (Nov/Dec’18) BL1
14 Design 32 to 1 multiplexer using 8 to 1 multiplexer and 2 to 4 decoder. (Nov/Dec’18) BL6
15 With suitable illustration explain the operation of BCD adder. (Apr/May‘18) (Nov/Dec’19) BL2
(ii) Implement Boolean function F(x, y, z) = ∑ (1, 2, 6, 7) using multiplexer.
16 (i) Design of 4 bit binary adder-subtractor circuit. (Apr./May.’19) (Nov/Dec’19) BL6
(ii) Design a combinational circuit that accepts a 3-bit number and generates a 6-bit binary number
output equal to the square of the input number. Write a high-level behavior VHDL description for the
circuit.
17 (i) Explain the Logic Diagram of a 4-Input Priority Encoder. (Apr./May.’19) BL2
(ii) Implement the following -Boolean function with an 8-to-1-linemultiplexer and an inverter.
F(A,B,C,D) =∑ (2,4,6,9, 10,11,15).
18 Draw and explain the logic circuit of a 4-bit magnitude comparator. (Apr/May ’19,22) BL2

UNIT II SEQUENTIAL LOGIC


Introduction to Latches – Difference: Combinational and sequential circuits- Flip-Flops– operation and excitation tables,
Triggering of FF, Analysis and design of clocked sequential circuits - Registers – Counters.
PART A

1 With reference to a JK flip-flop, what is racing? (Nov/Dec ‘14) (May/June ‘14) BL1
2 Give the truth table for J-K flip-flop BL1
3 Draw the diagram of T flip flop and discuss its working. (Nov/Dec ‘15) BL1
4 State the excitation table of JK Flip Flop. (May/June ‘16) BL1
5 Mention the uses of shift registers. BL4
6 What are Mealy and Moor machines? (or) Distinguish Moore and Mealy circuit. (Nov/Dec 14) BL1
7 Why D FF is known as Delay FF? BL1
8 Draw the logic diagram and write the function table of D Latch. (Apr./May.’19) BL3
9 Show the T- Flip flop implementation from SR flip flop
10 Define the hold time requirement of a clocked FF? BL1
11 What is meant by triggering of Flip flop? BL1
12 Give the truth table of T flip flop. BL1
13 Name the two problems that may arise in ripple counters or asynchronous counters. BL1
14 When is a counter said to suffer from lockout? BL1
15 Mention why the decoding gates for an asynchronous counter may have glitches on their BL1
outputs?
16 Draw a Mod 6 counter using feedback technique. BL3

17 What is a self-correcting counter? BL1

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CS4351 Digital Logic and Computer Organization Department of CSE 2024-2025
18 State how an asynchronous down counter differs from an up counter circuit. BL1
19 What is the minimum number of flip-flops needed to build a counter of modulus 60? BL1
20 What is a universal shift register? (2022) BL1
21 A shift register comprises of JK flip-flops. How will you complement the contents of the register? BL2
22 If a serial-in-serial-out shift register has N stages and if the clock frequency is f, what will be the BL4
time delay between input and output?
23 What is a state diagram? BL1
24 What do you meant by the term state reduction problem? BL1
25 Define Bit time & Word time. BL1
26 Give applications of J-K flip-flops. BL1
27 How race around condition can be eliminated? BL1
28 Give application of D and T flip-flops. BL1
29 What is flip-flop? BL1
30 Write the characteristics table and equation of JK flip flop. (May/June ‘14) BL1
31 What is the operation of JK flip flop? (Nov/ Dec ‘16) BL1
32 Define race around condition. (Nov/ Dec ‘16) (Apr/May ‘17) BL1
33 What are the significances of state assignment? (Apr/May ‘17) BL1
34 What is edge triggered flip flop? (Apr/May ‘17, Nov/ Dec ‘17) (Apr./May.’19) BL1
35 State the operation of T Flip-Flop. (Nov/ Dec ‘18) BL1
36 Mention the different types of shift registers. (Nov/ Dec ‘18) BL1
37 What is the drawback of SR flip-flop? How is it avoided in JK flip-flop? (April/May ’18) BL1
38 State the difference between latches and flip flops. (Apr./May.’19, 22) BL2
PART B
1 Design a sequential circuit by the following state diagram using T-flip flops (Nov/Dec ‘13) BL6

2 Design a synchronous counter that counts the sequence 000,001,010,011,100,101,110,111,000 using D BL1
flip flop. (May/June ‘14)
3 Implement T flipflop and JK flipflop using D flipflop. (May/June ‘14) (Apr/May ‘17) BL4
4 Design a BCD counter using JK flip-flops. (or) Design a MOD-10 Synchronous counter using JK flip- BL6
flops. Write execution table and state table. (Nov/Dec ‘14)
5 (i) A sequential circuit with two D flip-flops A and B, one input x and one output z is specified by the BL5
following next-state and output equations: (April/May ‘15)
A(t+1)= A′+B, B(t+1)=B′x, z=A+B′
(1) Draw the logic diagram of the circuit
(2) Draw the state table
(3) Draw the state diagram of the circuit
(ii) Explain the difference between a state table, characteristics table and excitation table.
6 Consider the design of 4-bit BCD counter that counts in the following way: (April/May ‘15) BL6
0000,0010,0011,….,1001 and back to 0000
(i) Draw the state diagram
(ii) List the next state table
Draw the logic diagram of the circuit
7 Design a binary counter using T flip flops to count in the following sequences: (May/June ‘16) BL6
(i) 000, 001, 010, 011, 100, 101, 111, 000
(ii) 000, 100, 111, 010, 011, 000
8 (i) Implement JK filp-flop using D flip flop. (Nov/ Dec ‘16) BL4
(ii) How race condition can be avoided in a flip flop.
9 Explain the operation of JK FF, SR FF, T-FF and D-FF with a neat diagram. Also discuss their BL5
characteristic equation and excitation table. (Nov/ Dec ‘17)

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CS4351 Digital Logic and Computer Organization Department of CSE 2024-2025
10 Design mod-7 counter using JK flip-flop. (Nov/ Dec ‘17) BL6

11 Draw logic circuit diagram for 3-bit synchronous up-down counter with clear input, start input and BL3
‘done’ output. The counter should produce ‘done’ output after completion of counter in either
direction.
12 Design a sequential circuit using RS flip flop for the state table with minimum flip flop. BL6
Present
Next State Output
State
x=0 x=1 x=0 x=1
A A B 0 0
B C D 0 0
C A D 0 0
D E F 0 1
E A F 0 1
F G F 0 1
G A F 0 1
13 What is the difference serial and parallel transfer? Explain how to convert parallel data to serial and BL1
serial data to parallel. What type of register is needed?
14 BL6
Design and implementation of SR Flip-Flop using NOR gate. (Nov/ Dec ‘18)
15 BL2
Explain in detail about 4 bit Johnson Counter. (Nov/ Dec ‘18)
16 BL6
Design Synchronous Mod 10 counter using D flipflop. (Apr/May ‘18)
17 (i) Describe the operations of R-S flip flop with a neat sketch. (Apr./May.’19) BL6
(ii) Design a sequential circuit with two D flip- flops A and B and one input X. When X=0, the state
of the circuit remains the same. When X=1, the circuit goes through the state transitions from 00 to10
to 11 to 01, back to 00 and then repeats.
18 (i)Construct a clocked Master Slave J.-K Flip flop and explain. (Apr./May.’19) BL3
(ii) A sequential circuit with two D flip-flops A and B, two inputs X and Y, and one output Z is
specified by the following input equation
A(t+1)=x'y+xA,
B(t+1)=x'B+xA, z=B
Draw the logic diagram of the circuit. Derive the state table and state diagram and state whether it is a
Mealy or a Moore machine.
19 Design a 3-bit binary counter using T flip flops. BL6
(Nov./Dec.’19)
20 (i) What are registers? Construct a 4-bit register using D flip-flops and explain the operations on the BL1
register. (Nov./Dec.’19)
(ii) With diagram explain how two binary numbers are added serially using shift registers:
21 A sequential circuit with two Dflip flops A and B, two inputs x and y; and one output z is specified by BL3
the following next-state and output equations:
A(t+1)=xy'+xB,
B(t+1)=xA+xB', z=A (Nov./Dec.’19)
(i) Draw the logic diagram of the circuit.
(ii) List the state table for the sequential circuit.
(iii) Draw the corresponding state diagram.
22 Explain the operations of a 4-bit bi directional Shift Register. (Apr./May.’19) BL2

UNIT III COMPUTER FUNDAMENTALS


Functional Units of a Digital Computer: Von Neumann Architecture – Operation and Operands of Computer Hardware
Instruction – Instruction Set Architecture (ISA): Memory Location, Address and Operation – Instruction and Instruction
Sequencing – Addressing Modes, Encoding of Machine Instruction – Interaction between Assembly and High Level
Language.
PART A

1 What are instructions capable of performing four types? BL1

2 What is Register Transfer Natation(RTN)? BL1


3 What are the Advantages and Disadvantages of addressing modes? BL1

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CS4351 Digital Logic and Computer Organization Department of CSE 2024-2025
4 Write the types of addressing modes. BL1
5 What is addressing modes? (2022) BL4
6 What is immediate mode? BL1
7 What is register mode? BL1
8 What is stack addressing mode? BL1
9 What are the relative addressing mode? BL1
10 What is base register addressing mode? BL1
11 What are the types of memories are used in computer systems? BL1
12 What are the Components of Von-Neumann Model? BL1
13 Draw basic structure of Von Neumann Architecture. (2022) BL1
14 What are the functional units of digital computers? BL1
15 What are the types of Operands in Computer Organization. BL1
16 Define ISA. BL1
17 What are the types of instructions set? BL1
18 What is a High-level language? BL1
19 What is an Assembly level language? BL1
20 Write any two Difference Between Assembly Language and High-Level Language. BL1
Part B
1 Explain the addressing mode with advantages and disadvantages. BL2
2 Explain encoding of machine instruction. BL2
3 Discuss Instruction set Architecture (2022) BL6
4 Difference between Assembly and high level languages BL3
5 Explain computer hardware instructions BL2
6 Discuss Instruction set BL6
7 Explain the functional units of digital computers. BL2
8 Discuss in detail about Von Neumann Architecture (2022) BL6
9 Explain in Detail about instruction Set Architecture (ISA) BL2
10 Explain Operation and Operands of Computer Hardware Instruction BL2

UNIT IV PROCESSOR
Instruction Execution – Building a Data Path – Designing a Control Unit – Hardwired Control, Microprogrammed
Control – Pipelining – Data Hazard – Control Hazards.
PART A
1 What is instruction cycle? BL1

2 What is the four phases of instruction cycle? BL1


3 Define program counter. BL1

4 What is MAR? BL1


5 What is IR? BL4
6 What is an arithmetic-logic unit (ALU)? BL1

7 What is register file? BL1

8 What is meant by sign extend? BL1

9 What is meant by branch taken? BL1

10 Define untaken branch? BL1

11 How is control unit classified? BL1

12 Define Micro-routine. BL1


13 What is Control Store? BL1

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CS4351 Digital Logic and Computer Organization Department of CSE 2024-2025
14 What are Types of Micro-programmed Control Unit? BL1
15 What is micro program? BL1

16 What is pipelining? (2022) BL1

17 What are the types of pipelining? BL1

18 Give formula for pipeline speed up? BL1

19 Define latency in pipelining BL1

20 Define Throughput in pipelining BL1


21 What are the types of hazards? BL1
22 What is data hazard? BL1
23 What are the four types of types of data dependencies? BL1
24 What are various methods to handling data hazard? BL1
25 What is control hazard? BL1
26 What is control unit? BL1
27 What is MBR? BL1
28 What is Microprogrammed Control? BL1
29 What is state element? BL1
30 What is hardwired control unit? BL1
PART B
1 Explain the role of components in instruction cycle? BL2
2 Explain the Steps for Executing of Instruction by CPU BL2
3 Why Instruction Cycle is required? write the Significance of Instruction of Cycle. BL1
4 Give brief description on various Types of Elements in the Datapath BL2
5 Explain Building a Datapath BL2
6 Discuss about Hardwired Control? BL6
7 what is Micro-programmed Control? BL2
8 Difference between Hardwired and Micro-programmed Control Unit (2022) BL3
9 Give brief description on various types of Micro-programmed Control Unit BL2
10 Explain 5 clock cycles of pipelining. BL2

UNIT V MEMORY AND I/O


Memory Concepts and Hierarchy – Memory Management – Cache Memories: Mapping and Replacement Techniques –
Virtual Memory – DMA – I/O – Accessing I/O: Parallel and Serial Interface – Interrupt I/O – Interconnection
Standards: USB, SATA
PART A
1 Write the advantages of memory hierarchy. BL1
2 Write the types of memory management. BL1
3 What is cache memory? (2022) BL1
4 Write the cache performance. BL1
5 What is mapping and its types? BL1
6 What is directing mapping? BL1
7 What is associative mapping? BL1
8 What is set-associative mapping? BL1
9 What is virtual memory? (2022) BL1
10 How virtual memory is work? BL1
11 Write the types of virtual memory. BL1
12 What is virtual memory paging? BL1
13 What is virtual memory in segmentation? BL1

14 Write the types of memory. BL1


PART B

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CS4351 Digital Logic and Computer Organization Department of CSE 2024-2025
1 Explain the virtual memory and its types. (2022) BL2
2 Explain the benefits of virtual memory. And its limitations. It can handle twice as many addresses as BL2
main memory
3 Explain accessing inputs and outputs. BL2
4 Explain USB. BL2
5 Explain SATA. BL2
6 Explain in detail about Parallel Interface BL2
7 Explain in detail about Serial Interface BL2
8 Discuss about mapping. BL6
9 How a virtual memory manager separates RAM BL2
10 How to manage virtual memory BL2

BL1- Remembering; BL2- Understanding; BL3- Applying; BL4- Analyzing; BL5- Evaluating; BL6- Creating

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