Reg.No:_____________________ i. Express it in sum of minterms.

ii. Find the minimal sum of products expression (CO2)(K3) [NOV/DEC2018]

R.V.S. COLLEGE OF ENGINEERING & TECHNOLOGY, COIMBATORE.
(13)
Department of Electrical and Electronics Engineering
(Or)
MODEL EXAMINATION- DECEMBER- 2022
b. Draw the logic diagram of a 2-to-4 line decoder using NOR gates only.
Subject code & Name: EE3302 DIGITAL LOGIC CIRCUITS Include an enable input (CO2)(K2) [NOV/DEC2018] (13)
Year / Branch / SEM: II /EEE /III Duration: 3 Hours
Date: 21.12.22(AN) (01.30 - 04.30 pm) Max. Marks: 100 13.
a. Design a combinational logic circuits to convert binary to Gray code and write
Answer All the Questions its truth table. (CO2)(K5) [APRIL/MAY 2018] (13)
Part - A (5 x 2 = 10 Marks) (Or)
1. Convert the following binary code into a Gray Code: b. Implement the following Boolean function using 4:1 multiplexer.
10101110002 (CO1)(K2) [APRIL/MAY 2016]
2. State the associative property of Boolean Algebra (CO1)(K1) [APRIL/MAY 2018] F(W,X,Y,Z)= Σ m(0,1,2,4,6,9,12,14) (CO2)(K5) [APRIL/MAY 2018] (13)
3. Write the POS representation of the following SOP function: 14.
f (x, y, z) = Σm (0, I, 3, 5, 7) (CO2)(K2) [APRIL/MAY 2016] a.
4. Design a half subtractor. (CO2)(K5) [APRIL/MAY 2017] i. Explain the operation of SR flip flop ,JK flip flop and T flip flop
5. Give the characteristic equation and characteristic table of a T Flip Flop. (CO3)(K1)
[APRIL/MAY 2016] (CO3)(K2) [NOV/DEC 2018] (7)
6. State the differences between. Moore and Melay state machines. (CO3)(K1) ii. Design a MOD-5 Counter using T Flip Flop(CO3)(K5) [NOV/DEC2017]
[APRIL/MAY 2017] (6)
7. Name the three types of hazards. (CO4)(K1) [NOV/DEC2019]
(Or)
8. State the difference between PROM, PLA and PAL. (CO4)(K1) [MAY/JUNE
2016] b. Explain in detail about different shift register (CO3)(K2) [NOV/DEC2017]
9. Give the syntax for package declaration and package body in VHDL. (CO5)(K1) (13)
[APRIL/MAY 2017] 15.
10. Write the VHDL code for a 2 x 1 multiplexer using behavioral
modeling(CO5)(K2) [MAY/JUNE 2016] a. Write a VHDL code to realize a full adder using behavioral modeling and
structural modeling. (CO5)(K5) [APRIL/MAY 2019] (13)
(Or)
Part - B (5*13=65 Marks) b. Design a 3 -bit magnitude comparator and write the VHDL code to realize it
11. using structural modeling. (CO5)(K5) [APRIL/MAY 2017] (13)
a.
i. Convert the given expression in canonical SOP form Y=AC+AB+BC Part - C (1*15=15 Marks)
(CO1)(K3) [APRIL/MAY 2018] (5) 16.
ii. Prove that ABC+ ABC’+ AB’C+ A’BC= AB+AC+BC (CO1)(K3) a. Simplify the following function and implement it using NAND gates only:
[APRIL/MAY 2018] (8) F(w,x,y,z)= Σ(1, 3, 5, 7, 9,11, 13, 15), with don't care states
(Or) d(w,x,y,z)= Σ (0, 2, 4, 6, 8) (CO2)(K3)[APRIL/MAY 2019] (15)
b. write a short notes on following (Or)
(i) RTL (ii) DTL (iii) TTL (iv) ECL b. Implement the following function using PLA and PAL:
(CO1)(K2) [NOV/DEC2017] (13) F 1 (A, B, C) = Σ m (3, 5, 6, 7) and F2 (A, B, C) = Σ m (0, 2, 4, 7)
12. (CO4) (K5) [NOV/DEC2019] (15)
a. Given the following Boolean function F = A' C + A' B + AB' C + BC.