THE INTEL 8086 MICROPROCESSOR

LECTURE - 6

Abdullah Al Noman
Lecturer
Computer Science and Engineering Department
Shahjalal University of Science and Technology
8086 Interrupt System
8086 INTERRUPT SYSTEM

o The 8086 interrupts can be classified into three types. These are
1. Predefined interrupts
• These interrupts are predefined by the manufacturer and serve specific
functions.

2. User-defined software interrupts

• Which can be initiated by the user through software

3. User-defined hardware interrupts

• Which can be initiated by the user through hardware
 BASICS OF INTERRUPT

• Every interrupt has a number called “interrupt number.”

• For example 20h or 21h etc.

• The number of interrupts can be from 0 to 255.

• In assembly language, we call a function subroutine.

• Each interrupt has a different ISR (interrupt service routine) which has to be defined
previously.

• ISR must be terminated with the IRET (interrupt return) instruction.

 WHAT HAPPENS WHEN AN INTERRUPT OCCURS?

Initially, CS and IP point to this location.

If an interrupt occurs while executing this
Let's assume while executing this instruction, this instruction will be completed first
instruction, an interrupt occurs. then the microprocessor will take a break.

At this point, the microprocessor will

push this address to the stack.
To run these ISRs, the starting address of
Now, the microprocessor is ready to those ISRs should be loaded into the CS and
execute the ISR using the interrupt IP.
number. To execute ISR, the
microprocessor calculates the particular
starting address of ISR using an interrupt Each starting address of ISR requires 4 bytes.
number and loads the starting address of Which is already stored in RAM. How and
ISR in CS and IP. where these addresses are stored?
 INTERRUPT VECTOR TABLE

• The interrupt vector addresses for all the 8086 interrupts are determined from a table
stored in locations 00000H through 003FFH.

• The starting addresses for the service routines for the interrupts are obtained by the
8086 using this table.

• Four bytes of the table are assigned to each interrupt: two bytes for IP and two bytes for
CS.

• The table may contain up to 256 32-bit vectors.

INTERRUPT VECTOR TABLE
 8086 INTERRUPT SYSTEM

• The 8086 assigns every interrupt a type code for identifying the interrupt.

• There are 256 type codes associated with the 256 table entries.

• Each entry consists of two word addresses, one for storing the IP contents and the other
for storing the CS contents.

• Each 8086 interrupt physical address vector is 20 bits wide and is computed from the
16-bit contents of IP and CS.

• How will the microprocessor know which interrupt service routine to run from this
interrupt number?
 8086 INTERRUPT SYSTEM

• For example, for the interrupt type n (instruction INT n), the table address for 𝐼𝑃 =
4 ∗ 𝑛 and the table address for 𝐶𝑆 = (4 ∗ 𝑛) + 2.

• For servicing the 8086's non-maskable interrupt (NMI pin), the 8086 assigns the type
code 2 to this interrupt. The 8086 automatically executes the INT 2 instruction
internally to obtain the interrupt address vector as follows:

• The 8086 loads the values of IP and CS from the 20-bit physical addresses 00008H and
0000AH in the pointer table. The user must store the desired 16-bit values of IP and CS
in these locations. Similarly, the IP and CS values for other interrupts are calculated.
 8086 INTERRUPT SYSTEM

• In response to an interrupt, the 8086 pushes flags, CS, and IP onto the stack, clears TF
and IF flags and then loads IP and CS from the pointer table using the type code.

• Interrupt service routines must be terminated with the IRET (Interrupt Return)
instruction which pops the top three stack words into IP, CS, and flags, thus returning to
the right place in the main program.

• The 256 interrupt type codes are assigned as follows:

• Types 0 to 4 are for the predefined interrupts.
• Types 5 to 31 are reserved by Intel for future use.
• Types 32 to 255 are available for maskable interrupts.
 PREDEFINED INTERRUPT (0 - 4)

• The predefined interrupts include

1. DIVISION BY ZERO (type 0),

2. SINGLE STEP (type 1)
3. NONMASKABLE INTERRUPT pin (type 2),
4. BREAKPOINT-INTERRUPT (type 3), and
5. INTERRUPT ON OVERFLOW (type 4).

• The user may also imitate these interrupts through hardware or software.

• If a predefined interrupt is not used in a system, the user may assign some other
function to the associated type.
 DIVISION BY ZERO (TYPE 0)

• The 8086 is automatically interrupted whenever a division by zero is attempted.

• This interrupt is non-maskable and is implemented by Intel as part of the execution of

the divide instruction.
 SINGLE STEP (TYPE 1)

• When the TF (TRAP/TRACE flag) is set by an instruction, the 8086 goes into the
single step mode. The TF can be set to one as follows:

• Note that in the above [BP + 0] rather than [BP] is used since BP cannot be used
without displacement.
• Once TF is set to one, the 8086 automatically generates a TYPE 1 interrupt after
execution of each instruction. The user can write a service routine at the interrupt
address vector to display memory locations and/or register to debug a program. Single
step is non-maskable and cannot be enabled by STI (enable interrupt) or disabled by
CLI (disable interrupt) instruction.
 NONMASKABLE INTERRUPT PIN (TYPE 2)

• The non-maskable interrupt is initiated via the 8086 NMI pin.

• It is edge triggered (LOW to HIGH) and must be active for two clock cycles to
guarantee recognition.

• It is normally used for catastrophic failures such as power failure.

• The 8086 obtains the interrupt vector address by automatically executing the INT 2
(type 2) instruction internally.
 BREAKPOINT-INTERRUPT (TYPE 3)

• Type 3 interrupt is used for breakpoint and is non-maskable.

• The user inserts the one-byte instruction INT 3 into a program by replacing an
instruction.

• Breakpoints are useful for program debugging.

 INTERRUPT ON OVERFLOW (TYPE 4)

• The INTERRUPT ON OVERFLOW is a type 4 interrupt.

• This interrupt occurs if the overflow flag (OF) is set and the INTO or INT 4 instruction
is executed.

• The overflow flag is affected, for example, after execution of signed arithmetic such as
IMUL (signed multiplication) instruction.

• The user can execute the INTO instruction after the IMUL.

• If there is an overflow, an error service routine written by the user at the type 4 interrupt
address vector is executed.
 USER-DEFINED SOFTWARE INTERRUPTS

• The user can generate an interrupt by executing a two-byte interrupt instruction INT n.

• The INT n instruction is not maskable by the interrupt enable flag (IF).

• The INT n instruction can be used to test an interrupt service routine for hardware
(external) interrupts.

• If predefined interrupt is not used in a system, the associated type code can be utilized
with the INT n instruction to generate software (internal) interrupts. So, type codes 0 to
255 can be used.

• Example: On board.
 USER-DEFINED HARDWARE INTERRUPTS

• An ISR should also be written for hardware interrupts. But the difference is that this
hardware interrupt will never be called like the following.
INT 21h

• Since it is a hardware interrupt, the device that is connected to the microprocessor will
call this interrupt.

• The interrupt flag must be set for hardware interrupts to work.

• Interrupt numbers up to 32 cannot be used for hardware interrupts. But all can be used
for software interrupts.
 USER-DEFINED HARDWARE INTERRUPTS

• Let’s say we defined interrupt number 36 as a hardware interrupt.

USER-DEFINED HARDWARE INTERRUPTS

• Hardware interrupts can be many because many hardware can be connected at once.
But how does the microprocessor know which hardware interrupt to activate?
 USER-DEFINED HARDWARE INTERRUPTS

• Let’s say, at some point the connected device at

address 40 needs to interrupt. This device will first
make an interrupt request to the microprocessor. Then
the microprocessor will stop its running operation.
Then the microprocessor will be confused because it
doesn't know which hardware has given it the
interrupt request. Then the microprocessor will send
an interrupt acknowledge signal to all. Then the
hardware that was trying to cause the interrupt will
know that the microprocessor has received the
interrupt signal. Then the hardware will send the
interrupt number (let’s say 40) to the microprocessor
through its data line. Then the microprocessor will
execute that hardware-related ISR.
 USER-DEFINED HARDWARE INTERRUPTS

• What happens if two hardware interrupt requests together?

• The device that is serially connected to the microprocessor first will work first.
So we will connect the hardware devices serially with the microprocessor
according to priority.

• Priority list of interrupts (If the two come together)

Single step > NMI > S/W > H/W

• When these three (Single step, NMI, S/W ) occur together

S/W > NMI (And single step will not work)
THANK YOU