Outlines

 The Metal Oxide Semiconductor (MOS) structure

 The MOS System under external bias
 Structure and Operation of MOS transistor
 MOSFET Current-Voltage characteristics
 MOSFET scaling and small-geometry effects
 MOSFET capacitances
 Outcomes
 References

1 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The Metal Oxide Semiconductor (MOS)
structure
 Compare to BJT, MOS transistor occupies a relatively smaller
silicon area, and its fabrication used to involve fewer
processing steps.
 We will examine the basic structure and electrical behavior
of nMOS as well as pMOS devices.
 The basic operation principles of both nMOS and pMOS
transistor are very similar to each other.
 We will start with the electrical behavior of the simple two
terminal MOS structure shown in figure.3.1
 Note that, the structure consist of three layers:

2 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The Metal Oxide Semiconductor (MOS)
structure

3 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The Metal Oxide Semiconductor (MOS)
structure
 Three layers are: The metal gate electrode, the insulating
oxide(SiO2) layer, and the p-type bulk semiconductor, called
the substrate.
 As such , the MOS structure forms a capacitor, with the gate
and the substrate acting as the two terminals and oxide layer
as the dielectric.
 The equilibrium concentrations of mobile carriers in a
semiconductor always obey the Mass Action Law given by

n. p = n .....(3.1)
2
i

4 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The Metal Oxide Semiconductor (MOS)
structure
 Here, n and p denote the mobile carrier concentrations of
electrons and holes, respectively, and ni denotes the intrinsic
carrier concentration of silicon, which is function of
Temerature T. (300K)

ni = 1.45  1010 cm −3
 Assuming that the substrate is uniformly doped with
acceptor(e.g. Boron concentration NA, the equilibrium
electron and hole concentrations in the p-type substrate are
approx given by eqn 3.2

5 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The Metal Oxide Semiconductor (MOS)
structure
2
n
n po  i

NA
p po  N A .....(3.2)

 The doping concentration of NA is typically on the order of

10^15 to 10^16 cm^-3; thus , it is much greater than the
intrinsic carrier concentration ni.

6 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The Metal Oxide Semiconductor (MOS)
structure
 The energy band diagram of p-type substrate is shown in fig
3.2. The band gab between the conduction band and the
valence band for silicon is approximately 1.1 eV.
 The location of the equilibrium Fermi level EF with in the
band –gap is determined by the doping type and the doping
concentration in the silicon substrate.
 The Fermi potential  , which is a function of temperature
F
and doping, demotes the difference between the intrinsic
Fermi level Ei and the Fermi level EF.

7 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The Metal Oxide Semiconductor (MOS)
structure

8 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The Metal Oxide Semiconductor (MOS)
structure
EF − Ei
F = .....(3.3)
q
 For a p-type semiconductor, Fermi potential can be
approximated by

kT ni
Fp = ln .....(3.4)
q NA
 Whereas for an n-type semiconductor(doped with donor
concentration ND), the Fermi potential is given by

9 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The Metal Oxide Semiconductor (MOS)
structure
kT N D
Fn = ln .....(3.5)
q ni
 Here, k denotes the Boltzmann constant an q denotes the
unit charge.
 Note that the definition given in (3.4) and (3.5) results in a
positive Fermi potential for n-type material, and a negative
Fermi potential for p-type material.
 The electron affinity of silicon, which is the potential
difference between the conduction band level and the
vacuum(free space) level, is denoted by qX in fig. 3.2.

10 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The Metal Oxide Semiconductor (MOS)
structure
 The energy required for an electron to move from the Fermi
level into free space is called the work function, and is given
by ,

qS = q  + ( EC − EF ).....(3.6)
 The insulating silicon dioxide layer between the silicon
substrate and the gate has a large band gap of about 8 eV and
an electron affinity of about 0.95 eV. On the other hand, the
work function of an aluminum gate is about 4.1 eV.
 Figure 3.3 shows the energy band diagram of three layers.

11 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The Metal Oxide Semiconductor (MOS)
structure

12 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The Metal Oxide Semiconductor (MOS)
structure
 Now consider that the three components of the ideal MOS
system are brought into physical contact.
 The Fermi levels of all three materials must line up, as they
form the MOS capacitor as shown in figure 3.1.
 Because of the work-function difference between the metal
and the semiconductor, a voltage drop occurs across the
MOS system.
 Part of this built in voltage drop occurs at the silicon surface
next to the silicon oxide interface, forcing the energy bands
of silicon to bend in this region.

13 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The Metal Oxide Semiconductor (MOS)
structure

14 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The Metal Oxide Semiconductor (MOS)
structure
 The resulting combine energy band diagram of the MOS
system is shown in fig.3.4.
 Notice that the equilibrium Fermi levels of the
semiconductor Si substrate and the metal gate are at the same
potential.
 The bulk Fermi level is not significantly affected by the band
bending, whereas the surface Fermi level moves closer to the
intrinsic Fermi (mid-gap) level.
 The Fermi potential at the surface, also called surface
potential  , is smaller in magnitude than the bulk Fermi
S
potential.

15 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The MOS System under External Bias
 We now turn our attention to the electric behavior of the
MOS structure under externally applied bias voltage.
 Assume that the substrate voltage is set at VB=0, and let the
gate voltage be the controlling parameter.
 Depending on the polarity and the magnitude of VG, three
different operating regions can be observed for the MOS
system: accumulation, depletion and inversion.
 If a negative voltage VG is applied to the gate electrode,
the holes in the p-type substrate are attracted to the
semiconductor-oxide interface.

16 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The MOS System under External Bias

17 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The MOS System under External Bias
 The majority carrier concentration near the surface becomes
larger than the equilibrium hole concentration in the
substrate; hence this condition is called carrier
accumulation on the surface.( Fig. 3.5).
 Note that in this case, the oxide electric field is directed
towards the gate electrode. The negative surface
potential also causes the energy bands to bend
upward near the surface.
 While the hole density near the surface increases as a result
of the applied negative gate bias, the electron(minority
carrier) concentration decreases as the negative charged
electrons are pushed deeper into the substrate.

18 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The MOS System under External Bias
 Now consider the next case in which a small positive gate
biasVG is applied to the gate electrode.
 Since the substrate bias is zero, the oxide electric field
will be directed towards the substrate in this case.
 The positive surface potential causes the energy bands to
bend downward near the surface, as shown in figure 3.6.
 The majority carriers, i.e., the holes in the substrate, will be
repelled back into the substrate as a result of the
positive gate bias, and these holes will leave negatively
charged fixed acceptor ions behind.
 Thus , a depletion region created near the surface.

19 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The MOS System under External Bias

20 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The MOS System under External Bias
 The thickness of depletion region on the surface can easily
found as a function of the surface potential. Assume that the
mobile hole charge in a thin horizontal layer parallel
to the surface is

dQ = −q  N A  dx.....(3.7)
 The change in surface potential require to displace this
charge sheet dQ by distance Xd away from the surface can
be found by using the Poisson equation.

21 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The MOS System under External Bias

dQ q  N A  x
d S = − x  = dx.....(3.8)
 Si  Si
 Integrating (3.7) along the vertical dimension (perpendicular
to the surface ) yields

S
q  NA  x
xd

 d =  dx.....(3.9)
 F
S
0
 Si

22 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The MOS System under External Bias

q  NA  x 2
S −  F = d
.....(3.10)
2 Si
 Thus, the depth of the depletion region is

2 Si  | S − F |
xd = .....(3.11)
q  NA
23 CC: Dr Robinson Paul | BVM EC 7/27/2022
 The MOS System under External Bias
 And the depletion region charge density, which consists
solely of fixed acceptor ions in this region, is given by the
following expression

Q = −q  N A  xd = − 2q  N A   Si  | S − F |.....(3.12)

 The amount of this depletion region charge plays a very

important role in the analysis of threshold voltage.
 Now , when we increase the positive gate bias. As a
result of the increasing surface potential, the downward
bending of the energy bands will increase as well.

24 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The MOS System under External Bias

25 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The MOS System under External Bias
 Eventually, the mid-gap energy level Ei becomes smaller than the
fermi level on the surface, which means that the substrate
semiconductor in this region become n-type.
 Within this thin layer, the electron density is larger than the
majority hole density, since the positive gate potential attracts
additional minority carriers(electrons) from the bulk substrate to
the surface(fig.3.7).
 The n-type region created near the surface by positive gate
bias is called the inversion layer, and this condition is called
surface inversion.
 It will be seen that the thin inversion layer on the surface with a
large mobile electron concentration can be utilized for conducting
current between two terminals of the MOS transistor.

26 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The MOS System under External Bias
 As a practical definition, the surface is said to be inverted
when the density of mobile electrons on the surface becomes
equal to the density of holes in the bulk (p-type) substrate.
 This condition requires that the surface potential has the
same magnitude, but the reverse polarity, as the bulk Fermi
potential.
 Further increase in the potential will increase in the mobile
electrons but not the width of the depletion region.
 So , at the surface inversion, we can able to see the maximum
depletion region depth.

27 CC: Dr Robinson Paul | BVM EC 7/27/2022

 The MOS System under External Bias
 So at surface inversion, the maximum depletion region
depth can be given by,

2 Si  | 2F |
xdm = .....(3.13)
q  NA

 The creation of conducting surface inversion layer through

externally applied gate bias is an essential phenomenon for
current conduction in MOS transistors.

28 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 The basic structure of an n-channel MOSFET is shown in
Fig.3.8.
 The surface of the substrate region between the drain and the
source is covered with a thin oxide layer, and the metal(or
polysilicon) gate is deposited on the top of this gate
dielectric.
 The midsection of the device can easily be recognized as the
basic MOS structure which was examined in the previous
sections.

29 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)

30 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 A conducting channel will eventually be formed through
applied gate voltage in the section of the device between the
drain and the source diffusion regions.
 The distance between the drain and source diffusion region is
the channel length L, and the lateral extent of the
channel(perpendicular to the length dimension) is the
channel width W.
 The thickness of oxide layer covering the channel region,
tox, is also an important parameter.

31 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 A MOS transistor which has no conducting channel region at
zero gate bias is called an enhancement type MOSFET.
 If a conducting channel already exists at zero gate bias, on the
other hand, the device is called a depletion type
MOSFET.
 P-type substrate is called n-channel MOSFET
 N-type substrate is called p-channel MOSFET.
 We can able to see all the terminals of the n-channel
MOSFET and p- channel MOSFET in the diagram 3.9 as a
symbolic representation.

32 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)

33 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 Now we check the electrical behavior of n-channel
MOSFET by applying the various voltages.
 As shown in fig 3.10. The source, the drain, and the substrate
terminals are all connected to ground.
 A positive gate –to – source voltage is then applied to
the gate in order to create the conducting channel
underneath the gate.
 With this bias arrangement, the channel region between the
source and the drain diffusions behaves exactly the same as
for the simple MOS structure we examined.

34 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)

35 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 For small gate voltage levels, the majority carriers(holes)
are repelled back into the substrate, and the surface of
the p-type substrate is depleted.
 Since the surface is devoid of any mobile carriers, current
conduction between the source and the drain is not
possible.
 Now assume that the gate-to-source voltage is further
increased. As soon as the surface potential in the channel
reaches negative fermi potential value(inverse layer),
surface inversion will be established, and a conducting n-type
layer will form between the source and the diffusion regions
as shown in fig. 3.11.

36 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)

37 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)

38 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 This channel now provides an electrical connection between
the two n+ regions, and it allows current flow.(fig.3.12)
 The value of the gate to source voltage needed to cause
surface inversion (to create the conducting channel) is called
the threshold voltage.
 Any gate to source voltage smaller than threshold voltage is
not sufficient to establish an inversion layer.
 Increasing the gate to source voltage above and beyond the
threshold voltage will not affect the surface potential and the
depletion region depth.

39 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 The Threshold Voltage
 Basically four parameters are affecting the threshold voltage
in MOS structure
 1. work function difference between the gate and the channel
and it is given by
GC = F ( substrate ) − M ( meta l −g ate ) .....(3.14)

GC = F ( substrate ) − M (g ate ) .....(3.15)

40 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 The work function difference between the gate and the
channel reflects the built in potential of the MOS system,
which consist of the p-type substrate, the thin silicon dioxide
layer, and the gate electrode.
 2. The gate voltage component to change the surface
potential.
 The external applied voltage must be changed to achieve
surface inversion, i.e., to change the surface potential by
−2F
 This will be the second component of the threshold voltage.

41 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 3. The gate voltage component to offset the
depletion region charge
 Which is due to the fixed acceptor ions located in the
depletion region near the surface.
 We can calculate the depletion region charge density at
surface inversion using (3.12)

QBO = − 2q  N A   Si  | −2F |.....(3.16)

 If the substrate (body) is biased at a different voltage level
than the source, which is at ground potential (reference),

42 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 Then the depletion region charge density can be expressed as
a function of the source to substrate voltage ,

QB = − 2q  N A   Si  | −2F + VSB |.....(3.17)

 The component that offsets the depletion region charge is

then equal to ,
QB
−
Cox
43 CC: Dr Robinson Paul | BVM EC 7/27/2022
 Structure and Operation of MOS
Transistor (MOSFET)
 The Gate oxide capacitance per unit area is given by ,

 ox
Cox = .....(3.18)
tox

 4. The voltage component to offset the fixed charges

in the gate oxide and in the silicon oxide interface.
 There always exists a fixed positive charge density at the
interface between the gate oxide and the silicon substrate,
due to impurities and/or lattice imperfections at the
interface.

44 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 The gate voltage component that is necessary to offset this
positive charge at the interface is ,

Qox
−
Cox

 So, finally combining all the four components which are

affecting the threshold voltage can be written as(for zero
substrate bias),
QBO Q
VTO = GC − 2F − − ox .....(3.19)
Cox Cox
45 CC: Dr Robinson Paul | BVM EC 7/27/2022
 Structure and Operation of MOS
Transistor (MOSFET)
 For nonzero substrate bias,

QB Qox
VT = GC − 2F − − .....(3.20)
Cox Cox

 The generalized form of the threshold voltage can also be

written as,
QBO Qox QB − QBO
VT = GC − 2F − − −
Cox Cox Cox
QB − QBO
= VTO − .....(3.21)
Cox
46 CC: Dr Robinson Paul | BVM EC 7/27/2022
 Structure and Operation of MOS
Transistor (MOSFET)
 Note that in this case, the threshold voltage differs only by an
additive term.
 This substrate bias term is a simple function of the material
constants and of the source to substrate voltage.

QB − QBO 2q  N A   Si
=−  ( | −2F + VSB | − | 2F |).....(3.22)
Cox Cox

 Thus, the most general expression of the threshold voltage

can be found as follows:

47 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)

VT = VTO +   ( | −2F + VSB | − | 2F |).....(3.23)

 Where, the parameter ,

2q  N A   Si
 = .....(3.24)
Cox
 Is the substrate bias (or body effect) coefficient.

48 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 Some of the terms have different polarities for nMOS and for
pMOS. Specifically
 Fermi potential level, depletion charge densities, substrate
bias coefficient and substrate bias voltage.
 Note that the exact value of the threshold voltage of an actual
MOS transistor can not be determined using the equation
3.23 in most practical cases, due to primarily to uncertainties
and variation of the doping concentrations, the oxide
thickness, and the fixed oxide interface charge.

49 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 Note that, using selective ion implantation into the channel,
the threshold voltage of an n-channel MOSFET can also be
made negative.
 This means that the resulting nMOS transistor will have a
conducting channel at gate to source voltage equals to zero,
enabling current flow between its source and drain terminals
as long as Vgs is larger than the negative threshold voltage.
 Such device is called depletion type(or normally ON) n-
channel MOSFET.
 Figure 3.13 shows a symbolic diagram of n channel depletion
type MOSFET.

50 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)

51 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 Example.

52 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 MOSFET Operation: A Qualitative View
 The basic structure of the n-channel MOS (nMOS) transistor
built on a p-type substrate was shown in figure 3.8.
 VGS  0 (accumulation)

 0  VGS  VTO (depletion)(no current flow)

 VGS  VTO (inversion)
 Now we will examine the electrical behavior of nMOS by
changing the value of Vds.

53 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 If small positive drain voltage is applied, a drain current will
flow from source to drain through the conducting channel.
 This operation mode is called the linear mode, or the linear
region.
 Thus, in linear region operation, the channel region act as a
voltage controlled resistor.
 As the drain voltage is increases, the inversion layer charge
and the channel and the channel depth at the drain end start
to decrease. (figure.3.14)

54 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)

Fig.3.14: cross sectional view of an n-channel MOS transistor

55 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)
 Eventually, for drain to source voltage will be equal to drain to
source saturation voltage, the inversion charge at the drain is
reduced to zero, which is called the pinch off point. Fig 3.14 b
 Beyond the pinch off point, i.e for drain to source voltage is
greater than the drain to source voltage saturation, the depletion
region grows toward the source with increasing drain voltages.
 This operation mode of the MOSFET is called the saturation mode
or saturation region.
 Because of this the effective channel length is reduced as the
inversion layer near to the drain vanishes. From this fundamentals
we can able to get the I-V characteristics of the MOSFET.

56 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)

Fig.3.14: cross sectional view of an n-channel MOS transistor

57 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Structure and Operation of MOS
Transistor (MOSFET)

Fig.3.14: cross sectional view of an n-channel MOS transistor

58 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Current –Voltage
Characteristics.
 The analytical derivation of the MOSFET current-voltage
relationship for various bias conditions requires that several
approximations be made to simplify the problem,
 Here we will use the Gradual channel approximation (GCA)
for establishing the MOSFET current voltage relationships,
which will effectively reduce the analysis to one dimensional
current flow problem.
 GCA have also its limitations, especially for small geometry
of MOSFETs. We will examine some of them and its
remedies.

59 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Current –Voltage
Characteristics.
 GCA
 To begin with the current flow analysis, consider the cross
sectional view of the n-channel MOSFET operating in the
linear mode as shown in fig. 3.15

60 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Current –Voltage
Characteristics.
VC ( y = 0) = VS = 0
VC ( y = L) = VDS .....(3.25)

Also, its is assumed that the entire channel region between the
source and the drain is inverted,.

VGS  VT 0
VGD = VGS − VDS  VT 0 .....(3.26)
61 CC: Dr Robinson Paul | BVM EC 7/27/2022
 MOSFET Current –Voltage
Characteristics.
 The channel current ( drain current) is due to electrons in
channel region traveling from the source to the drain under
the influence of the lateral electric field component Ey.
 Let Qi(y) be the total mobile electron charge in the surface
inversion layer.
 This charge can be expressed as a function of the gate to
source voltage and of the channel voltage as follows.,

QI ( y ) = −Cox  [VGS − Vc ( y ) − VT 0 ].....(3.27)

62 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Current –Voltage
Characteristics.
 Figure.3.16 shows the spatial geometry of the surface
inversion layer and indicates its significant dimensions.
 Now consider the incremental resistance dR of the
differential channel segment shown in fig 3.16.
 Assuming that all mobile electrons in the inversion layer have
constant surface mobility , the incremental resistance can be
expressed as follows.

dy
dR = − .....(3.28)
W  n  QI ( y )
63 CC: Dr Robinson Paul | BVM EC 7/27/2022
 MOSFET Current –Voltage
Characteristics.

64 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Current –Voltage
Characteristics.
 The electron surface mobility used in eq 3.28 depends on the
doping concentration of the channel region, and its
magnitude is typically about one-half of the of the bulk
electron mobility.
 We will assume that the channel current density is uniform
across this segment.
 According to the ohm's law.

ID
dVC = I D  dR = −  dy.....(3.29)
W  n  QI ( y )
65 CC: Dr Robinson Paul | BVM EC 7/27/2022
 MOSFET Current –Voltage
Characteristics.
 The equation 3.29 can now be integrated along the channel.,
i.e., from y=0 to y=L, using the boundary condition given
(3.25).
L VDS

I
0
D  dy = −W   n  Q ( y )  dV
0
I C .....(3.30)

 After simplification of eqn 3.30., we get

VDS

I D  L = W  n  Cox  (V
0
GS − Vc − VT 0 )  dVC .....(3.31)

66 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Current –Voltage
Characteristics.
 Assuming that Vc is the only variable in eqn 3.31., we get,

 n  Cox W
I D =   [2  (VGS − VT 0 )VDS − V
2
DS ].....(3.32)
2 L
 Above equation represent the drain current as a simple
second order function of the two external voltages and this
equation can also be rewritten as.,
'
k W
I D=   [2  (VGS − VT 0 )VDS − VDS
2
].....(3.33)
2 L
67 CC: Dr Robinson Paul | BVM EC 7/27/2022
 MOSFET Current –Voltage
Characteristics.
 OR,

k
I D =  [2  (VGS − VT 0 )VDS − VDS
2
].....(3.34)
2
 Where,

k =  n  Cox .....(3.35)
'

W
k = k  .....(3.36)
'

68 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Current –Voltage
Characteristics.
 The drain current equation given in (3.33) is the simplest
analytical voltage current relationship.
 The drain current is not valid beyond the linear
region/saturation region boundary,. For

VDS  VDSAT = VGS − VT 0 .....(3.37)

 This saturation drain current level can be found simply by
substituting (3.37) into 3.32
 We get,

69 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Current –Voltage
Characteristics.
 n  Cox W
I D ( sat ) =   [2  (VGS − VT 0 )  (VGS − VT 0 ) − (VGS − VT 0 ) 2 ]
2 L
 n  Cox W
I D ( sat ) =   (VGS − VT 0 ) 2 .....(3.38)
2 L
 Thus, the drain current becomes a function of the gate to
source voltage beyond the saturation boundary.
 Figure 3.17 shows the typical current versus drain voltage
characteristics of an n-channel MOSFET, as described by the
current equations 3.32 and 3.38.

70 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Current –Voltage
Characteristics.

71 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Current –Voltage
Characteristics.

72 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Current –Voltage
Characteristics.
 Channel length Modulation
 The inversion layer charge at the source end of the channel
is,
QI ( y = 0) = −Cox  (VGS − VT 0 ).....(3.39)
 And the inversion layer charge at the drain end of the channel
is ,

QI ( y = L) = −Cox  (VGS − VT 0 − VDS ).....(3.40)

73 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Current –Voltage
Characteristics.
 Now at the edge of saturation we get,

VDS = VDSAT = VGS − VT 0 .....(3.41)

 The inversion layer charge at the drain end becomes zero,
according to (3.40). Its not actually become zero but
becomes very small.

QI ( y = L)  0.....(3.42)
 Thus, we can state that under the bias condition given in3.41,
the channel is pinched off at the drain end.

74 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Current –Voltage
Characteristics.
 Now if we increase the drain to source voltage more than
saturation voltage, we can able to see the effect on channel
length, see the diagram no, 3.19

75 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Current –Voltage
Characteristics.
 The effect on channel length is,(channel length modulation)

L = L − L.....(3.43)
'

 And the channel voltage at this edge will be ,

Vc ( y = L ) = VDSAT .....(3.44)
'

 The channel current can be found using 3.38

 n  Cox W
I D ( sat ) =  '
 (VGS − VT 0 ) 2
.....(3.45)
2 L

76 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Current –Voltage
Characteristics.
 We can modify the 3.45 by using the equation 3.43, we get,

 
 1   n  Cox W
I D ( sat ) =     (VGS − VT 0 ) 2 .....(3.46)
L 2 L
 1− 
 L 
 Where,

L  VDS − VDSAT .....(3.47)

77 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Current –Voltage
Characteristics.
 For simplification,

L
1−  1 −   VDS .....(3.48)
L
 Here lemda is an empirical parameter and its also known as
channel length modulation coefficient.
 Now assuming that   V <<1, we can write the eqn
DS
3.45 as,
n  Cox W
I D ( sat ) =   (VGS − VT 0 ) 2  (1 +   VDS ).....(3.49)
2 L
78 CC: Dr Robinson Paul | BVM EC 7/27/2022
 MOSFET scaling and small-geometry
effects
 Two types of feature size reduction strategies:
 Full scaling(also called constant field scaling)
 Constant voltage scaling.
 Both have their unique effects on operating characteristics.
 Scaling MOS transistor is concerned with systematic
reduction of overall dimension of the devices as allowed by
the available technology, while preserving the geometric
ratios found in the larger devices.
 To describe device scaling, we introduce a constant scaling
factor S >1.

79 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET scaling and small-geometry
effects
 Table 3.1shows the recent history of reducing feature sizes
for the typical CMOS gate array process.

80 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET scaling and small-geometry
effects
 We consider the proportional scaling of all three dimensions
by the same scaling factor S.
 Figure 3.24 indicate the scaled dimensions and doping
densities.
 It is easy to recognize that the scaling of all dimensions by
factor of S>1 leads to the reduction of the area occupied by
the transistor by a factor of S^2.
 Here to understand the effects of scaling upon the
operational characteristics, we will examine two different
scaling options in the following sections.

81 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET scaling and small-geometry
effects

82 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET scaling and small-geometry
effects
 Full Scaling ( Constant-Field Scaling)
 This scaling option attempts to preserve the magnitude of
internal electric fields in the MOSFET, while the dimension
are scaled down by a factor of S.
 The Poisson equation describing the relationship between
charge densities and electric fields dictates that the charge
densities must be increased by a factor of S in order to
maintain the field conditions.
 Table 3.2 shows the comparison of old and new dimensions.

83 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET scaling and small-geometry
effects

84 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET scaling and small-geometry
effects
 The gate oxide capacitance per unit area is changed as follows

 ox  ox
C =
'
ox '
=S = S  Cox .....(3.67)
t ox tox
 The aspect ration W/L of the MOSFET will remain
unchanged under scaling.
 The linear mode drain current of the scaled MOSFET can
now be found as:
kn'
I (lin) =  [2  (VGS
'
D
'
− VT' )  VDS
'
− VDS
'2
]
2
S  kn 1 I (lin)
I D' (lin) =  2  [2  (VGS − VT )  VDS − VDS
2
]= D .....(3.68)
85 CC: Dr Robinson Paul2 S
| BVM EC S 7/27/2022
 MOSFET scaling and small-geometry
effects
 Similarly, the saturation-mode drain current is also reduced
by the same scaling factor.

k '
S  kn 1 I D ( sat )
I ( sat ) =  (VGS − VT ) =
'
D
' n ' 2
 2  (VGS − VT ) =
2
.....(3.69)
2 2 S S
 The instantaneous power dissipated by the device before
scaling can be found as:

P = I D VDS .....(3.70)
86 CC: Dr Robinson Paul | BVM EC 7/27/2022
 MOSFET scaling and small-geometry
effects
 Notice that full scaling reduces both the drain current and
the drain to source voltage by factor of S; the power
dissipation of the transistor will be reduced by the factor
S^2.
1 P
P = I V
' '
D
'
DS = 2  I D  VDS = 2 .....(3.71)
S S
 This significant reeducation of the power dissipation is one of
the most attractive features of full scaling.
 This scaling also affect the capacitance of the MOSFET .

87 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET scaling and small-geometry
effects

88 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET scaling and small-geometry
effects
 ConstantVoltage scaling
 In constant voltage scaling, all dimensions of the MOSFET
are reduced by a factor of S, as in full scaling.
 The power supply voltage and the terminal voltages remain
unchanged.
 Under this scaling the device characteristics are significantly
different compare to those in full scaling.
 The linear mode drain current can be written as,

89 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET scaling and small-geometry
effects
 The drain current ,

 Also, the saturation mode drain current will be increased by

a factor of S after constant voltage scaling,

90 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET scaling and small-geometry
effects
 Since the drain current is increased by a factor of S while the
drain to source voltage remains unchanged, the power
dissipation of the MOSFET increases by a factor of S.

91 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET scaling and small-geometry
effects
 We can see the effect after scaling on other parameters also,

 Constant voltage scaling may be preferred over full scaling in

many practical cases because of the external voltage level
constraints.

92 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET scaling and small-geometry
effects
 But in constant voltage scaling, large increase in current and
power density may eventually causes serious reliability
problems for the scaled transistor, such as electro migration,
hot carrier degradation, oxide breakdown, and electrical
over stress.
 Due to this scaling, the current equations have to be modified
accordingly. In the following, we will briefly investigate some
of these small geometry effects.

93 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET scaling and small-geometry
effects
 Short Channel Effects:
 As a working definition, a MOS transistor is called a short
channel device if its channel length is on the same order of
magnitude as the depletion region thicknesses of the source
and drain junction.
 The short channel effects that arise in this case are attributed
to two physical phenomena, (i) the limitations imposed on
electron drift characteristics in the channel,
 (ii) the modification of the threshold voltage due to the
shortening channel length.

94 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET scaling and small-geometry
effects
 Not that the lateral electric field Ey along the channel
increases, as the effective channel length is decreased.
 The effective channel length Leff will be reduced due to
channel length shortening.

 Since the channel end voltage is equal to saturation drain

voltage , the saturation current can be found a follows;

95 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 In order to examine the transient (AC) response of
MOSFETs and digital circuits consisting of MOSFETs, we
have to determine the nature and the amount of parasitic
capacitances associates with the MOS transistor.
 Most of the capacitances in MOS are not Lumped but are
distributed,
 Here in figure 3.29 shows the top view and cross sectional
view of the n channel MOSFET.

96 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances

97 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 We are studying the parasitic device capacitances, we will
have to become more familiar with the top view of the
MOSFET.
 From the diagram we can able to get the actual
length(channel length can be calculated)

 The typical diffusion region length is denoted by Y as shown

in figure 3.29.

98 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 The p+ (channel stop region) is to prevent the formation of
any unwanted (parasitic) channels between the neighboring
n+ diffusion regions.
 We will identify the parasitic capacitances associated with this
typical MOSFET structure as lumped equivalent capacitances
observed between the device terminals. (figure.3.30)
 Basically these capacitances are classified in two groups, (1)
oxide related capacitances and (2) Junction capacitances.

99 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances

100 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 The two overlap capacitances that arise as a result of this
structural arrangement are,

 WhereW is source and drain diffusion region width.

 These both the capacitances are not depending on the bias
conditions, they are voltage independent,

101 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 Now, If we consider the three mode of the MOSFETs,
starting with the cut off mode, the surface is not inverted.
 Consequently, there is not conducting channel that links the
surface to source and to the drain. So we get Cgs=Cgd=0.
 And the gate to substrate capacitance can be approximated by

 For more understanding, see the diagram number 3.31(a)

102 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances

103 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 Now, in a linear mode, the inverted channel extends across
the MOSFET,
 This conducting inversion layer on the surface effectively
shields the substrate from the gate electric field; thus Cgb=0.
 In this case we can able to get,

 This can be seen in the figure 3.31(b)

104 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances

105 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 Now , when operating in the saturation mode, since the
source is still linked to the conducting channel, we get
Cgb=0, and finally we get the approximated value is

 The diagram shows the effect on capacitance while in

saturation mode(figure 3.31_C)

106 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances

107 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 The table 3.6 shows the summery of the approximate oxide
capacitance values in three different operating modes of the
MOSFET.

108 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 The variation of the distributed parasitic oxide capacitances
as functions of the gate to source voltage is also shown in fig.
3.32

109 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 We have to combine the distributed Cgs and Cgd.
 The sum of all voltage dependent gate oxide capacitances
( Cgb+Cgs+Cgd) has a minimum value in saturation mode and
maximum value in cut off and linear mode.
For simple calculations, where all three capacitances can be
considered to be connected in parallel, we can use the below
value as a sum of all the gate oxide capacitances of MOSFET.

110 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 Junction capacitances
 Now, we consider the voltage dependent source – substrate
and drain substrate junction capacitances, Csb and Cdb
respectively.
 The calculation of the associated junction capacitances is
complicated by the three dimensional shape of the diffusion
region that form the source substrate and the drain substrate
junction as shown in figure 3.33.

111 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances

112 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 Table 3.7 shows the all 5 junction capacitance area and type,

113 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 To calculate depletion capacitance of a reverse biased abrupt
pn junction, consider first the depletion region thickness Xd,
and reverse bias voltage V, we get, Xd is

 Where the built in junction potential is calculated as,

114 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 Note that the junction is forward biased for a positive bias
voltage V, and reverse bias for the negative voltage V. The
depletion region charge stored can be written as ,

 Here, A indicates the junction area. The junction capacitance

associated with the depletion region is defined as

115 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 By differentiating equation 3.101with respect to bias voltage
V, we can now obtain the junction capacitance,

 This equation can be rewritten in a more general form,

116 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 The parameter “m” in eq 3.104 is called the grading
coefficient. Its value is equal to ½ for an abrupt junction, and
1/3 for a linear graded junction profile.
 The zero bias junction capacitance per unit area is defined by

 The problem of estimating capacitance values under changing

bias conditions can be simplified, if we calculate a large signal
average junction capacitance instead.

117 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 The equivalent large signal capacitance can be defined as
follows:

 By substituting 3.104 to 3.106, we get

118 CC: Dr Robinson Paul | BVM EC 7/27/2022

 MOSFET Capacitances
 For a special case of abrupt pn-junctions the equation
becomes

 This equation can be rewritten in as simpler form by finding

a dimensionless coefficient as follows,

119 CC: Dr Robinson Paul | BVM EC 7/27/2022

 Outcomes
 From this unit, the understanding of the Electrical behavior
of MOSFET become clear. The more focus on the variations
of the voltages and its effects on current and power as well as
the changes in the capacitances of the MOSFETs are also
become more clear.
 The electrical behavior can be understood in three of the
MOSFET modes named cut-off, linear and saturation.

120 CC: Dr Robinson Paul | BVM EC 7/27/2022

 References
 Book: CMOS Digital Integrated Circuit Design - Analysis and
Design by S.M. Kang andY. Leblebici.

121 CC: Dr Robinson Paul | BVM EC 7/27/2022