COMPUTER ARCHITECTURE

Computer Architecture
What is a Digital Computer?
A device capable of solving problems by processing information in discrete
form. It operates on data, including magnitudes, letters, and symbols, that are
expressed in binary code—i.e., using only the two digits 0 and 1.

By using various coding techniques, groups of bits can be made to represent

numbers and discrete symbols such as decimal digits or letters of the
alphabet.

By judicious use of binary arrangements and various coding techniques, the

group of bits are used to develop complete sets of instructions for performing
various types of instructions.

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 Block Diagram of a Digital Computer

Hardware Software

Computer Architecture
Computer Organisation is concerned with the way the hardware components
operate and the way they are connected together to form the computer.

Computer Design is concerned with the hardware design. It is concerned with

what hardware should be used and how the parts to be connected together -
Computer Implementation

Computer Architecture – Structure and behaviour of the system as seen by the

user

Computer Architecture
 Types of Architecture

• Von Neumann Architecture [Princeton Architecture]

• Harvard Architecture

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Von Neumann Architecture

• John von Neumann in 1945.

• Based on the stored-program computer concept, where instruction data and program data
are stored in the same memory. ...
• This design is still used in most computers produced today.

An electronic digital computer with these components

• A processing unit that contains an arithmetic logic unit and processor registers
• A control unit that contains an instruction register and program counter
• Memory that stores data and instructions
• External mass storage
• Input and output mechanisms

A stored-program digital computer keeps both program instructions and data in read–write, RAM.

Computer Architecture
Computer Architecture
Computer Architecture
UNIT 1: Computer Organization and Design
Instruction codes - Stored program organization; Computer registers; Computer instruction; Instruction
cycle-Fetch and decode; Input output and interrupt; I-O instructions; Program interrupt; Basic design of
computer.

BASIC COMPUTER ORGANIZATION AND DESIGN

MAIN TOPICS
• Instruction Codes
• Computer Registers
• Computer Instructions This unit explains the design of a basic but complete CPU with a much
• Timing and Control simpler design than any real-world processors available.
• Instruction Cycle
• Memory Reference Instructions The basic computer design represents all of the major concepts in CPU
• Input-Output and Interrupt design without complicating students with the complexity of a modern
• Complete Computer Description commercial CPU.
• Design of Basic Computer
• Design of Accumulator Logic

Computer Architecture
Instruction Codes
An instruction code is a group of bits that instruct the computer to perform a specific task.
It is usually divided into parts, each having its own particular interpretation.

They are:
•Operation Code or opcode
•Operands (in register /in address location)

The most basic part of an instruction code is its operation part.

Eg: - Add R1, R2, R3

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Computer Architecture
 A part of a C program
// Assuming the contents represented by variable i
is in address 2500

Scanf(“%d” ,& i) ;
K = i + j; MOV R1 ,2500 // Storing content to a memory
location

Add R3 , R2 , R1 //Adding the contents of R2 and

R1 and storing that in R3.

Here ,

Add is the opcode

R3, R2 and R1 are in the operand field

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 Sample assembly
language program

Computer Architecture
 Computer Instructions

Computer instructions are the basic components of a machine language program.

They are also known as macro operations, since each one is comprised of a sequence of
microoperations

Each instruction initiates a sequence of microoperations that fetch operands from registers or memory,
possibly perform arithmetic, logic, or shift operations, and store results in registers or memory.

Computer Architecture
Instructions are encoded as binary instruction codes.
Each instruction code contains of a operation code, or opcode, which designates the overall
purpose of the instruction (e.g. add, subtract, move, input, etc.).
The number of bits allocated for the opcode determined how many different instructions the
architecture supports.
The control unit is responsible for decoding the opcode and operand bits in the instruction
register, and then generating the control signals necessary to drive all other hardware in the
CPU to perform the sequence of micro-operations that comprise the instruction.
The opcode must consist of at least n bits for a given 2n or less distinct operations

Computer Architecture
Understanding the powers of 2

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STORED PROGRAM ORGANIZATION
DIRECT AND INDIRECT ADDRESSING

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Stored Program Organization
The operands are specified by indicating the registers and/or memory locations in which they are
stored.

– k bits can be used to specify which of 2 pow K registers (or memory locations) are to be used.

• The simplest design is to have one processor register

(called the accumulator) and two fields in the instruction,
one for the opcode and one for the operand.

• Any operation that does not need a memory operand frees

the other bits to be used for other purposes, such as
specifying different operations.

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Computer Architecture
 INTRODUCTION
• Every different processor type has its own design (different registers, buses, microoperations, machine
instructions, etc)
• Modern processor is a very complex device
• It contains
• Many registers
• Multiple arithmetic units, for both integer and floating point calculations
• The ability to pipeline several consecutive instructions to speed execution
• Etc.
• However, to understand how processors work, we will start with a simplified processor model
• This is similar to what real processors were like ~25 years ago
• M. Morris Mano introduces a simple processor model he calls the Basic Computer
• We will use this to introduce processor organization and the relationship of the RTL model to the higher
level computer processor
[In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit
in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those
signals.]

Computer Architecture
 THE BASIC COMPUTER

• The Basic Computer has two components, a processor and memory

• The memory has 4096 words in it
• 4096 = 212, so it takes 12 bits to select a word in memory
• Each word is 16 bits long
CPU RAM
0

15 0

4095

Computer Architecture
 Instruction codes

INSTRUCTIONS

• Program
- A sequence of (machine) instructions
• Machine Instruction
- A group of bits that tell the computer to perform a specific operation (a
sequence of micro-operation)
• The instructions of a program, along with any needed data are stored in
memory
• The CPU reads the each instruction from memory
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates the instruction into the
sequence of microoperations necessary to implement it

Computer Architecture
 Instruction codes
INSTRUCTION FORMAT
• A computer instruction is often divided into two parts
• An opcode (Operation Code) that specifies the operation for that instruction
• An address that specifies the registers and/or locations in memory to use for that operation
• In the Basic Computer, since the memory contains 4096 (= 212) words, we needs 12 bit to
specify which memory address this instruction will use
• In the Basic Computer, bit 15 of the instruction specifies the addressing mode (0: direct
addressing, 1: indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits long, that leaves 3 bits for the
instruction’s opcode

Computer Architecture
Addressing Modes
•There are four different types of operands
that can appear in an instruction:

– Direct operand - an operand stored in the register or in the memory location

specified.
– Indirect operand - an operand whose address is stored in the register or in the
memory location specified.
– Immediate operand - an operand whose value
is specified in the instruction.

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Computer Architecture
 Registers
Computer instructions are stored in consecutive locations and are executed
sequentially; this requires a register which can track the address of the next
instruction;
we call it the Program Counter.

We need registers which can hold the address at which a memory operand is
stored as well as the value itself.

We need a place where we can store

– temporary data
– the instruction being executed,
– a character being read in
– a character being written out.

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Computer Architecture
Computer Architecture
 The Common Bus System

To avoid excessive wiring, memory and all the register are connected via a common bus.

 The specific output that is selected for the bus is determined by S2 S1 S0

 The register whose LD (Load) is enable receives the data from the bus.

 Registers can be incremented by setting the INR control

 input and can be cleared by setting the CLR control input.

 The Accumulator’s input must come via the Adder & Logic Circuit. This allows the Accumulator and Data
Register to swap data simultaneously.

 The address of any memory location being accessed must be loaded in the Address Register.

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Computer Architecture
Computer Instructions
• The basic computer has three instruction code formats:

– Memory-reference format – where seven 3-bit opcodes are followed by a 12-bit

memory address and preceded by a bit which indicates whether direct or indirect
addressing is being used.

– Register-reference format – where 01112 is followed by 12 bits which indicate a

register instruction.

– Input-output format – where 11112 is followed by 12bit which indicate an input-

output instruction.

• In register-reference and I/O formats, only one of the lower 12 bits is set.

Computer Architecture
Memory-reference Instructions
The basic computer has 16-bit instruction register (IR) which can denote either memory
reference or register reference or input-output instruction.

Memory Reference – These instructions refer to memory address as an operand. The other
operand is always accumulator. Specifies 12-bit address, 3-bit opcode (other than 111) and 1-
bit addressing mode for direct and indirect addressing.

Computer Architecture
 Computer Instructions - 1. Memory Reference type
4 bits 3 sets of 4 bits

0 or 1 X X X 12 bit Memory Address

0 0 0
0 0 1
0 1 0
1 0 0
1 0 1
1 1 0

Example –
if the IR register contains = 0001 XXXX XXXX XXXX, i.e. ADD after fetching and decoding of instruction we find out that
it is a memory reference instruction for ADD operation.

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Computer Architecture
2. Register Reference –
• These instructions perform operations on registers rather than memory
addresses. The IR(14 – 12) is 111 (differentiates it from memory reference) and
IR(15) is 0 (differentiates it from input/output instructions). The rest 12 bits
specify register operation.

IR register contains = 0111001000000000, i.e. CMA after fetch and decode cycle we find out that it is a
register reference instruction for complement accumulator.

Computer Architecture
CLA 7800 Clear AC

CLE 7400 Clear E(overflow bit)

CMA 7200 Complement AC

REGISTER TRANSFER
CME 7100 Complement E
INSTRUCTIONS
CIR 7080 Circulate right AC and E

CIL 7040 Circulate left AC and E

INC 7020 Increment AC

SPA 7010 Skip next instruction if AC > 0

SNA 7008 Skip next instruction if AC < 0

SZA 7004 Skip next instruction if AC = 0

SZE 7002 Skip next instruction if E = 0

HLT 7001 Halt computer

Computer Architecture
3. Input/Output – These instructions are for communication between computer and outside
environment. The IR(14 – 12) is 111 (differentiates it from memory reference) and IR(15) is
1 (differentiates it from register reference instructions). The rest 12 bits specify I/O
operation.

Example –
IR register contains = 1111100000000000, i.e. INP after fetch and decode cycle we find
out that it is an input/output instruction for inputing character. Hence, INPUT character
from peripheral device.

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Computer Architecture
Instruction-Set Completeness
• A computer instruction set is said to be complete if the computer includes a
sufficient number of instructions in each of these categories:

– Arithmetic, logical and shift instructions

– Instructions for moving data from registers to memory and memory to registers.
– Program-control and status-checking instructions
– Input and output instructions

• We can perform moves using the LDA and STA instructions.

• We have unconditional branches (BUN), subprogram calls (BSA) and conditional
branches.
• We also have all the instructions we need to perform input and output and
handle the interrupt that they generate.
Computer Architecture
Instruction Set Completeness

• A set of instructions is said to be complete if the computer includes a sufficient number of instructions in
each of the following categories:
• Arithmetic, logical and shift instructions
• A set of instructions for moving information to and from memory and processor registers.
• Instructions which controls the program together with instructions that check status conditions.
• Input and Output instructions
• Arithmetic, logic and shift instructions provide computational capabilities for processing the type of data the
user may wish to employ.
• A huge amount of binary information is stored in the memory unit, but all computations are done in
processor registers. Therefore, one must possess the capability of moving information between these two
units.
• Program control instructions such as branch instructions are used change the sequence in which the
program is executed.
• Input and Output instructions act as an interface between the computer and the user. Programs and data
must be transferred into memory, and the results of computations must be transferred back to the user.

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 Timing and Control

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Timing and Control – Continued ..
• A Hard-wired Control consists of two decoders, a sequence counter, and a number of logic gates.
• An instruction fetched from the memory unit is placed in the instruction register (IR).
• The component of an instruction register includes; I bit, the operation code, and bits 0 through
11.
• The operation code in bits 12 through 14 are coded with a 3 x 8 decoder.
• The outputs of the decoder are designated by the symbols D0 through D7.
• The operation code at bit 15 is transferred to a flip-flop designated by the symbol I.
• The operation codes from Bits 0 through 11 are applied to the control logic gates.
• The Sequence counter (SC) can count in binary from 0 through 15.

Computer Architecture
 The last three waveforms in Fig. show
how SC is cleared when D3T4 = I.
Output D3 from the operation
decoder becomes active at the end of
timing signal T2

• When timing signal T4 becomes

active, the output of the AND gate
that implements the control function
D3T4 becomes active. This signal is
applied to the CLR input of SC.

Computer Architecture
 Instruction Cycle

A program residing in the memory unit of a computer consists of a

sequence of instructions.
These instructions are executed by the processor by going through a
cycle for each instruction.
In a basic computer, each instruction cycle consists of the following
phases:

1.Fetch instruction from memory.

2.Decode the instruction.
3.Read the effective address from memory.
4.Execute the instruction.

Computer Architecture
• The program is executed in the computer by going through a cycle for
each instruction.
• Upon the completion of step 4, the control goes back to step 1 to
fetch, decode, and execute the next instruction. This process
continues indefinitely unless a HALT instruction is encountered.

Computer Architecture
Instruction Cycle

• Initially, the program counter PC is loaded with the address of the first instruction in the program.
The sequence counter SC is cleared to 0, providing a decoded timing signal To.
• After each clock pulse, SC is incremented by one, so that the timing signals go through a sequence
T0, T1, T2, and so on. The microoperations for the fetch and decode phases can be specified by
the following register transfer statements.

• T0: AR <- PC
• T1: IR <-M[AR], PC <- PC + 1
• T2: D0, ••• , D7 <-Decode IR(12-14), AR <---IR(0-11), 1 <---IR(l5)
• Since only AR is connected to the address inputs of memory, it is necessary to transfer the
address from PC to AR during the clock transition associated with timing signal T0
• 1.The content of PC is placed onto the bus by setting the bus selection inputs S2S1S0 ie)010
• 2. The content of the bus is transferred to AR by enabling the LD input of AR

Computer Architecture
• To provide the data path for the
transfer of PC to IR, timing signal T1
is applied
• 1. The read input of memory is
enabled
• 2. the content of memory is placed
onto the bus by making s2s1s0 =111
• 3. The content of bus is transferred
to IR by enabling LD input of IR
• 4.
• PC is incremented by enabling the
INR input of PC

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Computer Architecture
Computer Architecture
Type of Instruction and Addressing
During time T3, the control unit determines if this is a memory-reference, register-
reference or input/output instruction.
If D7=1,then it should be register reference or I/O reference instruction depending
on I bit
-if D7 ≠0,it is a memory-reference instruction, opcode must be 000 through 011 the
I bit will determine direct or indirect addressing.

• The four separate paths are:

D7’IT3: AR ¬ M[AR]
D7’I’T3: Nothing
D7I’T3: Execute a register-reference instruction
D7IT3: Execute an input-output instruction

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Computer Architecture
COMPLETE COMPUTER DESCRIPTION

Fetch RT0: AR  PC
RT1: IR  M[AR], PC  PC + 1
Decode RT2: D0, ..., D7  Decode IR(12 ~ 14),
AR  IR(0 ~ 11), I  IR(15)
Indirect D7IT3: AR  M[AR]
Interrupt
T0T1T2(IEN)(FGI + FGO): R1
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
Memory-Reference
AND D0T4: DR  M[AR]
D0T5: AC  AC  DR, SC  0
ADD D1T4: DR  M[AR]
D1T5: AC  AC + DR, E  Cout, SC  0
LDA D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA D3T4: M[AR]  AC, SC  0
BUN D4T4: PC  AR, SC  0
BSA D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
ISZ D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if(DR=0) then (PC  PC + 1),
SC  0

Computer Architecture
COMPLETE COMPUTER DESCRIPTION Micro-operations

Register-Reference
D7IT3 = r (Common to all register-reference instr)
IR(i) = Bi (i = 0,1,2, ..., 11)
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC
CME rB8: E  E
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: If(AC(15) =0) then (PC  PC + 1)
SNA rB3: If(AC(15) =1) then (PC  PC + 1)
SZA rB2: If(AC = 0) then (PC  PC + 1)
SZE rB1: If(E=0) then (PC  PC + 1)
HLT rB0: S0

Input-Output D7IT3 = p (Common to all input-output instructions)

IR(i) = Bi (i = 6,7,8,9,10,11)
p: SC  0
INP pB11: AC(0-7)  INPR, FGI  0
OUT pB10: OUTR  AC(0-7), FGO  0
SKI pB9: If(FGI=1) then (PC  PC + 1)
SKO pB8: If(FGO=1) then (PC  PC + 1)
ION pB7: IEN  1
IOF pB6: IEN  0

Computer Architecture
 DESIGN OF BASIC COMPUTER
Hardware Components

• A basic computer consists of the following hardware components.

• A memory unit with 4096 words of 16 bits each
• 9 Registers: AC (Accumulator), DR (Data register), AR (Address register), IR
(Instruction register), PC (Program counter), TR (Temporary register), SC (Sequence
Counter), INPR (Input register), and OUTR (Output register).
• 7 Flip-Flops: I, S, E, R, IEN, FGI and FGO
Control Logic Gates
- Input Controls of the nine registers
- Read and Write Controls of memory
- Set, Clear, or Complement Controls of the flip-flops
- S2, S1, S0 Controls to select a register for the bus
- AC, and Adder and Logic circuit
Computer Architecture
 Design of Basic Computer

CONTROL OF REGISTERS AND MEMORY

Address Register; AR
Scan all of the register transfer statements that change the content of AR:
R’T0: AR  PC LD(AR)
R’T2: AR  IR(0-11) LD(AR)
D’7IT3: AR  M[AR] LD(AR)
RT0: AR  0 CLR(AR)
D5T4: AR  AR + 1 INR(AR)

LD(AR) = R'T0 + R'T2 + D'7IT3

CLR(AR) = RT0
INR(AR) = D5T4

12 12
From bus AR To bus
D'7
I
LD Clock
T3
T2 INR
CLR
R
T0
D
T4

Computer Architecture
 CONTROL OF FLAGS
IEN: Interrupt Enable Flag
pB7: IEN  1 (I/O Instruction)
pB6: IEN  0 (I/O Instruction)
RT2: IEN  0 (Interrupt)

p = D7IT3 (Input/Output Instruction)

D
7
p
I J IEN
Q
B7
T3

B6
K
R
T2

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 Design of ALU and AC -

Circuits associated with AC

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Instructions associated with AC

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