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47 views3 pages

Lec1 Q

Uploaded by

samehshehata830
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Lecture 1

Q: Consider a shared bus parallel computer built using 32 bit RISC processors running at 2 GHz which
carry out one instruction per clock cycle. Assume that 15% of the instructions are loads and 10% are
stores. Assume:

• 0.95 hit rate to cache for read and write through caches.
• The bandwidth of the bus is given as 20 GB/s.
• Each processor executes 2 billion cycles per second (2 GHz), with one instruction per cycle.

1. 1.How many processors can the bus support without getting saturated?
2. 2.If caches are not there how many processors can the bus support assuming the main memory
is as fast as the cache?

Solution:
In such a system, multiple processors share a common memory and access it via a shared
communication bus. Each processor has a local cache to reduce the frequency of memory accesses, as
cache hits don’t require bus usage. If there are too many processors, the bus may become saturated,
meaning it reaches its maximum data transfer capacity, which can limit the number of processors that
can be supported efficiently.
With cache
Number of processors which can be supported = the total bus bandwidth / Number of Transactions to
Main Memory (per Second) for a processor

1. Number of read Transactions to Main Memory


= reads percentage * cache miss rate * processor cycles per second
= 0.15 * 0.05 * (2 * 109) = 0.015 * 109 read transactions per second

• The problem assumes a write-through cache; hence, all stores go to memory directly. This
means all store instructions require bus access.
2. Number of write Transactions to Main Memory
= writes percentage * processor cycles per second
= 0.1 * (2 * 109) = 0.2 * 109 write transactions per second

3. Total Number of Transactions to Main Memory


= read Transactions + write Transactions
= = 0.015 * 109 + 0.2 * 109 = 0.215 * 109 Transaction per second

• as this is a 32-bit processor: Each transaction involves 4 bytes of data.


4. number of bytes traffic to memory per second
= Total Number of Transactions to Main Memory * 4
= 4 * 0.215 * 109= 0.86 * 109 byte/sec

5. Number of processors which can be supported


= the total bus bandwidth / Number of Transactions to Main Memory
= 20 * 109 byte per second / 0.86 * 109 = 23 processor.
Without Caches
we're assuming there are no caches, which means every load and store instruction requires access to
the main memory, significantly increasing the demand on the bus. With no caches, every load and store
instruction requires memory access.

1. Number of read Transactions to Main Memory


= reads percentage * processor cycles per second
= 0.15 * (2 * 109) = 0.3 * 109 read transactions per second

2. Number of write Transactions to Main Memory


= writes percentage * processor cycles per second
= 0.1 * (2 * 109) = 0.2 * 109 write transactions per second

3. Total Number of Transactions to Main Memory


= read Transactions + write Transactions
= = 0.3 * 109 + 0.2 * 109 = 0.5 * 109 Transaction per second

• as this is a 32-bit processor: Each transaction involves 4 bytes of data.


4. number of bytes traffic to memory per second
= Total Number of Transactions to Main Memory * 4
= 4 * 0.5 * 109= 2 * 109 byte/sec

5. Number of processors which can be supported


= the total bus bandwidth / Number of Transactions to Main Memory
= 20 * 109 byte per second / 2 * 109 = 10 processors

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