Digital Modulation

CHAPTER OUTLINE

1 Introduction 7 Bandwidth Efficiency

2 Information Capacity, Bits, Bit Rate, Baud, and 8 Carrier Recovery
M-ary Encoding 9 Clock Recovery
3 Amplitude-Shift Keying 10 Differential Phase-Shift Keying
4 Frequency-Shift Keying 11 Trellis Code Modulation
5 Phase-Shift Keying 12 Probability of Error and Bit Error Rate
6 Quadrature-Amplitude Modulation 13 Error Performance

OBJECTIVES

■ Define electronic communications ■ Describe 8- and 16-PSK

■ Define digital modulation and digital radio ■ Describe quadrature-amplitude modulation
■ Define digital communications ■ Explain 8-QAM
■ Define information capacity ■ Explain 16-QAM
■ Define bit, bit rate, baud, and minimum bandwidth ■ Define bandwidth efficiency
■ Explain Shannon’s limit for information capacity ■ Explain carrier recovery
■ Explain M-ary encoding ■ Explain clock recovery
■ Define and describe digital amplitude modulation ■ Define and describe differential phase-shift keying
■ Define and describe frequency-shift keying ■ Define and explain trellis-code modulation
■ Describe continuous-phase frequency-shift keying ■ Define probability of error and bit error rate
■ Define phase-shift keying ■ Develop error performance equations for FSK,
■ Explain binary phase-shift keying PSK, and QAM
■ Explain quaternary phase-shift keying

From Chapter 2 of Advanced Electronic Communications Systems, Sixth Edition. Wayne Tomasi.
Copyright © 2004 by Pearson Education, Inc. Published by Pearson Prentice Hall. All rights reserved.
49
 Digital Modulation

1 INTRODUCTION

In essence, electronic communications is the transmission, reception, and processing of in-

formation with the use of electronic circuits. Information is defined as knowledge or intel-
ligence that is communicated (i.e., transmitted or received) between two or more points.
Digital modulation is the transmittal of digitally modulated analog signals (carriers) be-
tween two or more points in a communications system. Digital modulation is sometimes
called digital radio because digitally modulated signals can be propagated through Earth’s
atmosphere and used in wireless communications systems. Traditional electronic commu-
nications systems that use conventional analog modulation, such as amplitude modulation
(AM), frequency modulation (FM), and phase modulation (PM), are rapidly being replaced
with more modern digital moduluation systems that offer several outstanding advantages
over traditional analog systems, such as ease of processing, ease of multiplexing, and noise
immunity.
Digital communications is a rather ambiguous term that could have entirely different
meanings to different people. In the context of this text, digital communications include
systems where relatively high-frequency analog carriers are modulated by relatively low-
frequency digital information signals (digital radio) and systems involving the transmission
of digital pulses (digital transmission). Digital transmission systems transport information
in digital form and, therefore, require a physical facility between the transmitter and re-
ceiver, such as a metallic wire pair, a coaxial cable, or an optical fiber cable. In digital ra-
dio systems, the carrier facility could be a physical cable, or it could be free space.
The property that distinguishes digital radio systems from conventional analog-
modulation communications systems is the nature of the modulating signal. Both analog
and digital modulation systems use analog carriers to transport the information through the
system. However, with analog modulation systems, the information signal is also analog,
whereas with digital modulation, the information signal is digital, which could be computer-
generated data or digitally encoded analog signals.
Referring to Equation 1, if the information signal is digital and the amplitude (V) of
the carrier is varied proportional to the information signal, a digitally modulated signal
called amplitude shift keying (ASK) is produced. If the frequency (f) is varied proportional
to the information signal, frequency shift keying (FSK) is produced, and if the phase of the
carrier (θ) is varied proportional to the information signal, phase shift keying (PSK) is pro-
duced. If both the amplitude and the phase are varied proportional to the information sig-
nal, quadrature amplitude modulation (QAM) results. ASK, FSK, PSK, and QAM are all
forms of digital modulation:
v(t) = V sin (2p . ƒt + U)

ASK FSK PSK

(1)
QAM

Digital modulation is ideally suited to a multitude of communications applications,

including both cable and wireless systems. Applications include the following: (1) rela-
tively low-speed voice-band data communications modems, such as those found in most
personal computers; (2) high-speed data transmission systems, such as broadband digital
subscriber lines (DSL); (3) digital microwave and satellite communications systems; and
(4) cellular telephone Personal Communications Systems (PCS).
Figure 1 shows a simplified block diagram for a digital modulation system. In the
transmitter, the precoder performs level conversion and then encodes the incoming data
into groups of bits that modulate an analog carrier. The modulated carrier is shaped (fil-

50
 Digital Modulation

FIGURE 1 Simplified block diagram of a digital radio system

tered), amplified, and then transmitted through the transmission medium to the receiver.
The transmission medium can be a metallic cable, optical fiber cable, Earth’s atmosphere,
or a combination of two or more types of transmission systems. In the receiver, the in-
coming signals are filtered, amplified, and then applied to the demodulator and decoder
circuits, which extracts the original source information from the modulated carrier. The
clock and carrier recovery circuits recover the analog carrier and digital timing (clock)
signals from the incoming modulated wave since they are necessary to perform the de-
modulation process.

2 INFORMATION CAPACITY, BITS, BIT RATE, BAUD,

AND M-ARY ENCODING

2-1 Information Capacity, Bits, and Bit Rate

Information theory is a highly theoretical study of the efficient use of bandwidth to propa-
gate information through electronic communications systems. Information theory can be
used to determine the information capacity of a data communications system. Information
capacity is a measure of how much information can be propagated through a communica-
tions system and is a function of bandwidth and transmission time.
Information capacity represents the number of independent symbols that can be car-
ried through a system in a given unit of time. The most basic digital symbol used to repre-
sent information is the binary digit, or bit. Therefore, it is often convenient to express the
information capacity of a system as a bit rate. Bit rate is simply the number of bits trans-
mitted during one second and is expressed in bits per second (bps).
In 1928, R. Hartley of Bell Telephone Laboratories developed a useful relationship
among bandwidth, transmission time, and information capacity. Simply stated, Hartley’s
law is
I∝Bt (2)
where I  information capacity (bits per second)
B  bandwidth (hertz)
t  transmission time (seconds)

51
 Digital Modulation

From Equation 2, it can be seen that information capacity is a linear function of band-
width and transmission time and is directly proportional to both. If either the bandwidth or
the transmission time changes, a directly proportional change occurs in the information ca-
pacity.
In 1948, mathematician Claude E. Shannon (also of Bell Telephone Laboratories)
published a paper in the Bell System Technical Journal relating the information capacity of
a communications channel to bandwidth and signal-to-noise ratio. The higher the signal-
to-noise ratio, the better the performance and the higher the information capacity. Mathe-
matically stated, the Shannon limit for information capacity is

S
I  B log2¢1  ≤ (3)
N

S
or I  3.32B log10 ¢1  ≤ (4)
N
where I  information capacity (bps)
B  bandwidth (hertz)
S
 signal-to-noise power ratio (unitless)
N
For a standard telephone circuit with a signal-to-noise power ratio of 1000 (30 dB)
and a bandwidth of 2.7 kHz, the Shannon limit for information capacity is
I  (3.32)(2700) log10 (1  1000)
 26.9 kbps

Shannon’s formula is often misunderstood. The results of the preceding example indi-
cate that 26.9 kbps can be propagated through a 2.7-kHz communications channel. This may
be true, but it cannot be done with a binary system. To achieve an information transmission
rate of 26.9 kbps through a 2.7-kHz channel, each symbol transmitted must contain more
than one bit.

2-2 M-ary Encoding

M-ary is a term derived from the word binary. M simply represents a digit that corresponds
to the number of conditions, levels, or combinations possible for a given number of binary
variables. It is often advantageous to encode at a level higher than binary (sometimes re-
ferred to as beyond binary or higher-than-binary encoding) where there are more than two
conditions possible. For example, a digital signal with four possible conditions (voltage lev-
els, frequencies, phases, and so on) is an M-ary system where M  4. If there are eight pos-
sible conditions, M  8 and so forth. The number of bits necessary to produce a given num-
ber of conditions is expressed mathematically as
N  log2 M (5)
where N  number of bits necessary
M  number of conditions, levels, or combinations possible with N bits
Equation 5 can be simplified and rearranged to express the number of conditions possible
with N bits as
2N  M (6)
For example, with one bit, only 21  2 conditions are possible. With two bits, 22  4 con-
ditions are possible, with three bits, 23  8 conditions are possible, and so on.

52
 Digital Modulation

2-3 Baud and Minimum Bandwidth

Baud is a term that is often misunderstood and commonly confused with bit rate (bps). Bit
rate refers to the rate of change of a digital information signal, which is usually binary.
Baud, like bit rate, is also a rate of change; however, baud refers to the rate of change of a
signal on the transmission medium after encoding and modulation have occurred. Hence,
baud is a unit of transmission rate, modulation rate, or symbol rate and, therefore, the terms
symbols per second and baud are often used interchangeably. Mathematically, baud is the
reciprocal of the time of one output signaling element, and a signaling element may repre-
sent several information bits. Baud is expressed as
1
baud  (7)
ts
where baud  symbol rate (baud per second)
ts  time of one signaling element (seconds)
A signaling element is sometimes called a symbol and could be encoded as a change in the
amplitude, frequency, or phase. For example, binary signals are generally encoded and
transmitted one bit at a time in the form of discrete voltage levels representing logic 1s
(highs) and logic 0s (lows). A baud is also transmitted one at a time; however, a baud may
represent more than one information bit. Thus, the baud of a data communications system
may be considerably less than the bit rate. In binary systems (such as binary FSK and bi-
nary PSK), baud and bits per second are equal. However, in higher-level systems (such as
QPSK and 8-PSK), bps is always greater than baud.
According to H. Nyquist, binary digital signals can be propagated through an ideal
noiseless transmission medium at a rate equal to two times the bandwidth of the medium.
The minimum theoretical bandwidth necessary to propagate a signal is called the minimum
Nyquist bandwidth or sometimes the minimum Nyquist frequency. Thus, fb  2B, where fb
is the bit rate in bps and B is the ideal Nyquist bandwidth. The actual bandwidth necessary
to propagate a given bit rate depends on several factors, including the type of encoding and
modulation used, the types of filters used, system noise, and desired error performance. The
ideal bandwidth is generally used for comparison purposes only.
The relationship between bandwidth and bit rate also applies to the opposite situation. For
a given bandwidth (B), the highest theoretical bit rate is 2B. For example, a standard telephone
circuit has a bandwidth of approximately 2700 Hz, which has the capacity to propagate
5400 bps through it. However, if more than two levels are used for signaling (higher-than-binary
encoding), more than one bit may be transmitted at a time, and it is possible to propagate a bit
rate that exceeds 2B. Using multilevel signaling, the Nyquist formulation for channel capacity is
fb  2B log2 M (8)
where fb  channel capacity (bps)
B  minimum Nyquist bandwidth (hertz)
M  number of discrete signal or voltage levels
Equation 8 can be rearranged to solve for the minimum bandwidth necessary to pass
M-ary digitally modulated carriers
fb
B¢ ≤ (9)
log2 M
If N is substituted for log2 M, Equation 9 reduces to
fb
B (10)
N
where N is the number of bits encoded into each signaling element.

53
 Digital Modulation

If information bits are encoded (grouped) and then converted to signals with more
than two levels, transmission rates in excess of 2B are possible, as will be seen in subse-
quent sections of this chapter. In addition, since baud is the encoded rate of change, it also
equals the bit rate divided by the number of bits encoded into one signaling element. Thus,
fb
baud  (11)
N
By comparing Equation 10 with Equation 11, it can be seen that with digital modu-
lation, the baud and the ideal minimum Nyquist bandwidth have the same value and are
equal to the bit rate divided by the number of bits encoded. This statement holds true for all
forms of digital modulation except frequency-shift keying.

3 AMPLITUDE-SHIFT KEYING

The simplest digital modulation technique is amplitude-shift keying (ASK), where a binary
information signal directly modulates the amplitude of an analog carrier. ASK is similar
to standard amplitude modulation except there are only two output amplitudes possible.
Amplitude-shift keying is sometimes called digital amplitude modulation (DAM). Mathe-
matically, amplitude-shift keying is

v1ask2 1t2  31  vm 1t2 4B cos1ct2R

A
(12)
2
where vask(t)  amplitude-shift keying wave
vm(t)  digital information (modulating) signal (volts)
A/2  unmodulated carrier amplitude (volts)
ωc  analog carrier radian frequency (radians per second, 2π fct)
In Equation 12, the modulating signal (vm[t]) is a normalized binary waveform, where 1
V  logic 1 and 1 V  logic 0. Therefore, for a logic 1 input, vm(t)  1 V, Equation 12 re-
duces to

v1ask2 1t2  31  14B cos1ct2R

A
2

 A cos1ct2
and for a logic 0 input, vm(t)  1 V, Equation 12 reduces to

v1ask2 1t2  31  1 4B cos1ct2R

A
2
0

Thus, the modulated wave vask(t), is either A cos(ωct) or 0. Hence, the carrier is either “on” or
“off,” which is why amplitude-shift keying is sometimes referred to as on-off keying (OOK).
Figure 2 shows the input and output waveforms from an ASK modulator. From the
figure, it can be seen that for every change in the input binary data stream, there is one
change in the ASK waveform, and the time of one bit (tb) equals the time of one analog sig-
naling element (ts). It is also important to note that for the entire time the binary input is high,
the output is a constant-amplitude, constant-frequency signal, and for the entire time the bi-
nary input is low, the carrier is off. The bit time is the reciprocal of the bit rate and the time
of one signaling element is the reciprocal of the baud. Therefore, the rate of change of the

54
 Digital Modulation

Binary
input

(a)

DAM
output
FIGURE 2 Digital amplitude modula-
tion: (a) input binary; (b) output DAM
(b) waveform

ASK waveform (baud) is the same as the rate of change of the binary input (bps); thus, the
bit rate equals the baud. With ASK, the bit rate is also equal to the minimum Nyquist band-
width. This can be verified by substituting into Equations 10 and 11 and setting N to 1:
fb fb
B  fb baud   fb
1 1

Example 1
Determine the baud and minimum bandwidth necessary to pass a 10 kbps binary signal using ampli-
tude shift keying.
Solution For ASK, N  1, and the baud and minimum bandwidth are determined from Equations
11 and 10, respectively:
10,000
B  10,000
1
10,000
baud   10,000
1
The use of amplitude-modulated analog carriers to transport digital information is a relatively
low-quality, low-cost type of digital modulation and, therefore, is seldom used except for very low-
speed telemetry circuits.

4 FREQUENCY-SHIFT KEYING

Frequency-shift keying (FSK) is another relatively simple, low-performance type of digital

modulation. FSK is a form of constant-amplitude angle modulation similar to standard fre-
quency modulation (FM) except the modulating signal is a binary signal that varies between
two discrete voltage levels rather than a continuously changing analog waveform. Conse-
quently, FSK is sometimes called binary FSK (BFSK). The general expression for FSK is
vfsk(t)  Vc cos{2π[fc  vm(t) f]t} (13)
where vfsk(t)  binary FSK waveform
Vc  peak analog carrier amplitude (volts)
fc  analog carrier center frequency (hertz)
f  peak change (shift) in the analog carrier frequency (hertz)
vm(t)  binary input (modulating) signal (volts)
From Equation 13, it can be seen that the peak shift in the carrier frequency (f) is
proportional to the amplitude of the binary input signal (vm[t]), and the direction of the shift

55
 Digital Modulation

–Δƒ +Δƒ

ƒs ƒc ƒm

Logic 1

Logic 0 Binary input FIGURE 3 FSK in the frequency

signal domain

is determined by the polarity. The modulating signal is a normalized binary waveform

where a logic 1  1 V and a logic 0  1 V. Thus, for a logic 1 input, vm(t)  1, Equa-
tion 13 can be rewritten as
vfsk(t)  Vc cos[2π(fc  f)t]
For a logic 0 input, vm(t)  1, Equation 13 becomes
vfsk(t)  Vc cos[2π(fc  f)t]
With binary FSK, the carrier center frequency (fc) is shifted (deviated) up and down
in the frequency domain by the binary input signal as shown in Figure 3. As the binary in-
put signal changes from a logic 0 to a logic 1 and vice versa, the output frequency shifts be-
tween two frequencies: a mark, or logic 1 frequency (fm), and a space, or logic 0 frequency
(fs). The mark and space frequencies are separated from the carrier frequency by the peak
frequency deviation (f) and from each other by 2 f.
With FSK, frequency deviation is defined as the difference between either the mark
or space frequency and the center frequency, or half the difference between the mark and
space frequencies. Frequency deviation is illustrated in Figure 3 and expressed mathemat-
ically as
冟 fm  fs冟
¢f  (14)
2
where f  frequency deviation (hertz)
|fm  fs|  absolute difference between the mark and space frequencies (hertz)
Figure 4a shows in the time domain the binary input to an FSK modulator and the cor-
responding FSK output. As the figure shows, when the binary input (fb) changes from a logic
1 to a logic 0 and vice versa, the FSK output frequency shifts from a mark (fm) to a space (fs)
frequency and vice versa. In Figure 4a, the mark frequency is the higher frequency (fc 
f), and the space frequency is the lower frequency (fc  f), although this relationship could
be just the opposite. Figure 4b shows the truth table for a binary FSK modulator. The truth
table shows the input and output possibilities for a given digital modulation scheme.

4-1 FSK Bit Rate, Baud, and Bandwidth

In Figure 4a, it can be seen that the time of one bit (tb) is the same as the time the FSK out-
put is a mark of space frequency (ts). Thus, the bit time equals the time of an FSK signal-
ing element, and the bit rate equals the baud.

56
 Digital Modulation

tb
Binary
input 0 1 0 1 0 1 0 1 0 1 0

ts
binary frequency
Analog input output
output
ƒs ƒm ƒs ƒm ƒs ƒm ƒs ƒm ƒs ƒm ƒs 0 space (fs)
1 mark (fm)
ƒm , mark frequency; ƒs space frequency

(a) (b)

FIGURE 4 FSK in the time domain: (a) waveform; (b) truth table

The baud for binary FSK can also be determined by substituting N  1 in Equa-
tion 11:
fb
baud   fb
1
FSK is the exception to the rule for digital modulation, as the minimum bandwidth is
not determined from Equation 10. The minimum bandwidth for FSK is given as
B  |( fs  fb)  ( fm  fb)|
 |fs  fm|  2 fb
and since |fs  fm| equals 2f, the minimum bandwidth can be approximated as
B  2(f  fb) (15)
where B  minimum Nyquist bandwidth (hertz)
f  frequency deviation (|fm  fs|) (hertz)
fb  input bit rate (bps)
Note how closely Equation 15 resembles Carson’s rule for determining the approxi-
mate bandwidth for an FM wave. The only difference in the two equations is that, for FSK,
the bit rate (fb) is substituted for the modulating-signal frequency (fm).
Example 2
Determine (a) the peak frequency deviation, (b) minimum bandwidth, and (c) baud for a binary FSK
signal with a mark frequency of 49 kHz, a space frequency of 51 kHz, and an input bit rate of 2 kbps.
Solution a. The peak frequency deviation is determined from Equation 14:
冟49kHz  51kHz冟
¢f 
2
 1 kHz
b. The minimum bandwidth is determined from Equation 15:
B  2(1000  2000)
 6 kHz
c. For FSK, N  1, and the baud is determined from Equation 11 as

2000
baud   2000
1

57
 Digital Modulation

Bessel functions can also be used to determine the approximate bandwidth for an
FSK wave. As shown in Figure 5, the fastest rate of change (highest fundamental frequency)
in a nonreturn-to-zero (NRZ) binary signal occurs when alternating 1s and 0s are occurring
(i.e., a square wave). Since it takes a high and a low to produce a cycle, the highest funda-
mental frequency present in a square wave equals the repetition rate of the square wave,
which with a binary signal is equal to half the bit rate. Therefore,
fb
fa  (16)
2
where fa  highest fundamental frequency of the binary input signal (hertz)
fb  input bit rate (bps)
The formula used for modulation index in FM is also valid for FSK; thus,

¢f
h 1unitless2 (17)
fa
where h  FM modulation index called the h-factor in FSK
fa  fundamental frequency of the binary modulating signal (hertz)
f  peak frequency deviation (hertz)
The worst-case modulation index (deviation ratio) is that which yields the widest band-
width. The worst-case or widest bandwidth occurs when both the frequency deviation and
the modulating-signal frequency are at their maximum values. As described earlier, the
peak frequency deviation in FSK is constant and always at its maximum value, and the
highest fundamental frequency is equal to half the incoming bit rate. Thus,
冟fm  fs冟

1unitless2
2
h
fb
2

冟fm  fs冟
or h (18)
fb

FIGURE 5 FSK modulator, tb, time of one bit = 1/fb; fm, mark frequency; fs, space
frequency; T1, period of shortest cycle; 1/T1, fundamental frequency of binary
square wave; fb, input bit rate (bps)

58
 Digital Modulation

where h  h-factor (unitless)

fm  mark frequency (hertz)
fs  space frequency (hertz)
fb  bit rate (bits per second)

Example 3
Using a Bessel table, determine the minimum bandwidth for the same FSK signal described in Exam-
ple 1 with a mark frequency of 49 kHz, a space frequency of 51 kHz, and an input bit rate of 2 kbps.
Solution The modulation index is found by substituting into Equation 17:
冟49 kHz  51 kHz冟
or h
2 kbps
2 kHz

2 kbps
1
From a Bessel table, three sets of significant sidebands are produced for a modulation index of
one. Therefore, the bandwidth can be determined as follows:
B  2(3  1000)
 6000 Hz
The bandwidth determined in Example 3 using the Bessel table is identical to the bandwidth
determined in Example 2.

4-2 FSK Transmitter

Figure 6 shows a simplified binary FSK modulator, which is very similar to a conventional
FM modulator and is very often a voltage-controlled oscillator (VCO). The center fre-
quency (fc) is chosen such that it falls halfway between the mark and space frequencies. A
logic 1 input shifts the VCO output to the mark frequency, and a logic 0 input shifts the VCO
output to the space frequency. Consequently, as the binary input signal changes back and
forth between logic 1 and logic 0 conditions, the VCO output shifts or deviates back and
forth between the mark and space frequencies.
In a binary FSK modulator, f is the peak frequency deviation of the carrier and is
equal to the difference between the carrier rest frequency and either the mark or the space
frequency (or half the difference between the carrier rest frequency) and either the mark or
the space frequency (or half the difference between the mark and space frequencies). A VCO-
FSK modulator can be operated in the sweep mode where the peak frequency deviation is

NRZ FSK output

binary FSK Modulator
input (VCO)
k1 = Hz/v

–Δƒ +Δƒ

ƒm ƒc ƒs

Logic 0
Logic 1

FIGURE 6 FSK modulator

59
 Digital Modulation

FIGURE 7 Noncoherent FSK demodulator

FIGURE 8 Coherent FSK demodulator

simply the product of the binary input voltage and the deviation sensitivity of the VCO. With
the sweep mode of modulation, the frequency deviation is expressed mathematically as
f  vm(t)kl (19)
where f  peak frequency deviation (hertz)
vm(t)  peak binary modulating-signal voltage (volts)
kl  deviation sensitivity (hertz per volt).
With binary FSK, the amplitude of the input signal can only be one of two values, one
for a logic 1 condition and one for a logic 0 condition. Therefore, the peak frequency devi-
ation is constant and always at its maximum value. Frequency deviation is simply plus or
minus the peak voltage of the binary signal times the deviation sensitivity of the VCO. Since
the peak voltage is the same for a logic 1 as it is for a logic 0, the magnitude of the frequency
deviation is also the same for a logic 1 as it is for a logic 0.

4-3 FSK Receiver

FSK demodulation is quite simple with a circuit such as the one shown in Figure 7. The
FSK input signal is simultaneously applied to the inputs of both bandpass filters (BPFs)
through a power splitter. The respective filter passes only the mark or only the space fre-
quency on to its respective envelope detector. The envelope detectors, in turn, indicate the
total power in each passband, and the comparator responds to the largest of the two pow-
ers. This type of FSK detection is referred to as noncoherent detection; there is no frequency
involved in the demodulation process that is synchronized either in phase, frequency, or
both with the incoming FSK signal.
Figure 8 shows the block diagram for a coherent FSK receiver. The incoming FSK sig-
nal is multiplied by a recovered carrier signal that has the exact same frequency and phase as
the transmitter reference. However, the two transmitted frequencies (the mark and space fre-
quencies) are not generally continuous; it is not practical to reproduce a local reference that
is coherent with both of them. Consequently, coherent FSK detection is seldom used.

60
 Digital Modulation

FIGURE 9 PLL-FSK demodulator

FIGURE 10 Noncontinuous FSK

waveform

The most common circuit used for demodulating binary FSK signals is the phase-
locked loop (PLL), which is shown in block diagram form in Figure 9. A PLL-FSK de-
modulator works similarly to a PLL-FM demodulator. As the input to the PLL shifts be-
tween the mark and space frequencies, the dc error voltage at the output of the phase
comparator follows the frequency shift. Because there are only two input frequencies (mark
and space), there are also only two output error voltages. One represents a logic 1 and the
other a logic 0. Therefore, the output is a two-level (binary) representation of the FSK in-
put. Generally, the natural frequency of the PLL is made equal to the center frequency of
the FSK modulator. As a result, the changes in the dc error voltage follow the changes in
the analog input frequency and are symmetrical around 0 V.
Binary FSK has a poorer error performance than PSK or QAM and, consequently, is sel-
dom used for high-performance digital radio systems. Its use is restricted to low-performance,
low-cost, asynchronous data modems that are used for data communications over analog,
voice-band telephone lines.
4-4 Continuous-Phase Frequency-Shift Keying
Continuous-phase frequency-shift keying (CP-FSK) is binary FSK except the mark and
space frequencies are synchronized with the input binary bit rate. Synchronous simply im-
plies that there is a precise time relationship between the two; it does not mean they are equal.
With CP-FSK, the mark and space frequencies are selected such that they are separated from
the center frequency by an exact multiple of one-half the bit rate (fm and fs  n[fb /2]), where
n  any integer). This ensures a smooth phase transition in the analog output signal when it
changes from a mark to a space frequency or vice versa. Figure 10 shows a noncontinuous
FSK waveform. It can be seen that when the input changes from a logic 1 to a logic 0 and
vice versa, there is an abrupt phase discontinuity in the analog signal. When this occurs, the
demodulator has trouble following the frequency shift; consequently, an error may occur.
Figure 11 shows a continuous phase FSK waveform. Notice that when the output fre-
quency changes, it is a smooth, continuous transition. Consequently, there are no phase dis-
continuities. CP-FSK has a better bit-error performance than conventional binary FSK for
a given signal-to-noise ratio. The disadvantage of CP-FSK is that it requires synchroniza-
tion circuits and is, therefore, more expensive to implement.

61
 Digital Modulation

FIGURE 11 Continuous-phase MSK waveform

5 PHASE-SHIFT KEYING

Phase-shift keying (PSK) is another form of angle-modulated, constant-amplitude digital

modulation. PSK is an M-ary digital modulation scheme similar to conventional phase
modulation except with PSK the input is a binary digital signal and there are a limited num-
ber of output phases possible. The input binary information is encoded into groups of bits
before modulating the carrier. The number of bits in a group ranges from 1 to 12 or more.
The number of output phases is defined by M as described in Equation 6 and determined by
the number of bits in the group (n).

5-1 Binary Phase-Shift Keying

The simplest form of PSK is binary phase-shift keying (BPSK), where N  1 and M  2.
Therefore, with BPSK, two phases (21  2) are possible for the carrier. One phase repre-
sents a logic 1, and the other phase represents a logic 0. As the input digital signal changes
state (i.e., from a 1 to a 0 or from a 0 to a 1), the phase of the output carrier shifts between
two angles that are separated by 180°. Hence, other names for BPSK are phase reversal key-
ing (PRK) and biphase modulation. BPSK is a form of square-wave modulation of a
continuous wave (CW) signal.

5-1-1 BPSK transmitter. Figure 12 shows a simplified block diagram of a BPSK

transmitter. The balanced modulator acts as a phase reversing switch. Depending on the

+v +v
o –v

Binary Level
data Balanced Bandpass Modulated
converter
in modulator filter PSK output
(UP to BP)

sin(ωct)

Buffer

sin(ωct)

Reference
carrier
oscillator

FIGURE 12 BPSK transmitter

62
 Digital Modulation

FIGURE 13 (a) Balanced ring modulator; (b) logic 1 input; (c) logic O input

logic condition of the digital input, the carrier is transferred to the output either in phase or
180° out of phase with the reference carrier oscillator.
Figure 13 shows the schematic diagram of a balanced ring modulator. The balanced
modulator has two inputs: a carrier that is in phase with the reference oscillator and the bi-
nary digital data. For the balanced modulator to operate properly, the digital input voltage
must be much greater than the peak carrier voltage. This ensures that the digital input con-
trols the on/off state of diodes D1 to D4. If the binary input is a logic 1 (positive voltage),
diodes D1 and D2 are forward biased and on, while diodes D3 and D4 are reverse biased
and off (Figure 13b). With the polarities shown, the carrier voltage is developed across

63
 Digital Modulation

FIGURE 14 BPSK modulator: (a) truth table; (b) phasor

diagram; (c) constellation diagram

transformer T2 in phase with the carrier voltage across T1. Consequently, the output signal
is in phase with the reference oscillator.
If the binary input is a logic 0 (negative voltage), diodes D1 and D2 are reverse biased
and off, while diodes D3 and D4 are forward biased and on (Figure 13c). As a result, the car-
rier voltage is developed across transformer T2 180° out of phase with the carrier voltage
across T1. Consequently, the output signal is 180° out of phase with the reference oscillator.
Figure 14 shows the truth table, phasor diagram, and constellation diagram for a BPSK mod-
ulator. A constellation diagram, which is sometimes called a signal state-space diagram, is
similar to a phasor diagram except that the entire phasor is not drawn. In a constellation di-
agram, only the relative positions of the peaks of the phasors are shown.

5-1-2 Bandwidth considerations of BPSK. A balanced modulator is a product

modulator; the output signal is the product of the two input signals. In a BPSK modulator,
the carrier input signal is multiplied by the binary data. If 1 V is assigned to a logic 1 and
1 V is assigned to a logic 0, the input carrier (sin ωct) is multiplied by either a  or 1.
Consequently, the output signal is either 1 sin ωct or 1 sin ωct; the first represents a sig-
nal that is in phase with the reference oscillator, the latter a signal that is 180° out of phase
with the reference oscillator. Each time the input logic condition changes, the output phase
changes. Consequently, for BPSK, the output rate of change (baud) is equal to the input rate
of change (bps), and the widest output bandwidth occurs when the input binary data are an
alternating 1/0 sequence. The fundamental frequency ( fa) of an alternative 1/0 bit sequence
is equal to one-half of the bit rate ( fb/2). Mathematically, the output of a BPSK modulator
is proportional to
BPSK output  [sin(2πfat)]  [sin(2πfct)] (20)

64
 Digital Modulation

FIGURE 15 Output phase-versus-time relationship for a BPSK modulator

where fa  maximum fundamental frequency of binary input (hertz)

fc  reference carrier frequency (hertz)
Solving for the trig identity for the product of two sine functions,

cos32π1fc  fa 2t4  cos32π1fc  fa 2t4

1 1
2 2
Thus, the minimum double-sided Nyquist bandwidth (B) is

fc  fa fc  fa
1fc  fa 2 fc  fa
or
2fa
and because fa  fb/2, where fb  input bit rate,
2fb
B  fb
2
where B is the minimum double-sided Nyquist bandwidth.
Figure 15 shows the output phase-versus-time relationship for a BPSK waveform. As
the figure shows, a logic 1 input produces an analog output signal with a 0° phase angle,
and a logic 0 input produces an analog output signal with a 180° phase angle. As the binary
input shifts between a logic 1 and a logic 0 condition and vice versa, the phase of the BPSK
waveform shifts between 0° and 180°, respectively. For simplicity, only one cycle of the
analog carrier is shown in each signaling element, although there may be anywhere be-
tween a fraction of a cycle to several thousand cycles, depending on the relationship be-
tween the input bit rate and the analog carrier frequency. It can also be seen that the time of
one BPSK signaling element (ts) is equal to the time of one information bit (tb), which in-
dicates that the bit rate equals the baud.
Example 4
For a BPSK modulator with a carrier frequency of 70 MHz and an input bit rate of 10 Mbps, deter-
mine the maximum and minimum upper and lower side frequencies, draw the output spectrum, de-
termine the minimum Nyquist bandwidth, and calculate the baud.

65
 Digital Modulation

± sin(ωct) UP
BPSK Balanced Level Binary +v
BPF LPF data
input modulator converter o
output

sin(ωct)

Clock
recovery
Coherent
carrier
recovery

FIGURE 16 Block diagram of a BPSK receiver

Solution Substituting into Equation 20 yields

output  (sin ωat)(sin ωct)
 [sin 2π(5 MHz)t][sin 2π(70 MHz)t]

cos 2π 170 MHz  5 MHz 2t  cos 2π 170 MHz  5 MHz 2 t

1 1

2 2

冧
冧
lower side frequency upper side frequency

Minimum lower side frequency (LSF):

LSF  70 MHz  5 MHz  65 MHz
Maximum upper side frequency (USF):
USF  70 MHz  5 MHz  75 MHz
Therefore, the output spectrum for the worst-case binary input conditions is as follows:
The minimum Nyquist bandwidth (B) is

B  75 MHz  65 MHz  10 MHz

and the baud  fb or 10 megabaud.

5-1-3 BPSK receiver. Figure 16 shows the block diagram of a BPSK receiver. The
input signal may be sin ωct or sin ωct. The coherent carrier recovery circuit detects and
regenerates a carrier signal that is both frequency and phase coherent with the original
transmit carrier. The balanced modulator is a product detector; the output is the product of
the two inputs (the BPSK signal and the recovered carrier). The low-pass filter (LPF) sep-
arates the recovered binary data from the complex demodulated signal. Mathematically, the
demodulation process is as follows.
For a BPSK input signal of sin ωct (logic 1), the output of the balanced modulator is
output  (sin ωct)(sin ωct)  sin2 ωct (21)

66
 Digital Modulation

(filtered out)

sin2 ct  11  cos 2ct2   cos 2 ct

1 1 1
or
2 2 2
1
leaving output   V  logic 1
2
It can be seen that the output of the balanced modulator contains a positive voltage
([1/2]V) and a cosine wave at twice the carrier frequency (2 ωc) The LPF has a cutoff fre-
quency much lower than 2ωc and, thus, blocks the second harmonic of the carrier and
passes only the positive constant component. A positive voltage represents a demodulated
logic 1.
For a BPSK input signal of sin ωct (logic 0), the output of the balanced modulator is
output  (sin ωct)(sin ωct)  sin2 ωct
(filtered out)

sin2 ct   11  cos 2ct2    cos 2ct

1 1 1
or
2 2 2
1
leaving output   V  logic 0
2
The output of the balanced modulator contains a negative voltage ([1/2]V) and a
cosine wave at twice the carrier frequency (2ωc). Again, the LPF blocks the second har-
monic of the carrier and passes only the negative constant component. A negative voltage
represents a demodulated logic 0.

5-2 Quaternary Phase-Shift Keying

Quaternary phase shift keying (QPSK), or quadrature PSK as it is sometimes called, is an-
other form of angle-modulated, constant-amplitude digital modulation. QPSK is an M-ary
encoding scheme where N  2 and M  4 (hence, the name “quaternary” meaning “4”).
With QPSK, four output phases are possible for a single carrier frequency. Because there
are four output phases, there must be four different input conditions. Because the digital in-
put to a QPSK modulator is a binary (base 2) signal, to produce four different input com-
binations, the modulator requires more than a single input bit to determine the output con-
dition. With two bits, there are four possible conditions: 00, 01, 10, and 11. Therefore, with
QPSK, the binary input data are combined into groups of two bits, called dibits. In the mod-
ulator, each dibit code generates one of the four possible output phases (45°, 135°,
45°, and 135°). Therefore, for each two-bit dibit clocked into the modulator, a single
output change occurs, and the rate of change at the output (baud) is equal to one-half the
input bit rate (i.e., two input bits produce one output phase change).

5-2-1 QPSK transmitter. A block diagram of a QPSK modulator is shown in

Figure 17. Two bits (a dibit) are clocked into the bit splitter. After both bits have been seri-
ally inputted, they are simultaneously parallel outputted. One bit is directed to the I chan-
nel and the other to the Q channel. The I bit modulates a carrier that is in phase with the ref-
erence oscillator (hence the name “I” for “in phase” channel), and the Q bit modulates a
carrier that is 90° out of phase or in quadrature with the reference carrier (hence the name
“Q” for “quadrature” channel).
It can be seen that once a dibit has been split into the I and Q channels, the operation
is the same as in a BPSK modulator. Essentially, a QPSK modulator is two BPSK modula-
tors combined in parallel. Again, for a logic 1  1 V and a logic 0  1 V, two phases
are possible at the output of the I balanced modulator (sin ωct and sin ωct), and two

67
 Digital Modulation

FIGURE 17 QPSK modulator

phases are possible at the output of the Q balanced modulator (cos ωct and cos ωct).
When the linear summer combines the two quadrature (90° out of phase) signals, there
are four possible resultant phasors given by these expressions:  sin ωct  cos ωct,  sin
ωct  cos ωct, sin ωct  cos ωct, and sin ωct  cos ωct.

Example 5
For the QPSK modulator shown in Figure 17, construct the truth table, phasor diagram, and constel-
lation diagram.
Solution For a binary data input of Q  0 and I  0, the two inputs to the I balanced modulator are
1 and sin ωct, and the two inputs to the Q balanced modulator are 1 and cos ωct. Consequently,
the outputs are
I balanced modulator  (1)(sin ωct)  1 sin ωct
Q balanced modulator  (1)(cos ωct)  1 cos ωct
and the output of the linear summer is
1 cos ωct  1 sin ωct  1.414 sin(ωct  135°)
For the remaining dibit codes (01, 10, and 11), the procedure is the same. The results are shown in
Figure 18a.

In Figures 18b and c, it can be seen that with QPSK each of the four possible output
phasors has exactly the same amplitude. Therefore, the binary information must be encoded
entirely in the phase of the output signal. This constant amplitude characteristic is the most
important characteristic of PSK that distinguishes it from QAM, which is explained later in
this chapter. Also, from Figure 18b, it can be seen that the angular separation between any
two adjacent phasors in QPSK is 90°. Therefore, a QPSK signal can undergo almost a 45°
or 45° shift in phase during transmission and still retain the correct encoded information
when demodulated at the receiver. Figure 19 shows the output phase-versus-time relation-
ship for a QPSK modulator.

68
 Digital Modulation

FIGURE 18 QPSK modulator: (a) truth table; (b) phasor diagram; (c) constellation diagram

FIGURE 19 Output phase-versus-time relationship for a QPSK modulator

5-2-2 Bandwidth considerations of QPSK. With QPSK, because the input data are
divided into two channels, the bit rate in either the I or the Q channel is equal to one-half of
the input data rate (fb/2). (Essentially, the bit splitter stretches the I and Q bits to twice their
input bit length.) Consequently, the highest fundamental frequency present at the data input
to the I or the Q balanced modulator is equal to one-fourth of the input data rate (one-half of
fb/2  fb/4). As a result, the output of the I and Q balanced modulators requires a minimum
double-sided Nyquist bandwidth equal to one-half of the incoming bit rate (fN  twice fb/4
 fb/2). Thus, with QPSK, a bandwidth compression is realized (the minimum bandwidth is
less than the incoming bit rate). Also, because the QPSK output signal does not change phase
until two bits (a dibit) have been clocked into the bit splitter, the fastest output rate of change
(baud) is also equal to one-half of the input bit rate. As with BPSK, the minimum bandwidth
and the baud are equal. This relationship is shown in Figure 20.

69
 Digital Modulation

FIGURE 20 Bandwidth considerations of a QPSK modulator

In Figure 20, it can be seen that the worse-case input condition to the I or Q balanced
modulator is an alternative 1/0 pattern, which occurs when the binary input data have a
1100 repetitive pattern. One cycle of the fastest binary transition (a 1/0 sequence) in the I
or Q channel takes the same time as four input data bits. Consequently, the highest funda-
mental frequency at the input and fastest rate of change at the output of the balanced mod-
ulators is equal to one-fourth of the binary input bit rate.
The output of the balanced modulators can be expressed mathematically as
output  (sin ωat)(sin ωct) (22)

fb
at  2π t and ct  2πfc
4
冧

冧
where modulating carrier
signal

t≤ 1sin 2πfct2
fb
Thus, output  ¢sin 2π
4
1 fb 1 fb
cos 2π¢fc  ≤ t  cos 2π¢fc  ≤t
2 4 2 4

The output frequency spectrum extends from fc  fb /4 to fc  fb /4, and the minimum band-
width (fN) is

fb fb 2fb fb
¢fc  ≤  ¢fc  ≤  
4 4 4 2

Example 6
For a QPSK modulator with an input data rate (fb) equal to 10 Mbps and a carrier frequency of
70 MHz, determine the minimum double-sided Nyquist bandwidth (fN) and the baud. Also, compare
the results with those achieved with the BPSK modulator in Example 4. Use the QPSK block diagram
shown in Figure 17 as the modulator model.
Solution The bit rate in both the I and Q channels is equal to one-half of the transmission bit rate, or
fb 10 Mbps
fbQ  fbI    5 Mbps
2 2

70
 Digital Modulation

The highest fundamental frequency presented to either balanced modulator is

fbQfbI 5 Mbps
fa  or   2.5 MHz
2 2 2
The output wave from each balanced modulator is
(sin 2πfat)(sin 2πfct)

cos 2π1fc  fa 2t  cos 2π1fc  fa 2t

1 1
2 2

cos 2π3 170  2.5 2 MHz4t  cos 2π3 170  2.52 MHz4t
1 1
2 2
1 1
cos 2π167.5 MHz2 t  cos 2π172.5 MHz2t
2 2
The minimum Nyquist bandwidth is
B  (72.5  67.5) MHz  5 MHz
The symbol rate equals the bandwidth; thus,
symbol rate  5 megabaud
The output spectrum is as follows:

B  5 MHz

It can be seen that for the same input bit rate the minimum bandwidth required to pass the output of
the QPSK modulator is equal to one-half of that required for the BPSK modulator in Example 4. Also,
the baud rate for the QPSK modulator is one-half that of the BPSK modulator.

The minimum bandwidth for the QPSK system described in Example 6 can also be
determined by simply substituting into Equation 10:
10 Mbps
B
2
 5 MHz

5-2-3 QPSK receiver. The block diagram of a QPSK receiver is shown in Figure
21. The power splitter directs the input QPSK signal to the I and Q product detectors and
the carrier recovery circuit. The carrier recovery circuit reproduces the original transmit
carrier oscillator signal. The recovered carrier must be frequency and phase coherent with
the transmit reference carrier. The QPSK signal is demodulated in the I and Q product de-
tectors, which generate the original I and Q data bits. The outputs of the product detectors
are fed to the bit combining circuit, where they are converted from parallel I and Q data
channels to a single binary output data stream.
The incoming QPSK signal may be any one of the four possible output phases shown
in Figure 18. To illustrate the demodulation process, let the incoming QPSK signal be sin
ωct  cos ωct. Mathematically, the demodulation process is as follows.

71
72
FIGURE 21 QPSK receiver
 Digital Modulation

The receive QPSK signal (sin ωct  cos ωct) is one of the inputs to the I product
detector. The other input is the recovered carrier (sin ωct). The output of the I product de-
tector is

I  1sin ct  cos ct2 1sin ct2 (23)

冦
冦
QPSK input signal carrier

 (sin ct)(sin ct)  (cos ct)(sin ct)

 sin2 ct  (cos ct)(sin ct)

  11  cos 2ct2  sin 1c  c 2t  sin1c  c 2t

1 1 1
2 2 2
(filtered out) (equals 0)

1 1 1 1
I    cos 2ct  sin 2ct  sin 0
2 2 2 2

  V 1logic 02
1
2
Again, the receive QPSK signal (sin ωct  cos ωct) is one of the inputs to the Q
product detector. The other input is the recovered carrier shifted 90° in phase (cos ωct). The
output of the Q product detector is

Q  1sin ct  cos ct2 1cos ct2 (24)

冦
QPSK input signal
冦 carrier

 cos ct  1sin ct2 1cos ct2

2

11  cos 2ct2  sin1c  c 2t  sin1c  c 2t

1 1 1

2 2 2
(filtered out) (equals 0)

1 1 1 1
Q  cos 2ct  sin 2ct  sin 0
2 2 2 2
1
 V1logic 12
2
The demodulated I and Q bits (0 and 1, respectively) correspond to the constellation
diagram and truth table for the QPSK modulator shown in Figure 18.

5-2-4 Offset QPSK. Offset QPSK (OQPSK) is a modified form of QPSK where the
bit waveforms on the I and Q channels are offset or shifted in phase from each other by one-
half of a bit time.
Figure 22 shows a simplified block diagram, the bit sequence alignment, and the con-
stellation diagram for a OQPSK modulator. Because changes in the I channel occur at the
midpoints of the Q channel bits and vice versa, there is never more than a single bit change
in the dibit code and, therefore, there is never more than a 90° shift in the output phase. In
conventional QPSK, a change in the input dibit from 00 to 11 or 01 to 10 causes a corre-
sponding 180° shift in the output phase. Therefore, an advantage of OQPSK is the lim-
ited phase shift that must be imparted during modulation. A disadvantage of OQPSK is

73
 Digital Modulation

FIGURE 22 Offset keyed (OQPSK): (a) block diagram; (b) bit alignment; (c) constellation
diagram

that changes in the output phase occur at twice the data rate in either the I or Q channels.
Consequently, with OQPSK the baud and minimum bandwidth are twice that of conven-
tional QPSK for a given transmission bit rate. OQPSK is sometimes called OKQPSK
(offset-keyed QPSK).

5-3 8-PSK
With 8-PSK, three bits are encoded, forming tribits and producing eight different output
phases. With 8-PSK, n  3, M  8, and there are eight possible output phases. To encode eight
different phases, the incoming bits are encoded in groups of three, called tribits (23  8).

5-3-1 8-PSK transmitter. A block diagram of an 8-PSK modulator is shown in

Figure 23. The incoming serial bit stream enters the bit splitter, where it is converted to
a parallel, three-channel output (the I or in-phase channel, the Q or in-quadrature chan-
nel, and the C or control channel). Consequently, the bit rate in each of the three chan-
nels is fb /3. The bits in the I and C channels enter the I channel 2-to-4-level converter,
and the bits in the Q and C channels enter the Q channel 2-to-4-level converter. Essen-
tially, the 2-to-4-level converters are parallel-input digital-to-analog converters
(DACs). With two input bits, four output voltages are possible. The algorithm for the
DACs is quite simple. The I or Q bit determines the polarity of the output analog sig-
nal (logic 1  V and logic 0  V), whereas the C or C bit determines the magni-

74
 Digital Modulation

FIGURE 23 8-PSK modulator

FIGURE 24 I- and Q-channel 2-to-4-level converters: (a) I-channel truth table;

(b) Q-channel truth table; (c) PAM levels

tude (logic 1  1.307 V and logic 0  0.541 V). Consequently, with two magnitudes and
two polarities, four different output conditions are possible.
Figure 24 shows the truth table and corresponding output conditions for the 2-to-4-
level converters. Because the C and C bits can never be the same logic state, the outputs
from the I and Q 2-to-4-level converters can never have the same magnitude, although they
can have the same polarity. The output of a 2-to-4-level converter is an M-ary, pulse-
amplitude-modulated (PAM) signal where M  4.
Example 7
For a tribit input of Q  0, 1  0, and C  0 (000), determine the output phase for the 8-PSK mod-
ulator shown in Figure 23.
Solution The inputs to the I channel 2-to-4-level converter are I  0 and C  0. From Figure 24
the output is 0.541 V. The inputs to the Q channel 2-to-4-level converter are Q  0 and C  1.
Again from Figure 24, the output is 1.307 V.
Thus, the two inputs to the I channel product modulators are 0.541 and sin ωct. The output is
I  (0.541)(sin ωct)  0.541 sin ωct
The two inputs to the Q channel product modulator are 1.307 V and cos ωct. The output is
Q  (1.307)(cos ωct)  1.307 cos ωct

75
 Digital Modulation

The outputs of the I and Q channel product modulators are combined in the linear summer and pro-
duce a modulated output of
summer output  0.541 sin ωct  1.307 cos ωct
 1.41 sin(ωct  112.5°)
For the remaining tribit codes (001, 010, 011, 100, 101, 110, and 111), the procedure is the same. The
results are shown in Figure 25.

FIGURE 25 8-PSK modulator: (a) truth table; (b) phasor diagram;

(c) constellation diagram

76
 Digital Modulation

FIGURE 26 Output phase-versus-time relationship for an 8-PSK modulator

From Figure 25, it can be seen that the angular separation between any two adjacent
phasors is 45°, half what it is with QPSK. Therefore, an 8-PSK signal can undergo almost
a 22.5° phase shift during transmission and still retain its integrity. Also, each phasor is
of equal magnitude; the tribit condition (actual information) is again contained only in the
phase of the signal. The PAM levels of 1.307 and 0.541 are relative values. Any levels may
be used as long as their ratio is 0.541/1.307 and their arc tangent is equal to 22.5°. For ex-
ample, if their values were doubled to 2.614 and 1.082, the resulting phase angles would
not change, although the magnitude of the phasor would increase proportionally.
It should also be noted that the tribit code between any two adjacent phases changes
by only one bit. This type of code is called the Gray code or, sometimes, the maximum dis-
tance code. This code is used to reduce the number of transmission errors. If a signal were
to undergo a phase shift during transmission, it would most likely be shifted to an adjacent
phasor. Using the Gray code results in only a single bit being received in error.
Figure 26 shows the output phase-versus-time relationship of an 8-PSK modulator.
5-3-2 Bandwidth considerations of 8-PSK. With 8-PSK, because the data are di-
vided into three channels, the bit rate in the I, Q, or C channel is equal to one-third of the
binary input data rate (f b /3). (The bit splitter stretches the I, Q, and C bits to three times their
input bit length.) Because the I, Q, and C bits are outputted simultaneously and in parallel,
the 2-to-4-level converters also see a change in their inputs (and consequently their outputs)
at a rate equal to fb /3.
Figure 27 shows the bit timing relationship between the binary input data; the I, Q, and
C channel data; and the I and Q PAM signals. It can be seen that the highest fundamental fre-
quency in the I, Q, or C channel is equal to one-sixth the bit rate of the binary input (one cy-
cle in the I, Q, or C channel takes the same amount of time as six input bits). Also, the highest
fundamental frequency in either PAM signal is equal to one-sixth of the binary input bit rate.
With an 8-PSK modulator, there is one change in phase at the output for every three
data input bits. Consequently, the baud for 8 PSK equals fb /3, the same as the minimum band-
width. Again, the balanced modulators are product modulators; their outputs are the product of
the carrier and the PAM signal. Mathematically, the output of the balanced modulators is
θ  (X sin ωat)(sin ωct) (25)
fb
where at  2π t and c t  2πfct
6
冧
冧

modulating signal carrier

and X  1.307 or 0.541

fb
Thus, θ  ¢X sin 2π t≤1sin 2πfct2
6
X fb X fb
 cos 2π¢fc  ≤t  cos 2π¢fc  ≤t
2 6 2 6

77
 Digital Modulation

FIGURE 27 Bandwidth considerations of an 8-PSK modulator

The output frequency spectrum extends from fc  f b /6 to fc  f b /6, and the minimum band-
width (fN) is
fb fb 2fb fb
¢fc  ≤  ¢fc  ≤  
6 6 6 3
Example 8
For an 8-PSK modulator with an input data rate (fb) equal to 10 Mbps and a carrier frequency of
70 MHz, determine the minimum double-sided Nyquist bandwidth (fN) and the baud. Also, compare
the results with those achieved with the BPSK and QPSK modulators in Examples 4 and 6. Use the
8-PSK block diagram shown in Figure 23 as the modulator model.
Solution The bit rate in the I, Q, and C channels is equal to one-third of the input bit rate, or
10 Mbps
fbC  fbQ  fbI   3.33 Mbps
3

78
 Digital Modulation

Therefore, the fastest rate of change and highest fundamental frequency presented to either balanced
modulator is
fbC fbQ fbI 3.33 Mbps
fa  or or   1.667 Mbps
2 2 2 2
The output wave from the balance modulators is
(sin 2π fa t)(sin 2πfc t)

cos 2π1fc  fa 2t  cos 2π1fc  fa 2t

1 1
2 2

cos 2π3 170  1.6672 MHz4t  cos 2π3 170  1.667 2 MHz4t
1 1
2 2
1 1
cos2π168.333 MHz2t  cos 2π171.667 MHz2 t
2 2
The minimum Nyquist bandwidth is
B  (71.667  68.333) MHz  3.333 MHz
The minimum bandwidth for the 8-PSK can also be determined by simply substituting into
Equation 10:
10 Mbps
B
3
 3.33 MHz
Again, the baud equals the bandwidth; thus,
baud  3.333 megabaud
The output spectrum is as follows:

B  3.333 MHz
It can be seen that for the same input bit rate the minimum bandwidth required to pass the output of
an 8-PSK modulator is equal to one-third that of the BPSK modulator in Example 4 and 50% less than
that required for the QPSK modulator in Example 6. Also, in each case the baud has been reduced by
the same proportions.

5-3-3 8-PSK receiver. Figure 28 shows a block diagram of an 8-PSK receiver. The
power splitter directs the input 8-PSK signal to the I and Q product detectors and the car-
rier recovery circuit. The carrier recovery circuit reproduces the original reference oscilla-
tor signal. The incoming 8-PSK signal is mixed with the recovered carrier in the I product
detector and with a quadrature carrier in the Q product detector. The outputs of the product
detectors are 4-level PAM signals that are fed to the 4-to-2-level analog-to-digital con-
verters (ADCs). The outputs from the I channel 4-to-2-level converter are the I and C
bits, whereas the outputs from the Q channel 4-to-2-level converter are the Q and C
bits. The parallel-to-serial logic circuit converts the I/C and Q>C bit pairs to serial I, Q,
and C output data streams.

5-4 16-PSK
16-PSK is an M-ary encoding technique where M  16; there are 16 different output phases
possible. With 16-PSK, four bits (called quadbits) are combined, producing 16 different
output phases. With 16-PSK, n  4 and M  16; therefore, the minimum bandwidth and

79
80
FIGURE 28 8-PSK receiver
 Digital Modulation

FIGURE 29 16-PSK: (a) truth table; (b) constellation diagram

baud equal one-fourth the bit rate ( f b /4). Figure 29 shows the truth table and constellation
diagram for 16-PSK, respectively. Comparing Figures 18, 25, and 29 shows that as the level
of encoding increases (i.e., the values of n and M increase), more output phases are possi-
ble and the closer each point on the constellation diagram is to an adjacent point. With 16-
PSK, the angular separation between adjacent output phases is only 22.5°. Therefore, 16-
PSK can undergo only a 11.25° phase shift during transmission and still retain its integrity.
For an M-ary PSK system with 64 output phases (n  6), the angular separation between
adjacent phases is only 5.6°. This is an obvious limitation in the level of encoding (and bit
rates) possible with PSK, as a point is eventually reached where receivers cannot discern
the phase of the received signaling element. In addition, phase impairments inherent on
communications lines have a tendency to shift the phase of the PSK signal, destroying its
integrity and producing errors.

6 QUADRATURE-AMPLITUDE MODULATION

Quadrature-amplitude modulation (QAM) is a form of digital modulation similar to PSK

except the digital information is contained in both the amplitude and the phase of the trans-
mitted carrier. With QAM, amplitude and phase-shift keying are combined in such a way
that the positions of the signaling elements on the constellation diagrams are optimized to
achieve the greatest distance between elements, thus reducing the likelihood of one element
being misinterpreted as another element. Obviously, this reduces the likelihood of errors oc-
curring.

6-1 8-QAM
8-QAM is an M-ary encoding technique where M  8. Unlike 8-PSK, the output signal from
an 8-QAM modulator is not a constant-amplitude signal.

6-1-1 8-QAM transmitter. Figure 30a shows the block diagram of an 8-QAM
transmitter. As you can see, the only difference between the 8-QAM transmitter and the 8-
PSK transmitter shown in Figure 23 is the omission of the inverter between the C channel
and the Q product modulator. As with 8-PSK, the incoming data are divided into groups of
three bits (tribits): the I, Q, and C bit streams, each with a bit rate equal to one-third of

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 Digital Modulation

FIGURE 30 8-QAM transmitter: (a) block diagram; (b) truth table 4 level converters

the incoming data rate. Again, the I and Q bits determine the polarity of the PAM signal at
the output of the 2-to-4-level converters, and the C channel determines the magnitude. Be-
cause the C bit is fed uninverted to both the I and the Q channel 2-to-4-level converters,
the magnitudes of the I and Q PAM signals are always equal. Their polarities depend on
the logic condition of the I and Q bits and, therefore, may be different. Figure 30b shows
the truth table for the I and Q channel 2-to-4-level converters; they are identical.

Example 9
For a tribit input of Q  0, I  0, and C  0 (000), determine the output amplitude and phase for the
8-QAM transmitter shown in Figure 30a.
Solution The inputs to the I channel 2-to-4-level converter are I  0 and C  0. From Figure 30b,
the output is 0.541 V. The inputs to the Q channel 2-to-4-level converter are Q  0 and C  0. Again
from Figure 30b, the output is 0.541 V.
Thus, the two inputs to the I channel product modulator are 0.541 and sin ωct. The output is
I  (0.541)(sin ωct)  0.541 sin ωct
The two inputs to the Q channel product modulator are 0.541 and cos ωct. The output is
Q  (0.541)(cos ωct)  0.541 cos ωct
The outputs from the I and Q channel product modulators are combined in the linear summer and pro-
duce a modulated output of
summer output  0.541 sin ωct 0.541 cos ωct
 0.765 sin(ωct  135°)
For the remaining tribit codes (001, 010, 011, 100, 101, 110, and 111), the procedure is the same. The
results are shown in Figure 31.
Figure 32 shows the output phase-versus-time relationship for an 8-QAM modulator. Note that
there are two output amplitudes, and only four phases are possible.

6-1-2 Bandwidth considerations of 8-QAM. In 8-QAM, the bit rate in the I and
Q channels is one-third of the input binary rate, the same as in 8-PSK. As a result, the high-
est fundamental modulating frequency and fastest output rate of change in 8-QAM are the
same as with 8-PSK. Therefore, the minimum bandwidth required for 8-QAM is f b /3, the
same as in 8-PSK.

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 Digital Modulation

FIGURE 31 8-QAM modulator: (a) truth table; (b) phasor diagram; (c) constellation diagram

FIGURE 32 Output phase and amplitude-versus-time relationship for 8-QAM

6-1-3 8-QAM receiver. An 8-QAM receiver is almost identical to the 8-PSK re-
ceiver shown in Figure 28. The differences are the PAM levels at the output of the product
detectors and the binary signals at the output of the analog-to-digital converters. Because
there are two transmit amplitudes possible with 8-QAM that are different from those
achievable with 8-PSK, the four demodulated PAM levels in 8-QAM are different from
those in 8-PSK. Therefore, the conversion factor for the analog-to-digital converters must
also be different. Also, with 8-QAM the binary output signals from the I channel analog-
to-digital converter are the I and C bits, and the binary output signals from the Q channel
analog-to-digital converter are the Q and C bits.

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 Digital Modulation

6-2 16-QAM
As with the 16-PSK, 16-QAM is an M-ary system where M  16. The input data are acted
on in groups of four (24  16). As with 8-QAM, both the phase and the amplitude of the
transmit carrier are varied.

6-2-1 QAM transmitter. The block diagram for a 16-QAM transmitter is shown in
Figure 33. The input binary data are divided into four channels: I, I , Q, and Q . The bit rate
in each channel is equal to one-fourth of the input bit rate ( f b /4). Four bits are serially
clocked into the bit splitter; then they are outputted simultaneously and in parallel with the
I, I , Q, and Q channels. The I and Q bits determine the polarity at the output of the 2-to-
4-level converters (a logic 1  positive and a logic 0  negative). The I and Q bits deter-
mine the magnitude (a logic I  0.821 V and a logic 0  0.22 V). Consequently, the 2-to-
4-level converters generate a 4-level PAM signal. Two polarities and two magnitudes are
possible at the output of each 2-to-4-level converter. They are 0.22 V and 0.821 V.
The PAM signals modulate the in-phase and quadrature carriers in the product mod-
ulators. Four outputs are possible for each product modulator. For the I product modulator,
they are 0.821 sin ωct, 0.821 sin ωct, 0.22 sin ωct, and 0.22 sin ωct. For the Q prod-
uct modulator, they are 0.821 cos ωct, 0.22 cos ωct, 0.821 cos ωct, and 0.22 cos ωct.
The linear summer combines the outputs from the I and Q channel product modulators and
produces the 16 output conditions necessary for 16-QAM. Figure 34 shows the truth table
for the I and Q channel 2-to-4-level converters.

FIGURE 33 16-QAM transmitter block diagram

FIGURE 34 Truth tables for the I- and Q-channel 2-to-4-

level converters: (a) I channel; (b) Q channel

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 Digital Modulation

Example 10
For a quadbit input of I  0, I  0, Q  0, and Q  0 (0000), determine the output amplitude and
phase for the 16-QAM modulator shown in Figure 33.
Solution The inputs to the I channel 2-to-4-level converter are I  0 and I  0. From Figure 34,
the output is 0.22 V. The inputs to the Q channel 2-to-4-level converter are Q  0 and Q  0. Again
from Figure 34, the output is 0.22 V.
Thus, the two inputs to the I channel product modulator are 0.22 V and sin ωct. The output is
I  (0.22)(sin ωct)  0.22 sin ωct
The two inputs to the Q channel product modulator are 0.22 V and cos ωct. The output is
Q  (0.22)(cos ωct)  0.22 cos ωct
The outputs from the I and Q channel product modulators are combined in the linear summer and pro-
duce a modulated output of
summer output  0.22 sin ωct  0.22 cos ωct
 0.311 sin(ωct  135°)
For the remaining quadbit codes, the procedure is the same. The results are shown in Figure 35.

FIGURE 35 16-QAM modulator: (a) truth table; (b) phasor diagram; (c) constellation diagram

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 Digital Modulation

FIGURE 36 Bandwidth considerations of a 16-QAM modulator

6-2-2 Bandwidth considerations of 16-QAM. With a 16-QAM, because the input

data are divided into four channels, the bit rate in the I, I , Q, or Q channel is equal to one-
fourth of the binary input data rate ( f b /4). (The bit splitter stretches the I, I , Q, and Q bits
to four times their input bit length.) Also, because the I, I , Q, and Q bits are outputted si-
multaneously and in parallel, the 2-to-4-level converters see a change in their inputs and
outputs at a rate equal to one-fourth of the input data rate.
Figure 36 shows the bit timing relationship between the binary input data; the I, I ,
Q, and Q channel data; and the I PAM signal. It can be seen that the highest fundamental
frequency in the I, I , Q, or Q channel is equal to one-eighth of the bit rate of the binary in-
put data (one cycle in the I, I , Q, or Q channel takes the same amount of time as eight in-
put bits). Also, the highest fundamental frequency of either PAM signal is equal to one-
eighth of the binary input bit rate.
With a 16-QAM modulator, there is one change in the output signal (either its phase,
amplitude, or both) for every four input data bits. Consequently, the baud equals f b /4, the
same as the minimum bandwidth.

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 Digital Modulation

Again, the balanced modulators are product modulators and their outputs can be rep-
resented mathematically as
output  (X sin ωat)(sin ωct) (26)
fb
where at  2π t and c t  2πfct
8

冧
冧
modulating signal carrier

and X 0.22 or 0.821

fb
Thus, output  ¢X sin 2π t≤1sin 2πfct2
8

X fb X fb
 cos 2π ¢fc  ≤t  cos 2π ¢fc  ≤t
2 8 2 8
The output frequency spectrum extends from fc  f b /8 to fc  f b /8, and the minimum band-
width (fN) is

fb fb 2fb fb
¢fc  ≤  ¢fc  ≤  
8 8 8 4

Example 11
For a 16-QAM modulator with an input data rate (fb) equal to 10 Mbps and a carrier frequency of
70 MHz, determine the minimum double-sided Nyquist frequency (fN) and the baud. Also, compare
the results with those achieved with the BPSK, QPSK, and 8-PSK modulators in Examples 4, 6, and
8. Use the 16-QAM block diagram shown in Figure 33 as the modulator model.
Solution The bit rate in the I, I , Q, and Q channels is equal to one-fourth of the input bit rate, or
fb 10 Mbps
fbI  fbI¿  fbQ  fbQ¿    2.5 Mbps
4 4
Therefore, the fastest rate of change and highest fundamental frequency presented to either balanced
modulator is
fbI fbI¿ fbQ fbQ¿ 2.5 Mbps
fa  or or or   1.25 MHz
2 2 2 2 2
The output wave from the balanced modulator is
(sin 2π fat)(sin 2π fct)

cos 2π1fc  fa 2t  cos 2π1fc  fa 2t

1 1
2 2

cos 2π3 170  1.25 2 MHz4 t  cos 2π3 170  1.252 MHz4t
1 1
2 2
1 1
cos 2π168.75 MHz2 t  cos 2π171.25 MHz2t
2 2
The minimum Nyquist bandwidth is
B  (71.25  68.75) MHz  2.5 MHz
The minimum bandwidth for the 16-QAM can also be determined by simply substituting into
Equation 10:
10 Mbps
B
4
 2.5 MHz

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 Digital Modulation

The symbol rate equals the bandwidth; thus,

symbol rate  2.5 megabaud
The output spectrum is as follows:

B  2.5 MHz
For the same input bit rate, the minimum bandwidth required to pass the output of a 16-QAM mod-
ulator is equal to one-fourth that of the BPSK modulator, one-half that of QPSK, and 25% less than
with 8-PSK. For each modulation technique, the baud is also reduced by the same proportions.

Example 12
For the following modulation schemes, construct a table showing the number of bits encoded, num-
ber of output conditions, minimum bandwidth, and baud for an information data rate of 12 kbps:
QPSK, 8-PSK, 8-QAM, 16-PSK, and 16-QAM.
Solution
Modulation n M B (Hz) baud

QPSK 2 4 6000 6000

8-PSK 3 8 4000 4000
8-QAM 3 8 4000 4000
16-PSK 4 16 3000 3000
16-QAM 4 16 3000 3000

From Example 12, it can be seen that a 12-kbps data stream can be propagated through a narrower
bandwidth using either 16-PSK or 16-QAM than with the lower levels of encoding.

Table 1 summarizes the relationship between the number of bits encoded, the num-
ber of output conditions possible, the minimum bandwidth, and the baud for ASK, FSK,
PSK, and QAM. Note that with the three binary modulation schemes (ASK, FSK, and

Table 1 ASK, FSK, PSK, and QAM Summary

Modulation Encoding Scheme Outputs Possible Minimum Bandwidth Baud

ASK Single bit 2 fb fb

FSK Single bit 2 fb fb
BPSK Single bit 2 fb fb
QPSK Dibits 4 fb /2 fb /2
8-PSK Tribits 8 fb /3 fb /3
8-QAM Tribits 8 fb /3 fb /3
16-QAM Quadbits 16 fb /4 fb /4
16-PSK Quadbits 16 fb /4 fb /4
32-PSK Five bits 32 fb /5 fb /5
32-QAM Five bits 32 fb /5 fb /5
64-PSK Six bits 64 fb /6 fb /6
64-QAM Six bits 64 fb /6 fb /6
128-PSK Seven bits 128 fb /7 fb /7
128-QAM Seven bits 128 fb /7 fb /7

Note: fb indicates a magnitude equal to the input bit rate.

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 Digital Modulation

BPSK), n  1, M  2, only two output conditions are possible, and the baud is equal to the
bit rate. However, for values of n > 1, the number of output conditions increases, and the
minimum bandwidth and baud decrease. Therefore, digital modulation schemes where n > 1
achieve bandwidth compression (i.e., less bandwidth is required to propagate a given bit
rate). When data compression is performed, higher data transmission rates are possible for
a given bandwidth.

7 BANDWIDTH EFFICIENCY

Bandwidth efficiency (sometimes called information density or spectral efficiency) is often

used to compare the performance of one digital modulation technique to another. In
essence, bandwidth efficiency is the ratio of the transmission bit rate to the minimum band-
width required for a particular modulation scheme. Bandwidth efficiency is generally nor-
malized to a 1-Hz bandwidth and, thus, indicates the number of bits that can be propagated
through a transmission medium for each hertz of bandwidth. Mathematically, bandwidth
efficiency is

Bη  transmission bit rate (bps) (27)

minimum bandwidth (Hz)

 bits/s  bits/s  bits

hertz cycles/s cycle
where Bη  bandwidth efficiency
Bandwidth efficiency can also be given as a percentage by simply multiplying Bη by 100.

Example 13
For an 8-PSK system, operating with an information bit rate of 24 kbps, determine (a) baud, (b) min-
imum bandwidth, and (c) bandwidth efficiency.
Solution a. Baud is determined by substituting into Equation 10:
24,000
baud   8000
3

b. Bandwidth is determined by substituting into Equation 11:

24,000
B  8000
3
c. Bandwidth efficiency is calculated from Equation 27:

24,000 bps
Bh 
8000 Hz
 3 bits per second per cycle of bandwidth

Example 14
For 16-PSK and a transmission system with a 10 kHz bandwidth, determine the maximum bit rate.
Solution The bandwidth efficiency for 16-PSK is 4, which means that four bits can be propagated
through the system for each hertz of bandwidth. Therefore, the maximum bit rate is simply the prod-
uct of the bandwidth and the bandwidth efficiency, or
bit rate  4  10,000
 40,000 bps

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 Digital Modulation

Table 2 ASK, FSK, PSK, and QAM Summary

Modulation Encoding Scheme Outputs Possible Minimum Bandwidth Baud Bη

ASK Single bit 2 fb fb 1

FSK Single bit 2 fb fb 1
BPSK Single bit 2 fb fb 1
QPSK Dibits 4 fb /2 fb /2 2
8-PSK Tribits 8 fb /3 fb /3 3
8-QAM Tribits 8 fb /3 fb /3 3
16-PSK Quadbits 16 fb /4 fb /4 4
16-QAM Quadbits 16 fb /4 fb /4 4
32-PSK Five bits 32 fb /5 fb /5 5
64-QAM Six bits 64 fb /6 fb /6 6

Note: fb indicates a magnitude equal to the input bit rate.

7-1 Digital Modulation Summary

The properties of several digital modulation schemes are summarized in Table 2.

8 CARRIER RECOVERY

Carrier recovery is the process of extracting a phase-coherent reference carrier from a re-
ceiver signal. This is sometimes called phase referencing.
In the phase modulation techniques described thus far, the binary data were encoded
as a precise phase of the transmitted carrier. (This is referred to as absolute phase encoding.)
Depending on the encoding method, the angular separation between adjacent phasors varied
between 30° and 180°. To correctly demodulate the data, a phase-coherent carrier was re-
covered and compared with the received carrier in a product detector. To determine the ab-
solute phase of the received carrier, it is necessary to produce a carrier at the receiver that is
phase coherent with the transmit reference oscillator. This is the function of the carrier re-
covery circuit.
With PSK and QAM, the carrier is suppressed in the balanced modulators and, there-
fore, is not transmitted. Consequently, at the receiver the carrier cannot simply be tracked
with a standard phase-locked loop (PLL). With suppressed-carrier systems, such as PSK
and QAM, sophisticated methods of carrier recovery are required, such as a squaring loop,
a Costas loop, or a remodulator.

8-1 Squaring Loop

A common method of achieving carrier recovery for BPSK is the squaring loop. Figure 37
shows the block diagram of a squaring loop. The received BPSK waveform is filtered and
then squared. The filtering reduces the spectral width of the received noise. The squaring
circuit removes the modulation and generates the second harmonic of the carrier frequency.
This harmonic is phase tracked by the PLL. The VCO output frequency from the PLL then
is divided by 2 and used as the phase reference for the product detectors.

FIGURE 37 Squaring loop carrier recovery circuit for a BPSK receiver

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 Digital Modulation

With BPSK, only two output phases are possible: sin ωct and sin ωct. Mathe-
matically, the operation of the squaring circuit can be described as follows. For a receive
signal of sin ωct, the output of the squaring circuit is
output  (sin ωct)(sin ωct)  sin2 ωct
(filtered out)

11  cos 2ct2   cos 2ct

1 1 1

2 2 2
For a received signal of sin ωct, the output of the squaring circuit is
output  (sin ωct)(sin ωct)  sin2 ωct
(filtered out)

11  cos 2ct2   cos 2ct

1 1 1

2 2 2
It can be seen that in both cases, the output from the squaring circuit contained a con-
stant voltage (1/2 V) and a signal at twice the carrier frequency (cos 2ωct). The constant
voltage is removed by filtering, leaving only cos 2ωct.

8-2 Costas Loop

A second method of carrier recovery is the Costas, or quadrature, loop shown in Figure 38.
The Costas loop produces the same results as a squaring circuit followed by an ordinary PLL
in place of the BPF. This recovery scheme uses two parallel tracking loops (I and Q) simul-
taneously to derive the product of the I and Q components of the signal that drives the VCO.
The in-phase (I) loop uses the VCO as in a PLL, and the quadrature (Q) loop uses a 90°
shifted VCO signal. Once the frequency of the VCO is equal to the suppressed-carrier

FIGURE 38 Costas loop carrier recovery circuit

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 Digital Modulation

FIGURE 39 Remodulator loop carrier recovery circuit

frequency, the product of the I and Q signals will produce an error voltage proportional to
any phase error in the VCO. The error voltage controls the phase and, thus, the frequency of
the VCO.

8-3 Remodulator
A third method of achieving recovery of a phase and frequency coherent carrier is the re-
modulator, shown in Figure 39. The remodulator produces a loop error voltage that is pro-
portional to twice the phase error between the incoming signal and the VCO signal. The re-
modulator has a faster acquisition time than either the squaring or the Costas loops.
Carrier recovery circuits for higher-than-binary encoding techniques are similar to BPSK
except that circuits that raise the receive signal to the fourth, eighth, and higher powers are used.

9 CLOCK RECOVERY

As with any digital system, digital radio requires precise timing or clock synchronization
between the transmit and the receive circuitry. Because of this, it is necessary to regenerate
clocks at the receiver that are synchronous with those at the transmitter.
Figure 40a shows a simple circuit that is commonly used to recover clocking infor-
mation from the received data. The recovered data are delayed by one-half a bit time and
then compared with the original data in an XOR circuit. The frequency of the clock that is
recovered with this method is equal to the received data rate (fb). Figure 40b shows the re-
lationship between the data and the recovered clock timing. From Figure 40b, it can be seen
that as long as the receive data contain a substantial number of transitions (1/0 sequences),
the recovered clock is maintained. If the receive data were to undergo an extended period
of successive 1s or 0s, the recovered clock would be lost. To prevent this from occurring,
the data are scrambled at the transmit end and descrambled at the receive end. Scrambling
introduces transitions (pulses) into the binary signal using a prescribed algorithm, and the
descrambler uses the same algorithm to remove the transitions.

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 Digital Modulation

FIGURE 40 (a) Clock recovery circuit; (b) timing diagram

FIGURE 41 DBPSK modulator: (a) block diagram; (b) timing diagram

10 DIFFERENTIAL PHASE-SHIFT KEYING

Differential phase-shift keying (DPSK) is an alternative form of digital modulation where

the binary input information is contained in the difference between two successive sig-
naling elements rather than the absolute phase. With DPSK, it is not necessary to recover
a phase-coherent carrier. Instead, a received signaling element is delayed by one signal-
ing element time slot and then compared with the next received signaling element. The
difference in the phase of the two signaling elements determines the logic condition of
the data.

10-1 Differential BPSK

10-1-1 DBPSK transmitter. Figure 41a shows a simplified block diagram of a

differential binary phase-shift keying (DBPSK) transmitter. An incoming information bit is

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 Digital Modulation

FIGURE 42 DBPSK demodulator: (a) block diagram; (b) timing sequence

XNORed with the preceding bit prior to entering the BPSK modulator (balanced modulator).
For the first data bit, there is no preceding bit with which to compare it. Therefore, an initial ref-
erence bit is assumed. Figure 41b shows the relationship between the input data, the XNOR out-
put data, and the phase at the output of the balanced modulator. If the initial reference bit is as-
sumed a logic 1, the output from the XNOR circuit is simply the complement of that shown.
In Figure 41b, the first data bit is XNORed with the reference bit. If they are the same,
the XNOR output is a logic 1; if they are different, the XNOR output is a logic 0. The bal-
anced modulator operates the same as a conventional BPSK modulator; a logic 1 produces
sin ωct at the output, and a logic 0 produces sin ωct at the output.

10-1-2 DBPSK receiver. Figure 42 shows the block diagram and timing sequence
for a DBPSK receiver. The received signal is delayed by one bit time, then compared with
the next signaling element in the balanced modulator. If they are the same, a logic 1 ( volt-
age) is generated. If they are different, a logic 0 ( voltage) is generated. If the reference
phase is incorrectly assumed, only the first demodulated bit is in error. Differential encod-
ing can be implemented with higher-than-binary digital modulation schemes, although the
differential algorithms are much more complicated than for DBPSK.
The primary advantage of DBPSK is the simplicity with which it can be imple-
mented. With DBPSK, no carrier recovery circuit is needed. A disadvantage of DBPSK is
that it requires between 1 dB and 3 dB more signal-to-noise ratio to achieve the same bit er-
ror rate as that of absolute PSK.

11 TRELLIS CODE MODULATION

Achieving data transmission rates in excess of 9600 bps over standard telephone lines with
approximately a 3-kHz bandwidth obviously requires an encoding scheme well beyond the
quadbits used with 16-PSK or 16-QAM (i.e., M must be significantly greater than 16). As
might be expected, higher encoding schemes require higher signal-to-noise ratios. Using
the Shannon limit for information capacity (Equation 4), a data transmission rate of 28.8
kbps through a 3200-Hz bandwidth requires a signal-to-noise ratio of
I(bps)  (3.32  B) log(1  S/N)

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 Digital Modulation

therefore, 28.8 kbps  (3.32)(3200) log(1  S/N)

28,800  10,624 log(1  S/N)
28,800
 log11  S>N2
10,624

2.71  log(1  S/N)

thus, 102.71  1  S/N

513  1  S/N
512  S/N

in dB, S/N(dB)  10 log 512

 27 dB
Transmission rates of 56 kbps require a signal-to-noise ratio of 53 dB, which is virtually
impossible to achieve over a standard telephone circuit.
Data transmission rates in excess of 56 kbps can be achieved, however, over standard
telephone circuits using an encoding technique called trellis code modulation (TCM).
Dr. Ungerboeck at IBM Zuerich Research Laboratory developed TCM, which involves us-
ing convolutional (tree) codes, which combines encoding and modulation to reduce the
probability of error, thus improving the bit error performance. The fundamental idea behind
TCM is introducing controlled redundancy in the bit stream with a convolutional code,
which reduces the likelihood of transmission errors. What sets TCM apart from standard
encoding schemes is the introduction of redundancy by doubling the number of signal
points in a given PSK or QAM constellation.
Trellis code modulation is sometimes thought of as a magical method of increasing trans-
mission bit rates over communications systems using QAM or PSK with fixed bandwidths. Few
people fully understand this concept, as modem manufacturers do not seem willing to share in-
formation on TCM. Therefore, the following explanation is intended not to fully describe the
process of TCM but rather to introduce the topic and give the reader a basic understanding of
how TCM works and the advantage it has over conventional digital modulation techniques.
M-ary QAM and PSK utilize a signal set of 2N  M, where N equals the number of
bits encoded into M different conditions. Therefore, N  2 produces a standard PSK con-
stellation with four signal points (i.e., QPSK) as shown in Figure 43a. Using TCM, the
number of signal points increases to two times M possible symbols for the same factor-of-
M reduction in bandwidth while transmitting each signal during the same time interval.
TCM-encoded QPSK is shown in Figure 43b.
Trellis coding also defines the manner in which signal-state transitions are allowed to
occur, and transitions that do not follow this pattern are interpreted in the receiver as trans-
mission errors. Therefore, TCM can improve error performance by restricting the manner
in which signals are allowed to transition. For values of N greater than 2, QAM is the mod-
ulation scheme of choice for TCM; however, for simplification purposes, the following ex-
planation uses PSK as it is easier to illustrate.
Figure 44 shows a TCM scheme using two-state 8-PSK, which is essentially two
QPSK constellations offset by 45°. One four-state constellation is labeled 0-4-2-6, and the
other is labeled 1-5-3-7. For this explanation, the signal point labels 0 through 7 are meant
not to represent the actual data conditions but rather to simply indicate a convenient method
of labeling the various signal points. Each digit represents one of four signal points per-
mitted within each of the two QPSK constellations. When in the 0-4-2-6 constellation and
a 0 or 4 is transmitted, the system remains in the same constellation. However, when either
a 2 or 6 is transmitted, the system switches to the 1-5-3-7 constellation. Once in the 1-5-3-7

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 Digital Modulation

FIGURE 43 QPSK constellations: (a) standard encoding format; (b) trellis encoding format

0 0
0-4-2-6
4 4

1 2 1 2
5 6 5 6

3 3
1-5-3-7
7 7

FIGURE 44 8-PSK TCM constellations

constellation and a 3 or 7 is transmitted, the system remains in the same constellation, and
if a 1 or 5 is transmitted, the system switches to the 0-4-2-6 constellation. Remember that
each symbol represents two bits, so the system undergoes a 45° phase shift whenever it
switches between the two constellations. A complete error analysis of standard QPSK
compared with TCM QPSK would reveal a coding gain for TCM of 2-to-1 1 or 3 dB.
Table 3 lists the coding gains achieved for TCM coding schemes with several different
trellis states.
The maximum data rate achievable using a given bandwidth can be determined by re-
arranging Equation 10:
N  B  fb

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 Digital Modulation

Table 3 Trellis Coding Gain

Number of Trellis States Coding Gain (dB)

2 3.0
4 5.5
8 6.0
16 6.5
32 7.1
64 7.3
128 7.3
256 7.4

where N  number of bits encoded (bits)

B  bandwidth (hertz)
fb  transmission bit rate (bits per second)
Remember that with M-ary QAM or PSK systems, the baud equals the minimum re-
quired bandwidth. Therefore, a 3200-Hz bandwidth using a nine-bit trellis code pro-
duces a 3200 baud signal with each baud carrying nine bits. Therefore, the transmission
rate fb  9  3200  28.8 kbps.
TCM is thought of as a coding scheme that improves on standard QAM by increasing
the distance between symbols on the constellation (known as the Euclidean distance). The
first TCM system used a five-bit code, which included four QAM bits (a quadbit) and a fifth
bit used to help decode the quadbit. Transmitting five bits within a single signaling element
requires producing 32 discernible signals. Figure 45 shows a 128-point QAM constallation.

90°
0110000 0111000
8
1100000 1111001 1101000 1110001

0010011 0101001 0010111 0100001 0010101

6
1011101 1000011 1011111 1000111 1011011 1000101

0110101 0001101 0110100 0001111 0111100 0001011 0111101

4
1100101 1111010 1100100 1111010 11001100 1110010 1101101 1110011

0010001 0101011 0010010 0101010 0010110 0100010 0010100 0100011 0010000

2
1011000 1000001 1011100 1000010 1011110 1000110 1011010 1000100 1011001 100000
0001000 0110111 0001100 0110110 0001110 0111110 0001010 0111111 0001001
–8 –6 –4 –2 2 4 6 8
180° 1100111 1111111 1100110 1111110 1101110 1110110 1101111 1110111 0°

0101000 0101000 0101000 0101000 0101001 0101000 0101000 0101000 0101000

–2
1010000 1001001 1010100 1001010 1010100 1001110 1010010 1001100 1010001 1001000

0000000 0110011 0000100 0110010 0000110 0111010 0000010 0111011 0000001

–4
1100011 1111101 1100010 1111100 1101010 1110100 1101011 1110101

0101101 0011011 0101100 0011111 0100100 0011101 0100101

–6
1010101 1001011 1010111 1001111 1010011 1001101

0000101 0110001 0000111 0111001 0000011

–8
1100001 1111000 1101001 1110000
0101000 270° 0100000

FIGURE 45 128-Point QAM TCM constellation

97
 Digital Modulation

236 224 216 212 218 228

234 205 185 173 164 162 170 181 197 220

226 193 165 146 133 123 121 125 137 154 179 207

229 189 156 131 110 96 87 33 92 100 117 140 172 208

201 160 126 98 79 64 58 54 62 71 90 112 141 180 221

222 177 135 102 77 55 41 35 31 37 48 65 91 118 155 198

203 158 119 84 60 39 24 17 15 20 30 49 72 101 138 182 230

194 148 108 75 50 28 13 6 4 8 21 38 63 93 127 171 219

238 186 142 103 69 43 22 9 1 0 5 16 32 56 85 122 163 213

190 144 106 73 45 25 11 3 2 7 18 36 59 88 124 166 217

199 152 113 80 52 33 19 12 10 14 26 42 66 97 134 174 225

210 167 128 94 67 47 34 27 23 29 40 57 81 111 147 187 237

232 183 149 115 89 68 53 46 44 51 61 78 99 132 168 209

214 175 139 116 95 82 74 70 76 86 104 129 157 195 235

205 176 150 130 114 107 105 109 120 136 161 191 227

215 184 169 153 145 143 151 159 178 202 231

233 211 200 192 188 196 204 223

239

FIGURE 46 One-fourth of a 960-Point QAM TCM constellation

A 3200-baud signal using nine-bit TCM encoding produces 512 different codes.
The nine data bits plus a redundant bit for TCM requires a 960-point constellation. Figure
46 shows one-fourth of the 960-point superconstellation showing 240 signal points. The
full superconstellation can be obtained by rotating the 240 points shown by 90°, 180°,
and 270°.

12 PROBABILITY OF ERROR AND BIT ERROR RATE

Probability of error P(e) and bit error rate (BER) are often used interchangeably, al-
though in practice they do have slightly different meanings. P(e) is a theoretical (mathe-
matical) expectation of the bit error rate for a given system. BER is an empirical (histor-
ical) record of a system’s actual bit error performance. For example, if a system has a
P(e) of 105, this means that mathematically you can expect one bit error in every
100,000 bits transmitted (1/105  1/100,000). If a system has a BER of 105, this
means that in past performance there was one bit error for every 100,000 bits transmit-
ted. A bit error rate is measured and then compared with the expected probability of er-
ror to evaluate a system’s performance.

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 Digital Modulation

Probability of error is a function of the carrier-to-noise power ratio (or, more specif-
ically, the average energy per bit-to-noise power density ratio) and the number of possible
encoding conditions used (M-ary). Carrier-to-noise power ratio is the ratio of the average
carrier power (the combined power of the carrier and its associated sidebands) to the
thermal noise power. Carrier power can be stated in watts or dBm, where

C1watts2
C1dBm2  10 log (28)
0.001
Thermal noise power is expressed mathematically as
N  KTB (watts) (29)
where N  thermal noise power (watts)
K  Boltzmann’s proportionality constant (1.38  1023 joules per kelvin)
T  temperature (kelvin: 0 K  273° C, room temperature  290 K)
B  bandwidth (hertz)

KTB
Stated in dBm, N1dBm2  10 log (30)
0.001
Mathematically, the carrier-to-noise power ratio is

1unitless ratio2
C C
 (31)
N KTB
where C  carrier power (watts)
N  noise power (watts)

1dB2  10 log
C C
Stated in dB,
N N
 C(dBm) N(dBm) (32)
Energy per bit is simply the energy of a single bit of information. Mathematically, en-
ergy per bit is
Eb  CTb (J/bit) (33)
where Eb  energy of a single bit (joules per bit)
Tb  time of a single bit (seconds)
C  carrier power (watts)
Stated in dBJ, Eb(dBJ)  10 log Eb (34)
and because Tb  1/fb, where fb is the bit rate in bits per second, Eb can be rewritten as

1J>bit2
C
Eb  (35)
fb
C
Stated in dBJ, Eb 1dBJ2  10 log (36)
fb

 10 log C  10 log fb (37)

Noise power density is the thermal noise power normalized to a 1-Hz bandwidth (i.e.,
the noise power present in a 1-Hz bandwidth). Mathematically, noise power density is

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 Digital Modulation

1W>Hz2
N
N0  (38)
B
where N0  noise power density (watts per hertz)
N  thermal noise power (watts)
B  bandwidth (hertz)
N
Stated in dBm, N01dBm2  10 log  10 log B (39)
0.001
 N(dBm)  10 log B (40)
Combining Equations 29 and 38 yields

 KT 1W>Hz2
KTB
N0  (41)
B
K
Stated in dBm, N01dBm2  10 log  10 log T (42)
0.001
Energy per bit-to-noise power density ratio is used to compare two or more digital
modulation systems that use different transmission rates (bit rates), modulation schemes
(FSK, PSK, QAM), or encoding techniques (M-ary). The energy per bit-to-noise power
density ratio is simply the ratio of the energy of a single bit to the noise power present in
1 Hz of bandwidth. Thus, Eb/N0 normalizes all multiphase modulation schemes to a com-
mon noise bandwidth, allowing for a simpler and more accurate comparison of their error
performance. Mathematically, Eb/N0 is
Eb C>fb CB
  (43)
N0 N>B Nfb
where EbN0 is the energy per bit-to-noise power density ratio. Rearranging Equation 43
yields the following expression:
Eb C B
  (44)
N0 N fb
where Eb/N0  energy per bit-to-noise power density ratio
C/N  carrier-to-noise power ratio
B/fb  noise bandwidth-to-bit rate ratio

1dB2  10 log  10 log

Eb C B
Stated in dB, (45)
N0 N fb
or  10 log Eb  10 log N0 (46)
From Equation 44, it can be seen that the Eb/N0 ratio is simply the product of the carrier-to-
noise power ratio and the noise bandwidth-to-bit rate ratio. Also, from Equation 44, it can
be seen that when the bandwidth equals the bit rate, Eb/N0  C/N.
In general, the minimum carrier-to-noise power ratio required for QAM systems is
less than that required for comparable PSK systems, Also, the higher the level of encoding
used (the higher the value of M), the higher the minimum carrier-to-noise power ratio.
Example 15
For a QPSK system and the given parameters, determine
a. Carrier power in dBm.
b. Noise power in dBm.

100
 Digital Modulation

c. Noise power density in dBm.

d. Energy per bit in dBJ.
e. Carrier-to-noise power ratio in dB.
f. Eb/N0 ratio.
C  1012 W fb  60 kbps
N  1.2  1014 W B  120 kHz
Solution a. The carrier power in dBm is determined by substituting into Equation 28:

1012
C  10 log  90 dBm
0.001

b. The noise power in dBm is determined by substituting into Equation 30:

1.2  1014
N  10 log  109.2 dBm
0.001
c. The noise power density is determined by substituting into Equation 40:
N0  109.2 dBm  10 log 120 kHz  160 dBm
d. The energy per bit is determined by substituting into Equation 36:
1012
Eb  10 log  167.8 dBJ
60 kbps
e. The carrier-to-noise power ratio is determined by substituting into Equation 34:
C 1012
 10 log  19.2 dB
N 1.2  1014
f. The energy per bit-to-noise density ratio is determined by substituting into Equation 45:
Eb 120 kHz
 19.2  10 log  22.2 dB
N0 60 kbps

13 ERROR PERFORMANCE

13-1 PSK Error Performance

The bit error performance for the various multiphase digital modulation systems is directly re-
lated to the distance between points on a signal state-space diagram. For example, on the signal
state-space diagram for BPSK shown in Figure 47a, it can be seen that the two signal points
(logic 1 and logic 0) have maximum separation (d) for a given power level (D). In essence, one
BPSK signal state is the exact negative of the other. As the figure shows, a noise vector (VN),
when combined with the signal vector (VS), effectively shifts the phase of the signaling element
(VSE) alpha degrees. If the phase shift exceeds 90°, the signal element is shifted beyond the
threshold points into the error region. For BPSK, it would require a noise vector of sufficient am-
plitude and phase to produce more than a 90° phase shift in the signaling element to produce
an error. For PSK systems, the general formula for the threshold points is
π
TP  ± (47)
M
where M is the number of signal states.
The phase relationship between signaling elements for BPSK (i.e., 180° out of phase)
is the optimum signaling format, referred to as antipodal signaling, and occurs only when
two binary signal levels are allowed and when one signal is the exact negative of the other.
Because no other bit-by-bit signaling scheme is any better, antipodal performance is often
used as a reference for comparison.
The error performance of the other multiphase PSK systems can be compared with
that of BPSK simply by determining the relative decrease in error distance between points

101
 Digital Modulation

FIGURE 47 PSK error region: (a) BPSK; (b) QPSK

on a signal state-space diagram. For PSK, the general formula for the maximum distance
between signaling points is given by
360° d>2
sin θ  sin  (48)
2M D
where d  error distance
M  number of phases
D  peak signal amplitude
Rearranging Equation 48 and solving for d yields

180°
d  ¢2 sin ≤D (49)
M
Figure 47b shows the signal state-space diagram for QPSK. From Figure 47 and Equa-
tion 48, it can be seen that QPSK can tolerate only a 45° phase shift. From Equation 47,

102
 Digital Modulation

the maximum phase shift for 8-PSK and 16-PSK is 22.5° and 11.25°, respectively. Con-
sequently, the higher levels of modulation (i.e., the greater the value of M) require a greater
energy per bit-to-noise power density ratio to reduce the effect of noise interference. Hence,
the higher the level of modulation, the smaller the angular separation between signal points
and the smaller the error distance.
The general expression for the bit error probability of an M-phase PSK system is

erf 1z2
1
P1e2  (50)
log2M
where erf  error function
z  sin1π>M2 1 2log2M2 1 2Eb>N0 2
By substituting into Equation 50, it can be shown that QPSK provides the same error
performance as BPSK. This is because the 3-dB reduction in error distance for QPSK is off-
set by the 3-dB decrease in its bandwidth (in addition to the error distance, the relative
widths of the noise bandwidths must also be considered). Thus, both systems provide opti-
mum performance. Figure 48 shows the error performance for 2-, 4-, 8-, 16-, and 32-PSK sys-
tems as a function of Eb/N0.

FIGURE 48 Error rates of PSK modulation systems

103
 Digital Modulation

Example 16
Determine the minimum bandwidth required to achieve a P(e) of 107 for an 8-PSK system operat-
ing at 10 Mbps with a carrier-to-noise power ratio of 11.7 dB.
Solution From Figure 48, the minimum Eb/N0 ratio to achieve a P(e) of 107 for an 8-PSK system
is 14.7 dB. The minimum bandwidth is found by rearranging Equation 44:
B Eb C
 
fb N0 N
 14.7 dB  11.7 dB  3 dB
B
 antilog 3  2
fb
B  2  10 Mbps  20 MHz

13-2 QAM Error Performance

For a large number of signal points (i.e., M-ary systems greater than 4), QAM outperforms
PSK. This is because the distance between signaling points in a PSK system is smaller
than the distance between points in a comparable QAM system. The general expression
for the distance between adjacent signaling points for a QAM system with L levels on each
axis is
22
d D (51)
L1
where d  error distance
L  number of levels on each axis
D  peak signal amplitude
In comparing Equation 49 to Equation 51, it can be seen that QAM systems have an
advantage over PSK systems with the same peak signal power level.
The general expression for the bit error probability of an L-level QAM system is

L1
≤ erfc1z 2
1
P1e2  ¢ (52)
log2L L
where erfc(z) is the complementary error function.

2log2L Eb
z
L  1 B N0
Figure 49 shows the error performance for 4-, 16-, 32-, and 64-QAM systems as a function
of Eb/N0.
Table 4 lists the minimum carrier-to-noise power ratios and energy per bit-to-noise
power density ratios required for a probability of error 106 for several PSK and QAM
modulation schemes.

Example 17
Which system requires the highest Eb/N0 ratio for a probability of error of 106, a four-level QAM
system or an 8-PSK system?
Solution From Figure 49, the minimum Eb/N0 ratio required for a four-level QAM system is 10.6
dB. From Figure 48, the minimum Eb/N0 ratio required for an 8-PSK system is 14 dB. Therefore, to
achieve a P(e) of 106, a four-level QAM system would require 3.4 dB less Eb/N0 ratio.

104
 Digital Modulation

FIGURE 49 Error rates of QAM modulation systems

Table 4 Performance Comparison of Various Digital Modulation

Schemes (BER = 106)

Modulation Technique C/N Ratio (dB) Eb /N0 Ratio (dB)

BPSK 10.6 10.6

QPSK 13.6 10.6
4-QAM 13.6 10.6
8-QAM 17.6 10.6
8-PSK 18.5 14
16-PSK 24.3 18.3
16-QAM 20.5 14.5
32-QAM 24.4 17.4
64-QAM 26.6 18.8

105
 Digital Modulation

FIGURE 50 Error rates for FSK modulation systems

13-3 FSK Error Performance

The error probability for FSK systems is evaluated in a somewhat different manner than
PSK and QAM. There are essentially only two types of FSK systems: noncoherent (asyn-
chronous) and coherent (synchronous). With noncoherent FSK, the transmitter and receiver
are not frequency or phase synchronized. With coherent FSK, local receiver reference sig-
nals are in frequency and phase lock with the transmitted signals. The probability of error
for noncoherent FSK is

1 Eb
P1e2  exp ¢ ≤ (53)
2 2N0
The probability of error for coherent FSK is

Eb
P1e2  erfc (54)
B N0
Figure 50 shows probability of error curves for both coherent and noncoherent FSK for sev-
eral values of Eb/N0. From Equations 53 and 54, it can be determined that the probability
of error for noncoherent FSK is greater than that of coherent FSK for equal energy per bit-
to-noise power density ratios.

QUESTIONS
1. Explain digital transmission and digital radio.
2. Define information capacity.
3. What are the three most predominant modulation schemes used in digital radio systems?

106
 Digital Modulation

4. Explain the relationship between bits per second and baud for an FSK system.
5. Define the following terms for FSK modulation: frequency deviation, modulation index, and dev-
iation ratio.
6. Explain the relationship between (a) the minimum bandwidth required for an FSK system and
the bit rate and (b) the mark and space frequencies.
7. What is the difference between standard FSK and MSK? What is the advantage of MSK?
8. Define PSK.
9. Explain the relationship between bits per second and baud for a BPSK system.
10. What is a constellation diagram, and how is it used with PSK?
11. Explain the relationship between the minimum bandwidth required for a BPSK system and the
bit rate.
12. Explain M-ary.
13. Explain the relationship between bits per second and baud for a QPSK system.
14. Explain the significance of the I and Q channels in a QPSK modulator.
15. Define dibit.
16. Explain the relationship between the minimum bandwidth required for a QPSK system and the
bit rate.
17. What is a coherent demodulator?
18. What advantage does OQPSK have over conventional QPSK? What is a disadvantage of OQPSK?
19. Explain the relationship between bits per second and baud for an 8-PSK system.
20. Define tribit.
21. Explain the relationship between the minimum bandwidth required for an 8-PSK system and the
bit rate.
22. Explain the relationship between bits per second and baud for a 16-PSK system.
23. Define quadbit.
24. Define QAM.
25. Explain the relationship between the minimum bandwidth required for a 16-QAM system and the
bit rate.
26. What is the difference between PSK and QAM?
27. Define bandwidth efficiency.
28. Define carrier recovery.
29. Explain the differences between absolute PSK and differential PSK.
30. What is the purpose of a clock recovery circuit? When is it used?
31. What is the difference between probability of error and bit error rate?

PROBLEMS
1. Determine the bandwidth and baud for an FSK signal with a mark frequency of 32 kHz, a space
frequency of 24 kHz, and a bit rate of 4 kbps.
2. Determine the maximum bit rate for an FSK signal with a mark frequency of 48 kHz, a space fre-
quency of 52 kHz, and an available bandwidth of 10 kHz.
3. Determine the bandwidth and baud for an FSK signal with a mark frequency of 99 kHz, a space
frequency of 101 kHz, and a bit rate of 10 kbps.
4. Determine the maximum bit rate for an FSK signal with a mark frequency of 102 kHz, a space
frequency of 104 kHz, and an available bandwidth of 8 kHz.
5. Determine the minimum bandwidth and baud for a BPSK modulator with a carrier frequency of
40 MHz and an input bit rate of 500 kbps. Sketch the output spectrum.
6. For the QPSK modulator shown in Figure 17, change the 90° phase-shift network to 90° and
sketch the new constellation diagram.
7. For the QPSK demodulator shown in Figure 21, determine the I and Q bits for an input signal of
sin ωct  cos ωct.

107
 Digital Modulation

8. For an 8-PSK modulator with an input data rate (fb) equal to 20 Mbps and a carrier frequency of
100 MHz, determine the minimum double-sided Nyquist bandwidth (fN) and the baud. Sketch the
output spectrum.
9. For the 8-PSK modulator shown in Figure 23, change the reference oscillator to cos ωct and
sketch the new constellation diagram.
10. For a 16-QAM modulator with an input bit rate (fb) equal to 20 Mbps and a carrier frequency of
100 MHz, determine the minimum double-sided Nyquist bandwidth (fN) and the baud. Sketch the
output spectrum.
11. For the 16-QAM modulator shown in Figure 33, change the reference oscillator to cos ωct and
determine the output expressions for the following I, I , Q, and Q input conditions: 0000, 1111,
1010, and 0101.
12. Determine the bandwidth efficiency for the following modulators:
a. QPSK, fb  10 Mbps
b. 8-PSK, fb  21 Mbps
c. 16-QAM, fb  20 Mbps
13. For the DBPSK modulator shown in Figure 40a, determine the output phase sequence for the fol-
lowing input bit sequence: 00110011010101 (assume that the reference bit  1).
14. For a QPSK system and the given parameters, determine
a. Carrier power in dBm.
b. Noise power in dBm.
c. Noise power density in dBm.
d. Energy per bit in dBJ.
e. Carrier-to-noise power ratio.
f. Eb/N0 ratio.
C  1013 W fb  30 kbps
N  0.06  1015 W B  60 kHz
15. Determine the minimum bandwidth required to achieve a P(e) of 106 for an 8-PSK system op-
erating at 20 Mbps with a carrier-to-noise power ratio of 11 dB.
16. Determine the minimum bandwidth and baud for a BPSK modulator with a carrier frequency of
80 MHz and an input bit rate fb  1 Mbps. Sketch the output spectrum.
17. For the QPSK modulator shown in Figure 17, change the reference oscillator to cos ωct and
sketch the new constellation diagram.
18. For the QPSK demodulator shown in Figure 21, determine the I and Q bits for an input signal
sin ωct  cos ωct.
19. For an 8-PSK modulator with an input bit rate fb  10 Mbps and a carrier frequency fc  80 MHz,
determine the minimum Nyquist bandwidth and the baud. Sketch the output spectrum.
20. For the 8-PSK modulator shown in Figure 23, change the 90° phase-shift network to a 90°
phase shifter and sketch the new constellation diagram.
21. For a 16-QAM modulator with an input bit rate fb  10 Mbps and a carrier frequency fc  60 MHz,
determine the minimum double-sided Nyquist frequency and the baud. Sketch the output spectrum.
22. For the 16-QAM modulator shown in Figure 33, change the 90° phase shift network to a  90°
phase shifter and determine the output expressions for the following I, I , Q, and Q input condi-
tions: 0000, 1111, 1010, and 0101.
23. Determine the bandwidth efficiency for the following modulators:
a. QPSK, fb  20 Mbps
b. 8-PSK, fb  28 Mbps
c. 16-PSK, fb  40 Mbps
24. For the DBPSK modulator shown in Figure 40a, determine the output phase sequence for the fol-
lowing input bit sequence: 11001100101010 (assume that the reference bit is a logic 1).

108
 Digital Modulation

ANSWERS TO SELECTED PROBLEMS

1. 16 kHz, 4000 baud
3. 22 kHz, 10 kbaud
5. 5 MHz, 5 Mbaud
7. I  1, Q  0
9. Q I C Phase
0 0 0 22.5°
0 0 1 67.5°
0 1 0 22.5°
0 1 1 67.5°
1 0 0 157.5°
1 0 1 112.5°
1 1 0 157.5°
1 1 1 112.5°

11. Q Q’ I I’ Phase

0 0 0 0 45°
1 1 1 1 135°
1 0 1 0 135°
0 1 0 1 45°

13. Input 00110011010101

XNOR 101110111001100
15. 40 MHz
17. Q I Phase

0 0 135°
0 1 45°
1 0 135°
1 1 45°

19. 3.33 MHz, 3.33 Mbaud

21. 2.5 MHz, 2.5 Mbaud
23. a. 2 bps/Hz
b. 3 bps/Hz
c. 4 bps/Hz

109
110
 Fundamental Concepts of Data Communications

Error performance is the rate in which errors occur, which can be described as either
an expected or an empirical value. The theoretical (mathematical) expectation of the rate at
which errors will occur is called probability of error (P[e]), whereas the actual historical
record of a system’s error performance is called bit error rate (BER). For example, if a sys-
tem has a P(e) of 105, this means that mathematically the system can expect to experience
one bit error for every 100,000 bits transported through the system (105  1/105 
1/100,000). If a system has a BER of 105, this means that in the past there was one bit er-
ror for every 100,000 bits transported. Typically, a BER is measured and then compared
with the probability of error to evaluate system performance. Error control can be divided
into two general categories: error detection and error correction.

5 ERROR DETECTION

Error detection is the process of monitoring data transmission and determining when errors
have occurred. Error-detection techniques neither correct errors nor identify which bits are
in error—they indicate only when an error has occurred. The purpose of error detection is
not to prevent errors from occurring but to prevent undetected errors from occurring.
The most common error-detection techniques are redundancy checking, which in-
cludes vertical redundancy checking, checksum, longitudinal redundancy checking, and
cyclic redundancy checking.

5-1 Redundancy Checking

Duplicating each data unit for the purpose of detecting errors is a form of error detection
called redundancy. Redundancy is an effective but rather costly means of detecting errors,
especially with long messages. It is much more efficient to add bits to data units that check
for transmission errors. Adding bits for the sole purpose of detecting errors is called
redundancy checking. There are four basic types of redundancy checks: vertical redundancy
checking, checksums, longitudinal redundancy checking, and cyclic redundancy checking.
5-1-1 Vertical redundancy checking. Vertical redundancy checking (VRC) is
probably the simplest error-detection scheme and is generally referred to as character par-
ity or simply parity. With character parity, each character has its own error-detection bit
called the parity bit. Since the parity bit is not actually part of the character, it is considered
a redundant bit. An n-character message would have n redundant parity bits. Therefore, the
number of error-detection bits is directly proportional to the length of the message.
With character parity, a single parity bit is added to each character to force the total
number of logic 1s in the character, including the parity bit, to be either an odd number (odd
parity) or an even number (even parity). For example, the ASCII code for the letter C is 43
hex, or P1000011 binary, where the P bit is the parity bit. There are three logic 1s in the
code, not counting the parity bit. If odd parity is used, the P bit is made a logic 0, keeping
the total number of logic 1s at three, which is an odd number. If even parity is used, the P
bit is made a logic 1, making the total number of logic 1s four, which is an even number.
The primary advantage of parity is its simplicity. The disadvantage is that when an
even number of bits are received in error, the parity checker will not detect them because
when the logic condition of an even number of bits is changed, the parity of the character
remains the same. Consequently, over a long time, parity will theoretically detect only 50%
of the transmission errors (this assumes an equal probability that an even or an odd number
of bits could be in error).
Example 2
Determine the odd and even parity bits for the ASCII character R.
Solution The hex code for the ASCII character R is 52, which is P1010010 in binary, where P des-
ignates the parity bit.

161
 Fundamental Concepts of Data Communications

For odd parity, the parity bit is a 0 because 52 hex contains three logic 1s, which is an odd num-
ber. Therefore, the odd-parity bit sequence for the ASCII character R is 01010010.
For even parity, the parity bit is 1, making the total number of logic 1s in the eight-bit sequence
four, which is an even number. Therefore, the even-parity bit sequence for the ASCII character R is
11010010.
Other forms of parity include marking parity (the parity bit is always a 1), no parity (the par-
ity bit is not sent or checked), and ignored parity (the parity bit is always a 0 bit if it is ignored). Mark-
ing parity is useful only when errors occur in a large number of bits. Ignored parity allows receivers
that are incapable of checking parity to communicate with devices that use parity.

5-1-2 Checksum. Checksum is another relatively simple form of redundancy error

checking where each character has a numerical value assigned to it. The characters within
a message are combined together to produce an error-checking character (checksum),
which can be as simple as the arithmetic sum of the numerical values of all the characters
in the message. The checksum is appended to the end of the message. The receiver repli-
cates the combining operation and determines its own checksum. The receiver’s checksum
is compared to the checksum appended to the message, and if they are the same, it is as-
sumed that no transmission errors have occurred. If the two checksums are different, a
transmission error has definitely occurred.

5-1-3 Longitudinal redundancy checking. Longitudinal redundancy checking

(LRC) is a redundancy error detection scheme that uses parity to determine if a transmis-
sion error has occurred within a message and is therefore sometimes called message parity.
With LRC, each bit position has a parity bit. In other words, b0 from each character in the
message is XORed with b0 from all the other characters in the message. Similarly, b1, b2,
and so on are XORed with their respective bits from all the characters in the message. Es-
sentially, LRC is the result of XORing the “character codes” that make up the message,
whereas VRC is the XORing of the bits within a single character. With LRC, even parity is
generally used, whereas with VRC, odd parity is generally used.
The LRC bits are computed in the transmitter while the data are being sent and then
appended to the end of the message as a redundant character. In the receiver, the LRC is re-
computed from the data, and the recomputed LRC is compared to the LRC appended to the
message. If the two LRC characters are the same, most likely no transmission errors have
occurred. If they are different, one or more transmission errors have occurred.
Example 3 shows how are VRC and LRC are calculated and how they can be used to-
gether.

Example 3
Determine the VRCs and LRC for the following ASCII-encoded message: THE CAT. Use odd parity
for the VRCs and even parity for the LRC.
Solution
Character T H E sp C A T LRC
Hex 54 48 45 20 43 41 54 2F
ASCII code b0 0 0 1 0 1 1 0 1
b1 0 0 0 0 1 0 0 1
b2 1 0 1 0 0 0 1 1
b3 0 1 0 0 0 0 0 1
b4 1 0 0 0 0 0 1 0
b5 0 0 0 1 0 0 0 1
b6 1 1 1 0 1 1 1 0
Parity bit b7 0 1 0 0 0 1 0 0
(VRC)

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 Fundamental Concepts of Data Communications

The LRC is 00101111 binary (2F hex), which is the character “/” in ASCII. Therefore, after the LRC
character is appended to the message, it would read “THE CAT/.”
The group of characters that comprise a message (i.e., THE CAT) is often called a block or
frame of data. Therefore, the bit sequence for the LRC is often called a block check sequence (BCS)
or frame check sequence (FCS).
With longitudinal redundancy checking, all messages (regardless of their length) have the same
number of error-detection characters. This characteristic alone makes LRC a better choice for systems
that typically send long messages.
Historically, LRC detects between 95% and 98% of all transmission errors. LRC will not de-
tect transmission errors when an even number of characters has an error in the same bit position. For
example, if b4 in an even number of characters is in error, the LRC is still valid even though multiple
transmission errors have occurred.

5-1-4 Cyclic redundancy checking. Probably the most reliable redundancy check-
ing technique for error detection is a convolutional coding scheme called cyclic redundancy
checking (CRC). With CRC, approximately 99.999% of all transmission errors are de-
tected. In the United States, the most common CRC code is CRC-16. With CRC-16, 16 bits
are used for the block check sequence. With CRC, the entire data stream is treated as a long
continuous binary number. Because the BCS is separate from the message but transported
within the same transmission, CRC is considered a systematic code. Cyclic block codes are
often written as (n, k) cyclic codes where n  bit length of transmission and k  bit length
of message. Therefore, the length of the BCC in bits is
BCC  n  k
A CRC-16 block check character is the remainder of a binary division process. A
data message polynominal G(x) is divided by a unique generator polynominal function
P(x), the quotient is discarded, and the remainder is truncated to 16 bits and appended
to the message as a BCS. The generator polynominal must be a prime number (i.e., a
number divisible by only itself and 1). CRC-16 detects all single-bit errors, all double-
bit errors (provided the divisor contains at least three logic 1s), all odd number of bit
errors (provided the division contains a factor 11), all error bursts of 16 bits or less, and
99.9% of error bursts greater than 16 bits long. For randomly distributed errors, it is es-
timated that the likelihood of CRC-16 not detecting an error is 1014, which equates
to one undetected error every two years of continuous data transmission at a rate of
1.544 Mbps.
With CRC generation, the division is not accomplished with standard arithmetic di-
vision. Instead, modulo-2 division is used, where the remainder is derived from an exclu-
sive OR (XOR) operation. In the receiver, the data stream, including the CRC code, is di-
vided by the same generating function P(x). If no transmission errors have occurred, the
remainder will be zero. In the receiver, the message and CRC character pass through a block
check register. After the entire message has passed through the register, its contents should
be zero if the receive message contains no errors.
Mathematically, CRC can be expressed as
G1x2
 Q1x2  R1x2 (1)
P1x2
where G(x)  message polynominal
P(x)  generator polynominal
Q(x)  quotient
R(x)  remainder
The generator polynomial for CRC-16 is
P(x)  x16  x15  x2  x0

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 Fundamental Concepts of Data Communications

CRC-16 polynominal, G(x) = X16 + X15 + X2 + X0

X2 X15 X16

15 14 + 13 12 11 10 9 8 7 6 5 4 3 2 1 + 0 +
MSB XOR XOR LSB XOR

Data input
BCC output

FIGURE 5 CRC-16 generating circuit

The number of bits in the CRC code is equal to the highest exponent of the gener-
ating polynomial. The exponents identify the bit positions in the generating polynomial
that contain a logic 1. Therefore, for CRC-16, b16, b15, b2, and b0 are logic 1s, and all
other bits are logic 0s. The number of bits in a CRC character is always twice the num-
ber of bits in a data character (i.e., eight-bit characters use CRC-16, six-bit characters use
CRC-12, and so on).
Figure 5 shows the block diagram for a circuit that will generate a CRC-16 BCC. A
CRC generating circuit requires one shift register for each bit in the BCC. Note that there
are 16 shift registers in Figure 5. Also note that an XOR gate is placed at the output of the
shift registers for each bit position of the generating polynomial that contains a logic 1, ex-
cept for x0. The BCC is the content of the 16 registers after the entire message has passed
through the CRC generating circuit.

Example 4
Determine the BCS for the following data and CRC generating polynomials:
Data G(x)  x7  x5  x4  x2  x1  x0
 10110111
CRC P(x)  x5  x4  x1  x0
 110011

Solution First, G(x) is multiplied by the number of bits in the CRC code, which is 5:
x5(x7  x5  x4  x2  x1  x0)  x12  x10  x9  x7  x6  x5  1011011100000
Then the result is divided by P(x):

1 1 0 1 0 1 1 1
1 1 0 0 1 1 | 1 0 1 1 0 1 1 1 0 0 0 0 0
1 1 0 0 1 1
1 1 1 1 0 1
1 1 0 0 1 1
1 1 1 0 1 0
1 1 0 0 1 1
1 0 0 1 0 0
1 1 0 0 1 1
1 0 1 1 1 0
1 1 0 0 1 1
1 1 1 0 1 0
1 1 0 0 1 1
0 1 0 0 1  CRC

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 Fundamental Concepts of Data Communications

The CRC is appended to the data to give the following data stream:
G(x) CRC

兵
兵
1 0 1 1 0 1 1 1 0 1 0 0 1

At the receiver, the data are again divided by P(x) :

1 1 0 1 0 1 1 1
1 1 0 0 1 1 | 1 0 1 1 0 1 1 1 0 1 0 0 1
1 1 0 0 1 1
1 1 1 1 0 1
1 1 0 0 1 1
1 1 1 0 1 0
1 1 0 0 1 1
1 0 0 1 1 0
1 1 0 0 1 1
1 0 1 0 1 0
1 1 0 0 1 1
1 1 0 0 1 1
1 1 0 0 1 1
0 0 0 0 0 0 Remainder  0,
which means there
were no transmis-
sion errors

6 ERROR CORRECTION

Although detecting errors is an important aspect of data communications, determining what

to do with data that contain errors is another consideration. There are two basic types of er-
ror messages: lost message and damaged message. A lost message is one that never arrives
at the destination or one that arrives but is damaged to the extent that it is unrecognizable.
A damaged message is one that is recognized at the destination but contains one or more
transmission errors.
Data communications network designers have developed two basic strategies for han-
dling transmission errors: error-detecting codes and error-correcting codes. Error-de-
tecting codes include enough redundant information with each transmitted message to en-
able the receiver to determine when an error has occurred. Parity bits, block and frame
check characters, and cyclic redundancy characters are examples of error-detecting codes.
Error-correcting codes include sufficient extraneous information along with each message
to enable the receiver to determine when an error has occurred and which bit is in error.
Transmission errors can occur as single-bit errors or as bursts of errors, depending on
the physical processes that caused them. Having errors occur in bursts is an advantage when
data are transmitted in blocks or frames containing many bits. For example, if a typical
frame size is 10,000 bits and the system has a probability of error of 104 (one bit error in
every 10,000 bits transmitted), independent bit errors would most likely produce an error
in every block. However, if errors occur in bursts of 1000, only one or two blocks out of
every 1000 transmitted would contain errors. The disadvantage of bursts of errors is they
are more difficult to detect and even more difficult to correct than isolated single-bit errors.
In the modern world of data communications, there are two primary methods used for er-
ror correction: retransmission and forward error correction.

6-1 Retransmission
Retransmission, as the name implies, is when a receive station requests the transmit station to re-
send a message (or a portion of a message) when the message is received in error. Because the
receive terminal automatically calls for a retransmission of the entire message, retransmission

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 Fundamental Concepts of Data Communications

is often called ARQ, which is an old two-way radio term that means automatic repeat request or
automatic retransmission request.ARQ is probably the most reliable method of error correction,
although it is not necessarily the most efficient. Impairments on transmission media often occur
in bursts. If short messages are used, the likelihood that impairments will occur during a trans-
mission is small. However, short messages require more acknowledgments and line turnarounds
than do long messages. Acknowledgments are when the recipient of data sends a short message
back to the sender acknowledging receipt of the last transmission. The acknowledgment can in-
dicate a successful transmission (positive acknowledgment) or an unsuccessful transmission
(negative acknowledgment). Line turnarounds are when a receive station becomes the transmit
station, such as when acknowledgments are sent or when retransmissions are sent in response
to a negative acknowledgment. Acknowledgments and line turnarounds for error control are
forms of overhead (data other than user information that must be transmitted). With long mes-
sages, less turnaround time is needed, although the likelihood that a transmission error will oc-
cur is higher than for short messages. It can be shown statistically that messages between 256
and 512 characters long are the optimum size for ARQ error correction.
There are two basic types of ARQ: discrete and continuous. Discrete ARQ uses ac-
knowledgments to indicate the successful or unsuccessful reception of data. There are two
basic types of acknowledgments: positive and negative. The destination station responds
with a positive acknowledgment when it receives an error-free message. The destination sta-
tion responds with a negative acknowledgment when it receives a message containing er-
rors to call for a retransmission. If the sending station does not receive an acknowledgment
after a predetermined length of time (called a time-out), it retransmits the message. This is
called retransmission after time-out.
Another type of ARQ, called continuous ARQ, can be used when messages are di-
vided into smaller blocks or frames that are sequentially numbered and transmitted in suc-
cession, without waiting for acknowledgments between blocks. Continuous ARQ allows
the destination station to asynchronously request the retransmission of a specific frame (or
frames) of data and still be able to reconstruct the entire message once all frames have been
successfully transported through the system. This technique is sometimes called selective
repeat, as it can be used to call for a retransmission of an entire message or only a portion
of a message.

6-2 Forward Error Correction

Forward error correction (FEC) is the only error-correction scheme that actually detects
and corrects transmission errors when they are received without requiring a retransmission.
With FEC, redundant bits are added to the message before transmission. When an error is
detected, the redundant bits are used to determine which bit is in error. Correcting the bit is
a simple matter of complementing it. The number of redundant bits necessary to correct er-
rors is much greater than the number of bits needed to simply detect errors. Therefore, FEC
is generally limited to one-, two-, or three-bit errors.
FEC is ideally suited for data communications systems when acknowledgments are
impractical or impossible, such as when simplex transmissions are used to transmit mes-
sages to many receivers or when the transmission, acknowledgment, and retransmission
time is excessive, for example when communicating to far away places, such as deep-space
vehicles. The purpose of FEC codes is to eliminate the time wasted for retransmissions.
However, the addition of the FEC bits to each message wastes time itself. Obviously, a
trade-off is made between ARQ and FEC, and system requirements determine which
method is best suited to a particular application. Probably the most popular error-correction
code is the Hamming code.

6-2-1 Hamming code. A mathematician named Richard W. Hamming, who was an

early pioneer in the development of error-detection and -correction procedures, developed

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 Fundamental Concepts of Data Communications

One data unit contains m + n bits

d1 d2 d3 d4 d5 d6 dm h1 h2 h3 hn

m data bits n Hamming bits

FIGURE 6 Data unit comprised of m character bits and n Hamming bits

the Hamming code while working at Bell Telephone Laboratories. The Hamming code is
an error-correcting code used for correcting transmission errors in synchronous data
streams. However, the Hamming code will correct only single-bit errors. It cannot correct
multiple-bit errors or burst errors, and it cannot identify errors that occur in the Hamming
bits themselves. The Hamming code, as with all FEC codes, requires the addition of over-
head to the message, consequently increasing the length of a transmission.
Hamming bits (sometimes called error bits) are inserted into a character at random lo-
cations. The combination of the data bits and the Hamming bits is called the Hamming code.
The only stipulation on the placement of the Hamming bits is that both the sender and the
receiver must agree on where they are placed. To calculate the number of redundant Ham-
ming bits necessary for a given character length, a relationship between the character bits
and the Hamming bits must be established. As shown in Figure 6, a data unit contains m
character bits and n Hamming bits. Therefore, the total number of bits in one data unit is
m  n. Since the Hamming bits must be able to identify which bit is in error, n Hamming bits
must be able to indicate at least m  n  1 different codes. Of the m  n codes, one code in-
dicates that no errors have occurred, and the remaining m  n codes indicate the bit position
where an error has occurred. Therefore, m  n bit positions must be identified with n bits.
Since n bits can produce 2n different codes, 2n must be equal to or greater than m  n  1.
Therefore, the number of Hamming bits is determined by the following expression:
2n ≥ m  n  1 (2)
where n  number of Hamming bits
m  number of bits in each data character
A seven-bit ASCII character requires four Hamming bits (24 > 7  4  1), which
could be placed at the end of the character bits, at the beginning of the character bits, or in-
terspersed throughout the character bits. Therefore, including the Hamming bits with
ASCII-coded data requires transmitting 11 bits per ASCII character, which equates to a
57% increase in the message length.

Example 5
For a 12-bit data string of 101100010010, determine the number of Hamming bits required, arbitrar-
ily place the Hamming bits into the data string, determine the logic condition of each Hamming bit,
assume an arbitrary single-bit transmission error, and prove that the Hamming code will successfully
detect the error.
Solution Substituting m  12 into Equation 2, the number of Hamming bits is
for n  4 24  16 ≥ 12  4  1  17
Because 16 < 17, four Hamming bits are insufficient:
for n  5 25  32 ≥ 12  5  1  18
Because 32 > 18, five Hamming bits are sufficient, and a total of 17 bits make up the data stream (12
data plus five Hamming).

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 Fundamental Concepts of Data Communications

Arbitrarily placing five Hamming bits into bit positions 4, 8, 9, 13, and 17 yields
bit position 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
H 1 0 1 H 1 0 0 H H 0 1 0 H 0 1 0
To determine the logic condition of the Hamming bits, express all bit positions that contain a logic 1
as a five-bit binary number and XOR them together:
Bit position Binary number
2 00010
6 00110
XOR 00100
12 01100
XOR 01000
14 01110
XOR 00110
16 10000
XOR 10110  Hamming bits
b17  1, b13  0, b9  1, b8  1, b4  0
The 17-bit Hamming code is
H H H H H
1 1 0 1 0 1 0 0 1 1 0 1 0 0 0 1 0
Assume that during transmission, an error occurs in bit position 14. The received data stream is
1 1 0 0 0 1 0 0 1 1 0 1 0 0 0 1 0
兵

error
At the receiver, to determine the bit position in error, extract the Hamming bits and XOR them with
the binary code for each data bit position that contains a logic 1:
Bit position Binary number
Hamming bits 10110
2 00010
XOR 10100
6 00110
XOR 10010
12 01100
XOR 11110
16 10000
XOR 01110  14
Therefore, bit position 14 contains an error.

7 CHARACTER SYNCHRONIZATION

In essence, synchronize means to harmonize, coincide, or agree in time. Character syn-

chronization involves identifying the beginning and end of a character within a message.
When a continuous string of data is received, it is necessary to identify which bits belong
to which characters and which bits are the MSBS and LSBS of the character. In essence,
this is character synchronization: identifying the beginning and end of a character code. In
data communications circuits, there are two formats commonly used to achieve character
synchronization: asynchronous and synchronous.

7-1 Asynchronous Serial Data

The term asynchronous literally means “without synchronism,” which in data communica-
tions terminology means “without a specific time reference.” Asynchronous data transmis-

168
 Fundamental Concepts of Data Communications

Data or
Stop bits Parity bit Data bits Start
(1, 1.5, or 2) (odd/even) (5 to 8) bit

1 or 0
b6
(1) (1) or b7 b5 b4 b3 b2 b1 b0 0
MSB
(MSB) LSB

Time

FIGURE 7 Asynchronous data format

sion is sometimes called start-stop transmission because each data character is framed be-
tween start and stop bits. The start and stop bits identify the beginning and end of the char-
acter, so the time gaps between characters do not present a problem. For asynchronously
transmitted serial data, framing characters individually with start and stop bits is sometimes
said to occur on a character-by-character basis.
Figure 7 shows the format used to frame a character for asynchronous serial data
transmission. The first bit transmitted is the start bit, which is always a logic 0. The char-
acter bits are transmitted next, beginning with the LSB and ending with the MSB. The data
character can contain between five and eight bits. The parity bit (if used) is transmitted di-
rectly after the MSB of the character. The last bit transmitted is the stop bit, which is always
a logic 1, and there can be either one, one and a half, or two stop bits. Therefore, a data char-
acter may be comprised of between seven and 11 bits.
A logic 0 is used for the start bit because an idle line condition (no data transmis-
sion) on a data communications circuit is identified by the transmission of continuous
logic 1s (called idle line 1s). Therefore, the start bit of a character is identified by a high-
to-low transition in the received data, and the bit that immediately follows the start bit is
the LSB of the character code. All stop bits are logic 1s, which guarantees a high-to-low
transition at the beginning of each character. After the start bit is detected, the data and par-
ity bits are clocked into the receiver. If data are transmitted in real time (i.e., as the opera-
tor types data into the computer terminal), the number of idle line 1s between each char-
acter will vary. During this dead time, the receive will simply wait for the occurrence of
another start bit (i.e., high-to-low transition) before clocking in the next character. Obvi-
ously, both slipping over and slipping under produce errors. However, the errors are some-
what self-inflicted, as they occur in the receiver and are not a result of an impairment that
occurred during transmission.
With asynchronous data, it is not necessary that the transmit and receive clocks be
continuously synchronized; however, their frequencies should be close, and they should be
synchronized at the beginning of each character. When the transmit and receive clocks are
substantially different, a condition called clock slippage may occur. If the transmit clock
is substantially lower than the receive clock, underslipping occurs. If the transmit clock is
substantially higher than the receive clock, a condition called overslipping occurs. With
overslipping, the receive clock samples the receive data slower than the bit rate. Conse-
quently, each successive sample occurs later in the bit time until finally a bit is completely
skipped.
Example 6
For the following sequence of bits, identify the ASCII-encoded character, the start and stop bits, and
the parity bits (assume even parity and two stop bits):

169
 Fundamental Concepts of Data Communications

Solution
time
1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 1 1 1 1 0 0 0 1 0 0 0
one asynchronous character one asynchronous character

Idle line Stop Start Stop Start

41 hex 44 hex
ones bits bit bits bit
A D

1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 1 1 1 1 0 0 0 1 0 0 0

MSB LSB MSB LSB

Parity Parity
bit bit

7-2 Synchronous Serial Data

Synchronous data generally involves transporting serial data at relatively high speeds in
groups of characters called blocks or frames. Therefore, synchronous data are not sent in
real time. Instead, a message is composed or formulated and then the entire message is
transmitted as a single entity with no time lapses between characters. With synchronous
data, rather than frame each character independently with start and stop bits, a unique se-
quence of bits, sometimes called a synchronizing (SYN) character, is transmitted at the be-
ginning of each message. For synchronously transmitted serial data, framing characters in
blocks is sometimes said to occur on a block-by-block basis. For example, with ASCII code,
the SYN character is 16 hex. The receiver disregards incoming data until it receives one or
more SYN characters. Once the synchronizing sequence is detected, the receiver clocks in
the next eight bits and interprets them as the first character of the message. The receiver
continues clocking in bits, interpreting them in groups of eight until it receives another
unique character that signifies the end of the message. The end-of-message character varies
with the type of protocol being used and what type of message it is associated with. With
synchronous data, the transmit and receive clocks must be synchronized because character
synchronization occurs only once at the beginning of a message.
With synchronous data, each character has two or three bits added to each character
(one start and either one, one and a half, or two stop bits). These bits are additional over-
head and, thus, reduce the efficiency of the transmission (i.e., the ratio of information bits
to total transmitted bits). Synchronous data generally has two SYN characters (16 bits of
overhead) added to each message. Therefore, asynchronous data are more efficient for short
messages, and synchronous data are more efficient for long messages.

Example 7
For the following string of ASCII-encoded characters, identify each character (assume odd parity):
Solution
time
0 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 0 1 1
4F hex 54 hex 16 hex
O T SYN Character

0 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 0 1 1

MSB LSB MSB LSB MSB LSB

Parity Parity Parity

bit bit bit

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 Fundamental Concepts of Data Communications

QUESTIONS
1. Define data communications code.
2. Give some of the alternate names for data communications codes.
3. Briefly describe the following data communications codes: Baudot, ASCII, and EBCDIC.
4. Describe the basic concepts of bar codes.
5. Describe a discrete bar code; continuous bar code; 2D bar code.
6. Explain the encoding formats used with Code 39 and UPC bar codes.
7. Describe what is meant by error control.
8. Explain the difference between error detection and error correction.
9. Describe the difference between redundancy and redundancy checking.
10. Explain vertical redundancy checking.
11. Define odd parity; even parity; marking parity.
12. Explain the difference between no parity and ignored parity.
13. Describe how checksums are used for error detection.
14. Explain longitudinal redundancy checking.
15. Describe the difference between character and message parity.
16. Describe cyclic redundancy checking.
17. Define forward error correction.
18. Explain the difference between using ARQ and a Hamming code.
19. What is meant by character synchronization?
20. Compare and contrast asynchronous and synchronous serial data formats.
21. Describe the basic format used with asynchronous data.
22. Define the start and stop bits.
23. Describe synchronous data.
24. What is a SYN character?
25. Define and give some examples of data terminal equipment.
26. Define and give examples of data communications equipment.
27. List and describe the basic components that make up a data communications circuit.
28. Define line control unit and describe its basic functions in a data communications circuit.
29. Describe the basic functions performed by a UART.
30. Describe the operation of a UART transmitter and receiver.
31. Explain the operation of a start bit verification circuit.
32. Explain clock slippage and describe the effects of slipping over and slipping under.
33. Describe the differences between UARTs, USRTs, and USARTs.
34. List the features provided by serial interfaces.
35. Describe the purpose of a serial interface.
36. Describe the physical, electrical, and functional characteristics of the RS-232 interface.
37. Describe the RS-449 interface and give the primary differences between it and the RS-232 in-
terface.
38. Describe data communications modems and explain where they are used in data communications
circuits.
39. What is meant by a Bell System–compatible modem?
40. What is the difference between asynchronous and synchronous modems?
41. Define modem synchronization and list its functions.
42. Describe modem equalization.
43. Briefly describe the following ITU-T modem recommendations: V.29, V.32, V.32bis, V.32terbo,
V.33, V.42, V.42bis, V.32fast, and V.34.

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 Fundamental Concepts of Data Communications

PROBLEMS
1. Determine the hex codes for the following Baudot codes: C, J, 4, and /.
2. Determine the hex codes for the following ASCII codes: C, J, 4, and /.
3. Determine the hex codes for the following EBCDIC codes: C, J, 4, and /.
4. Determine the left- and right-hand UPC label format for the digit 4.
5. Determine the LRC and VRC for the following message (use even parity for LRC and odd par-
ity for VCR):

D A T A sp C O M M U N I C A T I O N S

6. Determine the LRC and VRC for the following message (use even parity for LRC and odd par-
ity for VCR):

A S C I I sp C O D E

7. Determine the BCS for the following data- and CRC-generating polynomials:

G(x)  x7  x4  x2  x0  1 0 0 1 0 1 0 1
P(x)  x5  x4  x1  x0  1 1 0 0 1 1
8. Determine the BCC for the following data- and CRC-generating polynomials:

G(x)  x8  x5  x2  x0
P(x)  x5  x4  x1  x0

9. How many Hamming bits are required for a single EBCDIC character?
10. Determine the Hamming bits for the ASCII character “B.” Insert the hamming bits into every
other bit location starting from the left.
11. Determine the Hamming bits for the ASCII character “C” (use odd parity and two stop bits). In-
sert the Hamming bits into every other location starting at the right.
12. Determine the noise margins for an RS-232 interface with driver output signal voltages of 12
V.
13. Determine the noise margins for an RS-232 interface with driver output signal voltages of
11 V.

ANSWERS TO SELECTED PROBLEMS

1. C  0E, J  1A, 4  0A, /  17
3. C  C3, J  D1, 4  F4, /  61
5. 10100000 binary, A0 hex
7. 1000010010100000 binary, 84A0 hex
9. 4
11. Hamming bits  0010 in positions 8, 6, 4, and 2
13. 8V

212