Sheet 7
Sheet 7
Part A: The following table gives the parameters for a number of different caches, where m is the
number of physical address bits, C is the cache size (number of data bytes), B is the block size
in bytes, and E is the number of lines per set. For each cache, determine the number of cache
sets (S), tag bits (t), set index bits (s), and block offset bits (b).
Cache m C B E S t s b
1. 32 1024 4 4
2. 32 1024 4 256
3. 32 1024 8 1
4. 32 1024 8 128
5. 32 1024 32 1
6. 32 1024 32 4
Parts B, C, and D concern basic cache lookups.
● The memory is byte addressable.
● Memory accesses are to 1-byte words.
● Physical addresses are 12 bits wide.
● The cache is 4-way set associative, with a 4 byte line size and 8 total lines.
In the following tables, all numbers are given in hexadecimal. The contents of the cache are as
follows:
S0 058 0 02 55 AD 87
S0 123 1 3E 98 47 51
S0 12B 0 6C 77 89 14
S0 0EF 1 B9 64 78 25
S1 069 0 00 FF 14 43
S1 12B 1 92 63 42 21
S1 075 0 33 BE AF 31
S1 1C6 1 22 17 02 24
Part B
The box below shows the format of a physical address. Indicate (by labeling the diagram) the
fields that would be used to determine the following:
For the given physical address, indicate the cache entry accessed and the cache byte value
returned in hex. Indicate whether a cache miss occurs.
In the box below, write out the physical address (one bit per box).
11 10 9 8 7 6 5 4 3 2 1 0
Parameter Value
Block offset 0x
Set Index 0x
Cache Tag 0x
For the given physical address, indicate the cache entry accessed and the cache byte value
returned in hex. Indicate whether a cache miss occurs.
In the box below, write out the physical address (one bit per box).
11 10 9 8 7 6 5 4 3 2 1 0
Parameter Value
Block offset 0x
Set Index 0x
Cache Tag 0x