2023 International Conference on Technology and Policy in Energy and Electric Power (ICT-PEP)

Implementation of FIR Digital Filters on FPGA

Board for Real-Time Audio Processing
Fahad Syed Wasid Ali
Department of Electrical Engineering Department of Electrical Engineering
National Institute of Technology Srinagar National Institute of Technology Srinagar
Srinagar (J&K), India Srinagar (J&K), India
[email protected] [email protected]
2023 International Conference on Technology and Policy in Energy and Electric Power (ICT-PEP) | 979-8-3503-6971-7/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICT-PEP60152.2023.10351182

Adarsh Kumar Farhad Ilahi Bakhsh, SMIEEE

Department of Electrical Engineering Department of Electrical Engineering
National Institute of Technology Srinagar National Institute of Technology Srinagar
Srinagar (J&K), India Srinagar (J&K), India
[email protected] [email protected]

Abstract—This research paper presents the filters are widely used in various audio applications, such
implementation of digital filters on an FPGA platform for as frequency shaping, noise removal, and signal
real-time audio signal processing. The paper utilizes the enhancement. We justify the choice of these filters based
Basys-3 field programmable gate array (FPGA) board and on their relevance to audio processing and the human
the peripheral module (PMOD) I2S2 accessory to process auditory spectrum's frequency range.
audio data using digital finite impulse response (FIR) filters.
The extension of the filter kernel length is achieved by To optimize the filter performance and resource
converting the dual-channel input to a single-channel output, utilization, we explore techniques to extend the filter
and the use of free LUTs (Look Up Tables) as digital signal kernel length. We demonstrate how the conversion from
processing (DSP) multipliers, optimizing the utilization of dual-channel input to single-channel output allows for a
available resources. The successful implementation of the larger kernel length, maximizing the utilization of the
filters highlighted the potential for FPGA-based solutions in available resources on the FPGA. Furthermore, we
audio engineering and digital signal processing. The results investigate the utilization of free Look-Up Tables (LUTs)
provide valuable insights that can guide future work in as Digital Signal Processing (DSP) multipliers, enabling
optimizing FPGA-based digital filters for audio engineering. additional computational capacity without consuming
extra resources.
Keywords—digital filter, field programmable gate array
(FPGA), digital signal processing (DSP). The research presented in this paper contributes to
FPGA-based audio signal processing by showing the
I. INTRODUCTION feasibility and effectiveness of implementing digital filters
on the Basys-3 FPGA board. The outcomes of our paper
Digital signal processing techniques have provide valuable insights into the design and optimization
revolutionized the field of audio engineering by enabling of real-time audio processing systems using FPGAs. The
advanced manipulation and analysis of audio signals [1]. findings and methodologies discussed in this paper lay the
Real-time processing of audio data is crucial for groundwork for further advancements in FPGA-based
applications such as audio effects, noise cancellation, audio processing and inspire future research and
speech recognition, and audio enhancement. Field- innovation in this domain.
Programmable Gate Arrays (FPGAs) have emerged as a
powerful platform for implementing real-time signal
processing systems due to their reconfigurability, parallel II. LITERATURE REVIEW
processing capabilities, and low latency. In this paper, we
present an implementation of FIR digital filters on an A. Introduction to FPGAs
FPGA platform for real-time audio signal processing. Field-Programmable Gate Arrays (FPGAs) have
emerged as powerful hardware platforms for implementing
This paper aims to demonstrate the capabilities of various digital signal processing (DSP) applications,
FPGAs to design and implement efficient and high- including real-time audio processing. FPGAs are
performance digital filters. The chosen platform for our programmable semiconductor devices that consist of an
paper is the Basys-3 FPGA board, which offers a rich set array of configurable logic blocks (CLBs), embedded
of resources and peripherals suitable for audio processing memory blocks (BRAM), digital signal processing blocks
applications. To interface with audio sources, we utilize (DSPs), and input/output (I/O) blocks interconnected by a
the PMOD I2S2 accessory, which provides a convenient network of programmable routing resources. What sets
interface for transmitting audio data into and out of the FPGAs apart from other devices is their reconfigurability.
FPGA. This combination of hardware components forms Unlike ASICs, which are designed for specific functions
the foundation for our FPGA-based audio signal and cannot be altered once manufactured, FPGAs can be
processing system. programmed and reprogrammed to implement different
In this paper, we focus on the implementation of functionalities, making them highly adaptable to changing
essential filters for audio processing, including low-pass, requirements.
high-pass, band-pass, and moving average filters. These

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B. Past Research
The implementation of FIR digital filters on FPGA boards
for real-time audio processing has been an active area of
research in recent years. Several studies have been
conducted to design and implement FIR filters for audio
signal processing on FPGA platforms [2][3][4][5]. These
studies have focused on improving the efficiency and
performance of FIR filters for real-time audio processing.
One study proposed a real-time audio denoising system
using digital FIR filters with FPGA implementation [3].
The study aimed to overcome the complexity of analog
filter implementation by employing digital filters. Another
study implemented an audio enhancement technique using
digital FIR filters on FPGA to separate signal components
based on their frequency contents [5]. Researchers have
also explored the design and implementation of
communication digital FIR filters for audio signals on Fig. 2. Block Diagram of Setup
FPGA platforms [2][4]. In this paper, however, we restrict To facilitate audio data transmission into and out of the
ourselves to a generic but extensible implementation of a FPGA, we utilize the PMOD I2S2 accessory which is
FIR Filters on the Basys-3 platform to serve as a reference presented in Fig. 2. The PMOD I2S2 is a PMOD
for further implementations and improvements. (peripheral module) specifically designed for audio
applications. It supports the Inter-IC Sound (I2S) protocol,
III. METHODOLOGY a widely used standard for digital audio communication.
The PMOD I2S2 enables bidirectional audio data transfer
A. Hardware between the FPGA and external audio devices, such as
In this section, the hardware components employed in microphones, speakers, or audio codecs. By leveraging the
the implementation of digital filters for real-time audio capabilities of the PMOD I2S2, we can efficiently process
processing has been discussed. The paper utilizes the audio signals in real-time using the FPGA's computational
Basys-3 FPGA board and the PMOD I2S2 accessory, both power.
of which play pivotal roles in enabling efficient and
effective audio filtering. The successful implementation of our FPGA-based
audio signal processing system relies on the integration of
The Basys-3 FPGA board, manufactured by Digilent, various other components including an audio source,
serves as the primary hardware platform for the paper software to program the FPGA, and a speaker. The audio
shown in Fig. 1. The Basys-3 board features a Xilinx source in our setup is a smartphone equipped with a
Artix-7 FPGA [7], offering 33,280 logic cells in 5200 3.5mm audio jack, which plays back the sound to be
slices, along with 90 DSP slices, which provides ample processed. The software tool used for programming the
resources for implementing complex digital signal FPGA and flashing it with the designed System Verilog
processing algorithms, including digital filters. code is Xilinx Vivado. This powerful software suite
Additionally, it offers a range of input/output interfaces, enables the configuration and control of the FPGA,
including through PMOD accessories, allowing for facilitating the execution of our audio processing
seamless integration with external devices and peripherals, algorithms. Lastly, the Beoplay A1 speaker with a 3.5mm
making it well-suited for audio processing applications. audio jack serves as the output device, playing back the
analog audio signal generated by the FPGA. The seamless
integration of these components forms a comprehensive
audio processing system, enabling real-time signal
manipulation, and demonstrating the practical application
of FPGA technology in the audio domain.

IV. FILTER DESIGN

A. Choice of Filters
When designing digital filters for audio applications,
several constraints need to be considered to ensure optimal
performance and compatibility with the target hardware. In
the context of audio processing on a FPGA board, the
following constraints are particularly relevant: the audio
spectrum, the available DSP units on the FPGA, and the
sampling frequency. The human audio spectrum, which
encompasses the range of audible frequencies, typically
extends from 20 Hz to 20 kHz. To accurately process
audio signals within this frequency range, it is essential to
Fig. 1. Digilent Basys-3 FPGA Board view.
choose filters that provide sufficient frequency response

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coverage. The filters should be designed to handle TABLE I: RESOURCE UTILIZATION OF 45-TAP DUAL-CHANNEL FILTER
frequencies from 20 Hz to 20 kHz without significant Utilization
attenuation or distortion in their passband, and sufficient Site Type
Used Available % Utilization
attenuation in their stopbands so that an average human
can hear the effects of the filters. Slice LUTs 383 20800 1.84%

DSPs 90 90 100%
Another important consideration is the available
resources on the Basys-3 FPGA board. The board is
equipped with a limited number of DSP units, which are V. IMPLEMENTATION
essential for implementing digital filters efficiently. DSP The Digilent Basys-3 FPGA is programmed in System
units are specialized hardware blocks within the FPGA Verilog using Xilinx Vivado 2019.2. The FIR engine is
designed for digital signal processing operations. The divided into two main files: firbackend.sv and fir.sv. All
number of available DSP units determines the kernel the code can be found in [9]. The file firbackend.sv
length of the filters implemented. In the case of the Basys- contains System Verilog code implements FIR filter
3 FPGA board, having 90 DSP units means the filter engine capable of applying four different filters to
design should consider the utilization of these units to incoming data. It utilizes buffer elements to store the input
achieve the desired audio processing functionality. data and compute the filtered output based on the selected
filter's coefficients. The coefficients for the filters are a
Furthermore, the sampling frequency of the PMOD
part of this file. Based on the currently selected filter, the
I2S2 module plays a crucial role in filter design. The
FIR filter engine computes the output of the filter on
PMOD I2S2 module provides an interface for audio input
receiving each new packet. The output is computed using
and output and operates at a sampling frequency of 44.1
the standard formula for FIR filters, multiplying the
kHz [8]. This sampling frequency represents the number of
coefficients with the corresponding buffer values, and
samples taken per second from the analog audio signal. To
accumulating the results.
ensure accurate audio processing, the filters must be
designed to handle the specific sampling frequency of 44.1 The file fir.sv contains modules that handle and
kHz. This involves considering the cutoff frequencies and connect the AXI stream from the PMOD input to the FIR
filter characteristics that are appropriate for this sampling filter backend and forward the output from the FIR filter to
rate to avoid aliasing and ensure accurate reconstruction of the output stream. The file Basys-3-Master.xdc contains
the audio signal. the mapped pins and switches between hardware and
software, and the clocks used.
B. Selected Filters
With regards to the constraints introduced in the A. Resource Utilization
previous section, the following filters were selected to be Based on the synthesis report of the dual-channel 45-
implemented. All these filters are dual channel, with a tap filter, the utilization of resources is given in Table I.
kernel length of 45 for each filter. Although this design effectively utilizes the available DSP
resources with 100% utilization, there is some room for
1. Low-pass Filter with a cut-off frequency of 1KHz.
improvement in terms of LUT (Look Up Tables)
2. High-pass Filter with a cut-off frequency of 2KHz. utilization. This will be the focus of the next section.
3. Band-pass Filter with a passband from 1KHz to 4KHz.
VI. INCREASING THE KERNEL LENGTH
C. Generation of Coefficients Extending the filter kernel length is a crucial
The coefficients for the digital filters were generated consideration in digital signal processing applications. The
using GNU Octave, a high-level programming language kernel length refers to the number of taps or coefficients in
for numerical computations. The “fir1” function is used to the filter, which directly impacts the filter's frequency
generate the filter coefficients. This function creates a response and its ability to accurately process the input
finite impulse response (FIR) filter with the specified signal. We used two techniques to increase the kernel
number of taps and cutoff frequencies. The resulting length of the implemented filters.
coefficients are then scaled to fit within the desired
coefficient width of 16 bits. The code also prints out the A. Using Single-Channel filters instead of Dual-Channel
coefficients in a formatted, human-readable format. [9] filters
By converting the dual-channel input to a single-
channel output, the available resources can now be
dedicated entirely to a single channel, allowing for a
higher number of taps to be accommodated. By utilizing a
single-channel filter, the number of taps or coefficients can
be effectively doubled compared to a dual-channel filter
design with the same available resources. The decision to
use a single-channel filter should be based on the
application's nature and the specific requirements of the
signal processing task. In scenarios where the input signal
contains significant information in both channels, or when
preserving stereo imaging is crucial, a dual-channel filter
may be more appropriate.
Fig. 3. Pictorial view of PMOD I2S2.

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 200
150
100 Kernel Length
50
0

Dual Channel Optimized

Fig. 4. Visual comparison of dual-channel and optimized single-channel
filters.
Fig. 5. Magnitude Response and Phase Shift of the 163-tap single-channel
TABLE II: RESOURCE UTILIZATION OF 163-TAP DUAL-CHANNEL FILTER Low-pass filter

Utilization
Site Type
Used Available % Utilization
Slice LUTs 18948 20800 91.1%

DSPs 90 90 100%

However, when working with signals that do not

necessitate dual-channel processing, employing a single-
channel filter offers a practical solution for extending the
filter kernel length and enhancing the filtering capabilities.
Fig. 6. Magnitude Response and Phase Shift of the 163-tap single-channel
High-pass filter
B. Using Free LUTs as DSP Multipliers
FPGAs consist of an array of LUTs that can be
configured to implement any desired Boolean function. In
many applications, the LUTs are not fully utilized, leaving
some LUTs unused or underutilized. By repurposing these
unused LUTs as DSP multipliers, additional resources can
be made available for extending the filter kernel length.
The process involves mapping the multiplier Digital Signal
Processing (DSP) units of the FPGA to the available free
LUTs. This mapping allows the FPGA to effectively use
the LUTs as multipliers, augmenting the number of
available multiplier blocks beyond the default count Fig. 7. Magnitude Response and Phase Shift of the 163-tap single-channel
provided by the device. In our case, after mapping the Band-pass filter
multiplier DSP units to free LUTs, 73 extra multiplier
As is apparent from all the graphs, the phase response
blocks were obtained. After applying both the techniques
is perfectly linear in the passbands of all the filters. This is
to increase filter length, we could implement single-
one of the chief advantages of FIR Filters [10]. The
channel filters with a length of 163, which is a 262%
transition band is sufficiently sharp for many use-cases,
increase over our original 45-tap dual-channel filters.
but an even longer filter might be required if a sharper
frequency isolation is desired. Future work can focus on
C. Resource Utilization optimizing the filter designs, exploring advanced filter
The new resource utilization is reflective of our attempt algorithms.
to maximize the use of free LUTs which is given in Table
II. VIII. CONCLUSION
The implementation of digital filters on the FPGA
VII. PERFORMANCE
using the Basys-3 board and the PMOD I2S2 accessory
The performance of the filters can be best understood yielded successful results and demonstrated the
by seeing the magnitude response and phase shift of the effectiveness of the approach. Throughout the paper,
filters, as calculated and plotted in GNU Octave as shown various digital FIR filters were designed, implemented,
in Fig. 5, Fig. 6, and Fig. 7. The Fig. 5, Fig. 6, and Fig. 7 and tested.
show the magnitude response and phase-shift of the 163-
tap single-channel low-pass filter, high-pass filter, and The results of the paper showed that the implemented
band-pass filter, respectively. From Fig. 5 it is quite clear filters effectively processed audio data in real-time. The
that low-pass filter can successfully pass the low frequency response of each filter was analysed using
frequencies signal and block the high frequencies signal. frequency sweeps, and the filters demonstrated their ability
Similarly, from Fig. 6 it quite evident that high-pass filter to isolate different elements in audio recordings. The audio
is blocking the low frequency signals and passing the high output from the FPGA-based system exhibited the desired
frequency signals. Further, from Fig. 7 it is visual that filtering characteristics, achieving the intended purpose of
band-pass filter is passing the signal in a limited band audio signal processing. The successful implementation of
range while blocking the low and high frequency signals. the filters highlighted the potential for FPGA-based

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