International Conference on Communication and Signal Processing, April 3-5, 2018, India

IIR Digital Filter Design using Xilinx System

Generator for FPGA Implementation
Priya P and Ashok S


Abstract—In general Application Specific Integrated Circuits filter design requires linear phase characteristics. Whereas IIR
(ASIC) and Digital Signal Processors (DSP) are usually used for filters shows nonlinear characteristics. By using IIR filter, the
implementing digital filters. As compared to the conventional filter order is significantly reduced than that of FIR filter for
methods available the speed of computation of digital filter is
the same frequency response.
increased by implementing on Field Programmable Logic Gate
Array (FPGA). This paper provides a novel design and In several cases the IIR filters can meet the desired
implementation of digital filter in FPGA using a high level specifications with lower order terms, while FIR filters
description tool like Xilinx System Generator. The designed filter contains higher order terms to meet the same specifications.
with desired specification is analyzed in Simulink environment in This is the main advantage of IIR filter over FIR filter. Since
MATLAB. A method for implementing IIR filter in FPGA using the FIR filter contains higher order terms, the computational
System Generator is proposed. The Xilinx system generator is
complexity is more. The computational savings is an
used for synthesizing and simulation for FPGA filter analysis.
The FPGA shows its high performance in terms of speed, important factor in the filter design. IIR filters with lower filter
memory, resource management, and power consumption. order are able to show better frequency response than FIR
filters with same frequency response. In digital signal
Index Terms—Digital Filter; Field Programmable Logic Gate processing, the implementation of IIR filter consistently
Array; Infinite Impulse Response filter; Xilinx System Generator reduces the calculations per time step. Unlike FIR filter, the
IIR filters have nonlinear phase characteristics [6-7]. They
I. INTRODUCTION might almost have linear phase characteristics if the data

T HE fundamental operation in signal processing is

filtering. Many electronic devices are widely using
filtering technique to cancel the redundant part in a signal. The
processing is to be accomplished off line. In this paper the
entire input data signal is made available prior to filtering. In
the case of real time implementation of IIR filter the nonlinear
noise which damages the signal can be easily removed using phase characteristics is not much considered.
filtering technique. Application Specific Integrated Circuits The section II discusses the different IIR filter structure,
(ASIC) and Digital Signal Processors (DSP) are commonly classified mainly into Direct form I and Direct form II. Section
used for digital filter design. In this paper the speed of III describes the architecture for the implementation of the
computation of filter design can be increased extensively digital IIR filter in the Xilinx System Generator platform. The
without affecting the system complexity using the parallelism simulation and hardware results are analyzed in sections IV
feature of Field Programmable Gate Array (FPGA) [1]. and V respectively. Finally, Section VI concludes the paper.
Digital filters are classified into two as Finite Impulse
Response (FIR) filter and Infinite Impulse Response (IIR) II. IIR FILTER STRUCTURE
filter. This paper presents FPGA implementation of IIR filters The IIR filters are often known as recursive digital filters
using Xilinx System generator. FIR filters [2] are digital filters since the filter equation contains both forward path and
with finite impulse response, while IIR filters have infinite feedback path.
impulse response. Since IIR filters are having feedback from
output (a recursive part) they are often known as recursive y (n) = b0 x(n) + b1 x(n-1) + b2 x(n-2) + b3 x(n-3) – a1 y(n-1) -
filters [3]. Consequently, the recursive filters have better a2 y(n-2) - a3 y(n-3) (1)
frequency response as compared to non-recursive FIR filters The Z Transform of the digital filter is given by,
of same order. Thus the implementation of IIR filter in FPGA
[4] will increase the speed of computation since the FPGA is a ( )= X(Z) (2)
parallel processor [5]. FIR filters are commonly used when the
The transfer function of filter will be a rational function where
Priya P is pursuing Post Graduation in the Electrical Engineering
in general both the poles and the zeros are at nonzero locations
Department, National Institute of Technology Calicut, Kerala, India (e-mail: in the z-plane. IIR filters can be designed in various forms like
[email protected]). direct form I, direct form II, Transposed direct form II. The
Ashok S works as the Professor in the Department of Electrical conventional IIR filters available are Butterworth, Chebyshev
Engineering, National Institute of Technology Calicut, Kerala, India (e-mail:
[email protected]).

978-1-5386-3521-6/18/$31.00 ©2018 IEEE

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Type I and Type II, Bessel and Elliptic filter. All these filters A cascaded Direct form II realization technique is
approximate the ideal “brick wall” filter in various ways. implemented in the Xilinx system generator for higher order
filter when area, speed are considered as major constraint [8-
x(n) hb(n) y(n) 9]. The filter coefficients can be designed using Filter Design
X(Z) B(Z) Y(Z) and Analysis (FDA) tool available in the MATLAB. For third
order low pass Butterworth filter [10-11], the filter design
contains 2 separate sections. The coefficients in each section
are implemented in cascaded Direct form II configuration.
Different types of filter can be designed using the FDA tool as
ha(n)
per the requirements.
A(Z)
III. FPGA IMPLEMENTATION OF IIR FILTER
Fig. 1. Block diagram of IIR filter
The Xilinx System Generator environment from MATLAB
By using signal processing tool in MATLAB we can is taken for simulation of the designed filter. The FDA tool in
implement all these different type of filters and can select the signal processing toolbox gives the filter coefficients as
anyone of them according to the specification required. These per the filter specifications. For filtering out the transients
filters can be implemented in both analog domain and digital occurred in a three phase supply, a third order low pass
domain and in low pass, high pass, band pass, band stop Butterworth filter is designed. This filter is used in prior to a
configuration according to the requirements. The block recursive wavelet transform. So the filter specification
diagram of IIR filter is shown in Fig. 1. according to the requirement is given below:
A third order Butterworth low pass IIR filter with cutoff
frequency 320Hz and sampling frequency 16 KHz is designed Filter Specifications:
in this paper. This can be implemented in various ways as Cut off frequency fc = 320 Hz
mentioned above. The direct form I structure is shown below Sampling frequency fs= 16 KHz
(Fig. 2).
b0
X(n) Y(n)
+

Z¯' Z¯'
b1 -a1

+
Z¯' Z¯'

b2 -a2

+
Fig. 2. Direct Form I

The direct form I has more delay terms so it makes the

filter structure bulky. Since the direct form I contain more
delay elements, for the ease of computation we can go for
direct form II structure which shows in Fig. 3. In this
structure, for a Nth order filter the number of delay elements
required is N. That is comparatively less number of delay
elements which makes the speed of computation high and
require less hardware. Fig. 4. IIR filter design using FDA tool

X(n)
b0
Y(n)
The FDA tool in MATLAB which shows in Fig. 4 is used
+ + to design the filter coefficients for specified requirements. And
also any filter like IIR or FIR of low pass, high pass, band
-a1
Z¯'
b1
pass, band stop filter with pass band attenuation, stop band
+ + attenuation can be designed easily. As per the order of filter,
the number of sections in the filter is designed. The
Z¯' architecture for implementing digital filter in System
-a2 b2 Generator is designed using Xilinx block set. The Xilinx block
set consists of adders, multipliers, constants and delays.
Fig. 3. Direct form II

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0055
 Fig. 7. Input Signal to the IIR filter
Fig. 5. Realization of IIR filter in Xilinx system generator

In the architecture shown above, the subsystem block is

modeled as below. The subsystem block is a cascaded
connection of Direct Form II ( Fig. 5). For higher order filter
more number of Direct Form II structure are connected in
cascade form which is shown in Fig. 6. For example, a fifth
order Butterworth filter comprised of three cascaded Direct
Form II structure.

Fig. 8. Filtered Response

V. HARDWARE RESULT
The designed digital filter in Xilinx System Generator is
now implementing in FPGA using WAVECT. The FPGA
based platform offers high-speed serial input/output ports,
embedded processors, arithmetic modules, and plenty of
Fig. 6. Realization of filter in cascade form (Direct form II) memory. The system generator model in MATLAB
generates VHDL code for the Xilinx blocks. The VHDL code
IV. SIMULATION RESULTS is converted into a bin file and that is dumped into Zynq7000
Here in order to filter out the disturbances like switching FPGA board in the WAVECT. The WAVECT consists of
transients with sudden variation in the load, an IIR digital voltage sensors, current sensors, 12-bit Analog to Digital
filter is simulated in Xilinx System Generator. A three phase Converter (ADC) and Zynq7000 FPGA board. The probes
source makes the input to the system. The designed IIR filter connected to the WAVECT shows the results. Using
is capable of filtering out the arriving signal as per the filter WAVECT software in PC the hardware results are obtained.
specifications. In this work a combination of three different The implementation algorithm as a flowchart is shown
sinusoidal signals (50Hz, 320Hz, and 5 KHz) are given as below in Fig. 9. A third order Butterworth filter with cutoff
inputs to IIR filter as given in Fig. 7.The desired cut off frequency 320Hz and sampling frequency 16 KHz was
frequency is maintained at 320Hz thereby removing higher implemented on WAVECT using Xilinx system generator
frequency signals. The filtered response is shows in Fig. 8. (refer Fig. 10).

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0056
 Developing Algorithm
Fig. 11 and Fig. 12 show the hardware implementation using
PC and WAVECT and realization of filter response within the
cutoff frequency using WAVECT respectively.
System Generator
VI. CONCLUSION
This paper describes an approach for IIR digital filter
design using Xilinx system generator and subsequent synthesis
Code Generation
on FPGA. The three phase supply is given as input signal
which may contain transients due to switching, load variation
or lightning, which is filtered to a specific band of frequencies
Xilinx implementation Flow using IIR filter designed in a Xilinx- FPGA platform. The
proposed IIR filter is analysed using Xilinx system generator
model and their performances are verified in terms of
Bitstream Generation computational complexity, power consumption and resource
requirement on FPGA. Implementation of digital filters in
FPGA has increased the computational speed. The filter
design provides flexibility to implement a real time digital
Download bitstream to an
FPGA filter for any applications like image processing, noise
reduction in biomedical field, audio-video filtering etc.
Fig. 9. Flowchart
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Fig. 12. Realization of filtered signal in WAVECT

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