2019 14th IEEE International Conference on Electronic Measurement & Instruments ICEMI’2019

Design of fourth-order IIR digital filter based on FPGA

Zhang Qiang, Sun Jing, Wang Weilian, Yao Ruping, Chen Cheng
School of Information Science & Technology, Yunnan University
Kunming 650500, China
Phone: 18487242992, Email: [email protected]

Abstract —The IIR filte r is a widely used digital signal filter can be realized by cascade or parallel connection. [2]
processing component, which can be roughly classified into The way to achieve the hardware acceleration of the IIR
direct type, cascade type and parallel type. The IIR filte r filter, and finally through the Modelsim simulation of the
coefficients are designed by using MATLAB Buffer function, and FPGA implementation of the filter, the experimental results
implemented on the FPGA using Verilog language. The circuit are consistent with the expected theoretical values. [3]
is composed o f several second-order filte r cascades. When the
sampling frequency is 44.1KHz, the cut-off frequency o f the II. METHODOLOGY
passband is 1KHz, and a sine wave o f 1KHz+3KHz is input.
After different types o f IIR filters, a 1KHz sine wave is output A. filter principle
and passed. Visual graphical and hardware waveform results The IIR type filter is called an infinite impulse
are simulated by MATLAB andModelsim respectively. response filter. It has a simple structure, fast calculation
Keywords — D ig ita l signal processing, IIR digital filter, speed, and less storage space. It has high calculation
Second-order section, FPGA, Modelsim accuracy and good frequency selection characteristics.
The unit impulse response of the IIR filter is
I. INTRODUCTION immeasurable, and the output of the second-order filter of
the previous stage can be recursively input to the input of
The digital filter can be divided into a Finite impulse the next second-order filter, which is a filter with a
response (FIR) filter and an Infinite impulse response (IIR) feedback circuit structure. The transfer function of a
filter. The latter has a lower order, which can save discrete transform of an N-th order IIR digital filter can be
hardware resources and is not strictly linear. Phase represented as [4]
characteristics are one of the most commonly used digital M
filters [1]. E brz r
In order to improve the effective utilization of the H X z) = - ^ N ,(N > M ) (1)
signal and eliminate the high frequency noise in the signal, 1+ Z akz ~k
k=1
the original model of the stable and high speed IIR digital
filter is designed according to the Chebyshev type II Can be represented by a difference equation
function and the Buffer function of the filter in MATLAB.
At present, the design of digital filters mostly stays in the y (n) = E brx(n - r ) + Z a y(n - k) (2)
r=( k=
simulation stage of software. In the hardware
implementation, there are still problems such as the The y(n) consists of two parts. The former is a filter
uncertainty of word length and the fixed point of floating that delays the input signal and has a delay network of M
point multiplication. Since Field-Programmable Gate sections. The latter is a delay network in which the filter
Array (FPGA) can realize parallel operation of functions, delays the output signal and has a total of N sections [5].
the second-order nodal filter can be realized by using Given an input sequence of the system, according to the
fewer logic units in the FPGA without using hardware type and parameters of the given filter, the corresponding
multipliers and IP cores. The hardware acceleration of IIR output sequence signal can be calculated by MATLAB
simulation and Modelsim simulation [6].
978-1-7281-0510-9/19/$31.00 ©2019 IEEE

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 2019 14th IEEE International Conference on Electronic Measurement & Instruments ICEMI’2019

B. Different cascade types offourth-order IIR filters corresponding to direct I and direct II IIR filters are the
There are four cascaded types of this fourth-order same. The four-stage series type and the fourth-order
IIR filter design, which are direct I type, direct type II, parallel type respectively correspond to different system
cascade type, and parallel type. The direct I type system functions.
function (such as formula (1)) is a z-transformation form
of linear invariant system. When the order is N-order, the III. PROPOSED FUSION
zero and pole of the system function can only be full real FRAMEW ORK FOR FAULT
or complex conjugate logarithm [7], so formula (1) can be
DIAGNOSIS
expressed as zero pole
A. ferentframe design offourth-order IIR filter
M M
n (1 - cr z-1) n (1 - p r z 1)(1 - q**z-1) According to the formulas (5), (6), and (7), four
H (z) = A-N0-------------- or H (z) = A -Jf----------------------------
block diagrams of fourth-order IIR filters composed of a
n (1 - dkz-1) n (1 _ qk z"1)(1 - q*z-1)
k=1 k=1 plurality of second-order nodal filters can be drawn, as
shown in Fig. 1 to Fig. 4, respectively.
(3)
In equation (3), A is the extracted constant
coefficient, cr and dk are the poles of the real form of the
system function, pr and qr* represent a pair of conjugate
complex zeros of the system function, and qk and qk*
represent a pair of system functions. Yoke complex pole.
This filter is composed of a second-order filter, so when
the order is 2, the second-order filter system function of
Fig. 1 Direct I type 4th Fig. 2 Direct II type 4th
equation (3) can be expressed as
order IIR filter order IIR filter
1+ h z~ l + b2z ~2 0
------ L- i ---- ^ (4)
1+ a 1z + a 2z
The system functions corresponding to the
fourth-order IIR filter designed in this system are all
cascaded or connected in parallel by formula (4), so the
corresponding system function can be expressed as [8]
Fig. 3 Cascaded 4th order IIR filter
4th order direct type I or type II:

b0 + b1z^ + b2z ^ + b3z ~3 + b4z ^ (5)

-1 -2 -3 -4 (5)
1+ a 1z + a 2z + a 3z + a 4z

4th order series type:

H (z) = b (1 + BllZ-1+ B12z~2)(1 + B2lZ~1+ B22z-2)

K 0 (1 + A11z-1+ 4 2z“2)(1 + A21z-1+ A22z~2)

(6)
4th order parallel type:

H (z) = C0 + B'° + B" z T + Bz0 + 18212 -

1+ A11z 1+ A12z 2 1+ A21z 1+ A22z 2

(7)
Fig. 4 Parallel type 4th order IIR filter
Since the direct type IIR filters have two different
types of cascaded modes, the system functions The direct type II filter combines the serial branches

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 2019 14th IEEE International Conference on Electronic Measurement & Instruments ICEMI’2019

of the direct type I filter, while the former's delay unit obtains the time domain, frequency domain and
saves half, so the storage space can be saved when amplitude-frequency response, which are shown in Fig. 7
implemented with the resources of FPGA. Both the to Fig. 9, respectively.
cascading type and the parallel type are implemented by a
second-order section filter, and the delay unit is the same,
and can also be optimized by using FPGA resources. [9]
B. Filter implementation
The design of this system is implemented by
graphical simulation in MATLAB and filter waveform
simulation in Quartus II using Verilog language. [10]
In MATLAB, multiple second-order nodal filters are
designed by using Buffer function, which are cascaded to
form a 4th-order IIR low-pass filter. The passband cutoff
frequency is 1KHz, and the input signal is 1KHz+3KHz
sine wave. It is expected to pass the 4th order IIR. After Fig. 7 Time domain diagram before and after IIR filter
the filter, the output waveform is a 1KHz sine wave, and filtering
the specific parameter settings of the filter are shown in
Fig. 5.
FS =44100; ^Sample ra te Frequncy
fc = 1000; Mkhz
fe = 3000; ^e x te rn a l input 3khz
H = 1024 Asampling
Q = 16 Aquant i f ica t ion
Fig. 5 Parameters of IIR filter design in MATLAB
In the Quartus II software, the design of the IIR filter
is implemented by Verilog. Both the input excitation
signal and the output excitation signal adopt a signed
number of 32-bit signed type. [11] The filter parameters are
shown in Fig. 6.
it i me s c a l e lp s / lp s Fig. 8 Frequency domain diagram before and after IIR filter
m o d u le i i r ( filtering
in p u t , me I k ,
in p u t re s e t_ n ?
in p u t s ig n e d [ 3 1 : 0 ] p c m ._ in ,
o u tp u t s ig n e d [3 1 :0 ] pcm _out
) :

Fig. 6 Parameters of IIR filter design in Verilog

IV. EXPERIMENTAL RESULTS

AND ANALYSIS
A. Simulation Results and Analysis in MATLAB
By calling the existing library function in MATLAB,
the coefficients of the 4th-order IIR filter are quantized [12],
and the IIR low-pass filter is used to filter out the 3KHz
sinusoidal signal. The system of 4th-order IIR filter
Fig. 9 Amplitude-frequency response of IIR filter

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 2019 14th IEEE International Conference on Electronic Measurement & Instruments ICEMI’2019

As shown in Fig. 7, the input signal is a sine wave of waveform results are shown in Fig. 10 to Fig. 12,
1KHz+3KHz. After the IIR filter, the waveform is respectively.
distorted during 0~0.005s, and the 1KHz sine wave signal
is perfectly extracted. [13] In Fig. 8, after inputting the
3KHz sinusoidal noise signal through the IIR filter, it is
probably weakened by about 25db; similarly, in Fig. 9, it
can be seen from the amplitude-frequency response that
the position of 3KHz is probably weakened by 25db.
B. Hardware Waveform Results and Analysis in
Modelsim
In the Quartus II software, the hardware is
programmed according to the successfully simulated IIR
filter coefficients in MATLAB. The hardware simulation
of the IIR filter is simulated in Modelsim. [14] The Fig. 10 Sampling signal

Fig. 11 Input 1KHz sinusoidal signal

Fig. 12 Signal change of the IIR filter

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 2019 14th IEEE International Conference on Electronic Measurement & Instruments ICEMI’2019

In order to test the FPGA to achieve the filtering Yunnan Major Science and Technology Special
effect of the 4th-order IIR filter, this paper uses the Foundation of China under Grant No. 2018ZF017.
sampling rate of 44.1Kz, inputs 1KHZ sinusoidal signal
and mixes 3KHz sinusoidal signal as the noise of the input
REFERENCES
signal. After filtering by the 4th-order IIR filter designed [1] CHEN X L ,X IN X N,HUANG X.Design and FPGA

by FPGA, a cleaner 1KHz sinusoidal signal is available. Implementation o f IIR Digital Filter[J]. Microprocessor, 2018,

The simulation waveforms of the sampling rate clock, 39(01): 43-47.

input signal, and output signal in the Modelism software [2] L I X H ,M A W.Design and Implementation o f IIR D igital Filter

are shown in Fig. 10 to Fig. 12, respectively. It can be Based on FPGA[J]. Electronic Technology, 2016, 45(05): 58-60.

seen from Fig. 12 that the signal filtered by the 4th-order [3] HUANG Y J,HUANG Y Q.Design and FPGA Implementation o f

IIR filter is the same as the output signal waveform Cascaded IIR Filter Based on Matlab[J]. Journal o f Chuzhou

obtained by the MATLAB graphical simulation, University, 2018, 28(06): 26-32.

indicating that the 4th-order IIR filter realizes the function [4] HUANG B.Design and Implementation o f IIR Digital Filter in

of the LPF and passes the MATLAB graphical result. M A T LA B [J]. Western Radio and Television, 2018(21): 193-194.

Simulation test with Modelism hardware circuit. [15] [5] ZH AN G W T,ZHANG P Y,ZH AO P.Lab V IE W Auxiliary

Design Digital Filter and FPGA Implementation^]. Equipment

V. CONCLUSION AND FUTURE Manufacturing Technology, 2018(02): 4-7.

W ORK [6] ZH AN G H R.Design and Implementation o f IIR Digital

Filter[J].Journal o f Guizhou Teachers College,2016,32(12):8-11.

Taking the FPGA as the carrier and the design of the
[7] W A N G M Y. Design o f IIR digital filte r based on FPGA [D].
fourth-order IIR digital low-pass filter as an example, this
Southeast University, 2016.
paper proposes a method to quickly design a high-speed
[8] LE I Y. FPGA-based adaptive filte r design [D]. Taiyuan
4th-order IIR low-pass filter, and theoretically test the
University o f Technology, 2016.
designed filter, optimization and stability analysis. Firstly,
[9] CAO Y. Design and Implementation o f High Speed FIR Digital
the transfer function and constant coefficient of the filter
Filter and Multi-rate Filter Based on FPGA[D]. Guangxi Normal
are obtained by using MATLAB to call the library
University, 2016.
function. Then, the transfer function coefficient is
[10] X U H. Parametric design and efficient implementation o f digital
quantized by the rounding method to make full use of the
filte r [D]. Zhejiang University o f Technology, 2016.
high-speed performance of the FPGA. Finally, the
[11] X IA O Y J.Rapid Implementation o f FPGA for IIR Digital
Verilog hardware description language is used to realize
Filter[J]. Journal o f Changzhou Institute o f Technology, 2015,
the low IIR number. Pass filter. The simulation results in
28(04): 21-24.
MATLAB and Modelsim show that the design method is
[12] ZH AN G Q.Design and Implementation o f SRRC Digital Filter
fast and efficient, and the fourth-order IIR filter can be
Based on FPGA[J]. Electronic Technology,
applied to high-speed applications. In the later research,
2015,44(04):78-84+77.
FPGA resource optimization can be optimized on
[13] GUO Y Q, Q IN Y.Design and Implementation o f IIR Digital
higher-order IIR filter design, and strive to use the
Filter[J].Software Guide,2015,14(04):84-86.
minimum resource ratio and clock cycle to achieve
[14] L IU X ,W A N G SH K ,L I G L.Iron-based IIR digital filter
high-efficiency, low-cost high-order IIR filter design, and
implementation and its quantized word length effect
further The FPGA implementation of high-order IIR
analysis[J].Electronic Design Engineering,2014,22(15):23-26.
digital filters is applied to project practice.
[15] DONG X. Design o f IIR digital filte r based on FPGA [D].

Heilongjiang University, 2014.

ACKNOWLEDGMENT
Author Biographies
This work is supported partly by National Natural
Science Foundation of China under Grant No. 61261008, Zhang Qiang was born in Guangan, Sichuan, China in 1993.

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 2019 14th IEEE International Conference on Electronic Measurement & Instruments ICEMI’2019

He holds a master's degree in communication and information University, and a master's tutor. His research direction is signal
systems from the School o f Information, Yunnan University. and information processing.
His research interests include embedded system design and Yao Ruping was born in Luzhou, Sichuan, China in 1995.
FPGA accelerated deep learning. She is a graduate student in electronics and communication
Sun Jing was born in Kunming, Yunnan, China in 1964. engineering at the School o f Information, Yunnan University.
She is associate professor o f the School o f Information, Yunnan Her research direction is biomedical signal processing.
University, master's tutor, research direction for digital T V and Chen Cheng was born in Meishan, Sichuan, China in 1995.
circuit integration. She is a graduate student in electronics and communication
Wang Weilian was born in Kunming, Yunnan, China in engineering at the School o f Information, Yunnan University.
1948. He is a professor at the School o f Information, Yunnan Her research direction is biomedical signal processing.

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