Chapter 3

Mano’s Basic Computer

 REVIEW
• We introduced registers
• We discussed the kinds of Transfer, Arithmetic,
Logic and Shift Microoperations
• We discussed general aspects of CPU, Memory
and Bus architectures

• In this chapter we introduce a more

complicated basic computer and show how its
operation can be specified with register
transfer statements
 CONSIDERING THE NEXT PROBLEM IN DESIGN

A computer organization involves combining

everything we have learned to date into a single
integrated unit
What is a computer?

Von Neuman refers to a computer as a “stored

program digital computer”
What is a program?
 What is an instruction?
 How are instructions executed?
 GOALS
We conclude our lecture series by considering
computer organization
Combining the CPU, Memory and Bus architectures

We introduce the concept of an instruction

Instruction design and architecture
Microoperation sequencing (timing, control)
Roles of different registers

We will follow a model of a virtual/logical

computer organization adapted from M. Mano
(Computer System Architecture, 3d Edition)
 COMPUTER – HIGH LEVEL VIEW

CPU, Memory and Bus architectures with interface to I/O.

Data Bus
Volatile Memory (RAM) Input Output
M[0]
I/O Bus
M[1] CPU
Control Unit (CU)
CLK
Control
Bus

M[K] Arithmetic and Logic

Unit
(ALU)

M[L-1]
Address Bus
 MANO’S COMPUTER SPECIFICATION

 Mano has a Memory (RAM) of

4096 words. RAM
0
 This requires an Address bus of
12 bits.
 Each word is 16 bits long.
 The Data bus carries exactly 1
word of data between Memory
and CPU. 15 0 4095
 It has 8 registers.
 Input and Output is defined
using the ASCII code of length 8
bits.
 Instruction is stored in one 16-bit memory word,
 It consists 4 bits for the operation code (abbreviated
opcode) to specify one out of 16 possible operations, and 12
bits to specify the address of an operand (data used).
 The control reads a 16-bit instruction from the program
portion of memory. It then executes the operation specified
by the operation code.
 Computers that have a single-processor register usually
assign to it the name Accumulator and label it AC.
FETCH – DECODE – EXECUTE CYCLE
 THE MANO MODEL OF THE CPU REGISTERS
CPU registers used in the model (Mano), categorized by
length:
 PC :: Program counter (hold address of next inst. – 12 bits)
 AR :: Address register (holds address for memory– 12 bits)
 DR :: Data register (holds memory operand– 16 bits)
 AC :: Accumulator (processor register holds data – 16 bits)
 IR :: Instruction register (holds instruction code – 16 bits)
 TR :: Temporary register (holds temporary data – 16 bits)
 INR :: Input buffer register (holds input ASCII data – 8 bits)
 OUTR :: Output buffer register (holds output ASCII data – 8
bits)
 SCR :: Sequence counter register (4 bits)
 E, R :: Single bit flip-flops (flag/utility, interrupt)
BASIC COMPUTER REGISTERS AND MEMORY
11 0
PC

11 0 Memory
4096 words
AR 16 bits per
word
15 0
IR

15 0
15 0
DR
TR

7 0 7 0 15 0
OUT
OUT INPR
AC
RR
 STORED PROGRAMS
 A stored program is a set of instructions and data
expressed in binary language, stored in non-volatile
(ie. disk storage) memory

Programs can be executed only from Memory.

Thus, a program must be loaded from disk to RAM in order
to execute it.
Loaded programs are called processes.
Individual instructions must be transferred to the CPU where
they are executed, using data that must be obtained from
either CPU registers or RAM

 A process is executed by executing each individual

instruction that, collectively, fulfill the intentions of
the programmer.
 COMPUTER INSTRUCTION
o A computer instruction is a binary code that specifies
a sequence of microoperations for the computer.
o Instruction codes together with data are stored in
memory (RAM).
o The computer reads each instruction from memory and
places it in a control register.
o The control then interprets the binary code of the
instruction and proceeds to execute it by issuing a
sequence of microoperations.
o Operations such as: add, subtract, multiply, shift, and
complement.
o The number of bits required for the operation code of an
instruction depends on the total number of operations
available in the computer.
 RELATIONSHIP BETWEEN A COMPUTER
OPERATION AND A MICROOPERATION
o An operation is part of an instruction stored in
computer memory. It is a binary code that tells the
computer to perform a specific operation.
o For every operation code, the control issues a sequence
of microoperations needed for the hardware
implementation of the specified operation.
o An instruction code must specify not only the operation
but also the registers (by binary code) or the memory
words (by address) where the operands are to be found,
as well as the register or memory word where the result
is to be stored.
 INSTRUCTION ARCHITECTURE
The list of all instructions engineered for a computer’s CPU
is called the instruction set.
To distinguish each instruction, they are assigned a unique
numeric code
Can be done in many ways
Does not need to be ordinal (ie. starting from 0 and running
contiguously)
Can be partially ordinal and partially hierarchical
 Mano’s approach
Instructions must be capable of referencing Memory
and/or CPU addresses in order to cause data to be
transferred and operated on.
 INSTRUCTION FORMAT
Instructions usually consist of:
 Operation code (opcode) part
 Address part
 Addressing Mode part
Direct addressing – data found at the specified address
Indirect addressing – data found at the address found at the
specified address (pointer concept)
The number of memory referenced operands varies from
computer to computer.
0 Mano simplifies the instruction architecture to permit zero or
1 one memory address field. In the case of Indirect addressing
mode there are two memory accesses, but only one
reference.
15 14 12 11 0

IR
Mode I OpCode Address
bit
 MANO’S INSTRUCTION FORMAT

• In Mano’s Computer, since the memory contains

4096 (= 212) words, we needs 12 bit to specify
which memory address this instruction will use
• Bit 15 of the instruction specifies the addressing
mode (0: direct addressing, 1: indirect addressing)
• 3 bits for the instruction’s opcode (possible 8
operations)
MANO’S COMPUTER INSTRUCTION FORMAT
 INSTRUCTION HIERARCHY
Mano’s instruction set consists of 25 instructions:

Instruction

OpCode (000-110) OpCode (111)

Direct (I=0) Indirect (I=1) Direct (I=0) Indirect (I=1)

4 bit code 4 bit code 16 bit code 16 bit code
0 AND 8 AND 7800 CLA F800 INP
1 ADD 9 ADD 7400 CLE F400 OUT
2 LDA A LDA 7200 CMA F200 SKI
3 STA B STA 7100 CME F100 SKO
4 BUN C BUN 7080 CIR F080 ION
5 BSA D BSA 7040 CIL F040 IOF
6 ISZ E ISZ 7020 INC
7010 SPA
7008 SNA 6
7 7004 SZA
7002 SZE 12
7001 HLT
 INSTRUCTION SET COMPLETENESS
Selection of instructions should span a variety of
applications suitable to support programming

Arithmetic, logical and shift instructions

Instructions for moving data to and from memory and CPU

registers

Program control instructions, instructions that check status

conditions

Input and Output instructions

 Instructions

INSTRUCTION SET COMPLETENESS

Set of instructions using which user can construct machine language
programs to evaluate any computable function.

• Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA (other than ADD/AND?)
Transfer Instructions
- Data transfers between the main memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT
 INSTRUCTION CYCLE

 In Computer, a machine instruction is executed in the

following cycle:
1. Fetch an instruction from memory
2. Decode the instruction and calculate effective address (EA)
3. Read the EA from memory if the instruction has an indirect
address (Fetch operand)
4. Execute the instruction

 Upon the completion of step 4, the control goes back to step

1 to fetch, decode, and execute the next instruction.
 This process continues indefinitely unless a HALT instruction
is encountered.
 FETCH AND DECODE CYCLE

Microoperations for the fetch and decode phases can be

specified by the following register transfer statements:

T0: ARPC Fetch from memory the current instruction

T1: IRM[AR] ; PCPC+1

(which address is in PC)

T3 : D0 ,…,D7 Decode IR(12-14) ,ARIR(0-11)

,IIR(15)
Decode instruction found now in IR
 DETERMINE THE TYPE OF INSTRUCTION
 We use bits 12 , 13, 14 as input to the decoder to
determine the type of instruction
 Only one of the decoder outputs = 1 at certain
combination (i.e. operation) of the inputs.
DIFFERENCE BETWEEN DIRECT AND INDIRECT
ADDRESSING
Direct addressing Indirect addressing

22 0 ADD 457 35 1 ADD 300

300 1350
457 Operand
1350 Operand

+ +
AC AC
 1. MEMORY-REFERENCE INSTRUCTIONS:

Symbol Operation Symbolic description

Decoder
AND D0 AC AC ^M[AR]
ADD D1 ACAC + M[AR] , E COUT
LDA (load to D2 AC M[AR]
accumulator)
STA (Store from D3 M[AR]  AC
accumulator)
BUN (branch D4 PC  AR
unconsitionally)
BSA D5 M[AR]  PC , PCAR+1
ISZ D6 M[AR]  M[AR]+1,
 D0: AND: AND TO AC

 This is an instruction that performs the AND logic

operation on pairs of bits in AC and the memory
word specified by the effective address found in
(AR) now.
 We can not work on the memory location directly,
we have to bring the data to DR (Data Register)
first.
 The result of the operation is transferred to AC.
 The microoperations that execute this instruction
are:

D0T4: DR M[AR]

D0T5: AC AC ^DR, SC 0

 D1: ADD: ADD TO AC

 This instruction adds the content of the memory

word specified by the effective address found in
(AR) now to the value of AC.
 We can not work on the memory location directly,
we have to bring the data to DR (Data Register)
first.
 The result of the operation is transferred to AC.
 The microoperations that execute this instruction
are:
D1T4: DR M[AR]

D1T5: AC AC +DR, ECout,

SC 0
 D2: LDA: LOAD TO AC

 This instruction transfers the memory word

specified by the effective address found in (AR)
now to AC.
 We can not work on the memory location directly,
we have to bring the data to DR (Data Register)
first.
 The microoperations that execute this instruction
are:
D2T4: DR M[AR]

D2T5: AC DR, SC 0

 D3: STA: STORE AC

 This instruction stores the content of AC into the

memory word specified by the effective address
found in (AR) now.

 The microoperation that execute this instruction

is:
D3T4: M[AR]  AC , SC 0
 D4: BUN: BRANCH UNCONDITIONALLY

 This instruction transfers the program to the

instruction specified by the effective address found in
(AR) now.
 The BUN instruction allows the programmer to specify
an instruction out of sequence and we say that the
program branches (or jumps) unconditionally.
 The effective address from AR is transferred through
the common bus to PC.
 The microoperation that execute this instruction is:
D4T4: PC AR , SC 0
 D5: BSA: BRANCH AND SAVE RETURN ADDRESS

 This instruction is useful for branching to a portion of

the program called a subroutine or procedure.
 When executed, the BSA instruction stores the
address of the next instruction in sequence (which is
available in PC) into a memory location specified by
the effective address found in (AR) now.
 The effective address plus one is then transferred to
PC to serve as the address of the first instruction in
the subroutine.
 The microoperation that execute this instruction is:
D4T4: M[AR] PC , AR  AR + 1 ,
D5T4: PC AR, SC 0
EXAMPLE ON BSA
 The BSA instruction is assumed to be in
memory at address 20
 The I bit is 0 and the address part of the
instruction has the binary equivalent of
135.
 After the fetch and decode phases, PC
contains 21, which is the address of the
next instruction in the program (referred
to as the return address).
 AR holds the effective address 135.
 The BSA instruction performs the
following numerical operation:
M[135]  21 , PC135 + 1 = 136
A) Memory, Pc and AR B) memory, PC and
at time T4 AR after execution

Figure 3.8 Example of BSA instruction execution.

 D6: ISZ: INCREMENT AND SKIP IF ZERO

 This instruction increments the word specified by the

effective address found in (AR) now, and if the
incremented value is equal to 0, PC is incremented by
1.
 The programmer usually stores a negative number (in
2’s complement) in the memory word (AR).
 As this negative number is repeatedly incremented by
one, it eventually reaches the value of zero.
 At that time PC is incremented by one in order to skip
the next instruction in the program.
 Since it is not possible to increment a word inside the
memory, it is necessary to read the word into DR,
increment DR, and store the word back into memory.
 The microoperations that execute this
instruction are:
D6T4: DR M[AR]

D6T5: DRDR+1

D6T6: M[AR] DR, if(DR= 0) then

(PCPC + 1), SC 0
 REGISTER REFERENCE INSTRUCTIONS
12 INSTRUCTIONS, STARTS WITH 0111
Hex Mnemonic Binary coding Meaning
7800 CLA 0111100000000000 CLear Accumulator
7400 CLE 0111010000000000 CLear E
7200 CMA 0111001000000000 CoMplement Accumulator
7100 CME 0111000100000000 CoMplement E
7080 CIR 0111000010000000 CIrcular shift Right
7040 CIL 0111000001000000 CIrcular shift Left

7020 INC 0111000000100000 INCrement AC

7010 SPA 0111000000010000 Skip if Positive Accumulator

7008 SNA 0111000000001000 Skip if Negative Accumulator
7004 SZA 0111000000000100 Skip if Zero Accumulator
7002 SZE 0111000000000010 Skip if Zero E

7001 HLT 0111000000000001 HaLT the computer

 REGISTER REFERENCE INSTRUCTIONS
 Within this instruction subset, we group the
instructions by which register is affected
Hex Mnemonic
7800 CLA
7200 CMA
7080 CIR AC affected
7040 CIL 8 instructions
7020 INC
7010 SPA
7008 SNA
7004 SZA

7400 CLE E affected

7100 CME 3 instructions
7002 SZE

7001 HLT Control affected

 REGISTER REFERENCE INSTRUCTIONS
Clear, Complement or Increment : AC register.

CLA
Hex Mnemonic RTL CMA
7800 CLA AC = 0 INC
AC
7200 CMA AC = ~ AC
7020 INC AC = AC + 1

Clear, Complement : E register

CLE
Hex Mnemonic RTL CME

7400 CLE E = 0 E
7100 CME E = ~ E
 REGISTER REFERENCE INSTRUCTIONS
Shift AC register.
This is a circular shift that is performed using the E register
Control over timing ensures all operations operate in parallel
 Eg. Use master-slave flip-flops in registers

Hex Mnemonic RTL

7080 CIR AC(0-14) = AC(1-15),
AC(15) = E, E = AC(0)

7040 CIL AC(1-15) = AC(0-14),

AC(0) = E, E = AC(15)

AC
 REGISTER REFERENCE INSTRUCTIONS
Skip on <condition> : AC register.
 Tests sign/value status of 2’s complement integer in AC
 If status matches query, advance PC by one instruction word

Hex Mnemonic RTL

7010 SPA ( AC > 0 ) : PC = PC + 1
7008 SNA ( AC < 0 ) : PC = PC + 1
7004 SZA ( AC = 0 ) : PC = PC + 1

Skip on Zero condition : E register

 Test status of E bit. If not zero, proceed to the next instruction.
 If zero, advance PC by one instruction word (recall that it has already
been incremented by one, so this causes skipping the next instruction
in contiguous sequence.

Hex Mnemonic RTL

7002 SZE ~ E : PC = PC + 1
 REGISTER REFERENCE INSTRUCTIONS
Halting the computer
 Disable all circuits (over-ride all specific Enable controls with a general
Disable).

Hex Mnemonic RTL

7001 HLT Disable all circuits
We have D7I/T3 = r (common to all register-reference instructions)
We have only one bit IR(i) = Bi [bit in IR(0—11) that specifies
operation]

r: SC 0 Clear SC

CLA rB11: AC 0 Clear AC

CLE rB10: E  0 Clear E
CMA rB9: AC AC Complement AC
CME rB8: E E Complement E
CIR rB7: AC shr AC, AC(15)  E, E AC(0) Circulate right
CIL rB6: AC shl AC, AC(0) E, EAC(15) Circulate left
INC rB5: AC AC + 1 Increment AC
SPA rB4: If (AC(15) = 0) then (PCPC+ 1) Skip if positive
SNA rB3: If (AC(15) = 1) then (PCPC + 1) Skip if negative
SZA rB2: If (AC = 0) then (PC PC + 1) Skip if AC zero
SZE rB1: If(E = 0) then (PCPC + 1) Skip if E zero
INPUT, OUTPUT AND INTERRUPT INSTRUCTIONS
15 14 12 11 0

IR 1 1 1 1 I/O operation control bits

 INPUT/OUTPUT INSTRUCTIONS
Each peripheral device has a communications and control
interface that interacts with the computer’s interface logic
circuits
 Input
 Need a data buffer (INPR) and a flag (FGI) indicating buffer empty/full
 Output
 Need a data buffer (OUTR) and a flag (FGO) indicating buffer empty/full

FGO
Status
Printer Receiver
Interface OUTR Data

NOTE:
AC(H) AC(L) Only the low order part
of AC is used.

Keyboard Transmitter INPR Data

Interface
Status
FGI
PERIPHERAL DEVICES CPU
THE PROCESS OF INPUT INFORMATION
TRANSFER IS AS FOLLOWS:
1. Initially, the input flag FGI is cleared to 0.
2. When a key is struck in the keyboard, an 8-bit
alphanumeric code is shifted into INPR and the input
flag FGI is set to 1. As long as the flag is set, the
information in INPR cannot be changed by striking
another key.
3. The computer checks the flag bit; if it is 1, the
information from INPR is transferred in parallel into
the eight low-order bits of AC and FGI is cleared to
0.
4. Once the flag is cleared, new information can be
shifted into INPR by striking another key.

 The output register OUTR works similarly but the

direction of information flow is reversed.
THE PROCESS OF OUTPUT INFORMATION
TRANSFER IS AS FOLLOWS:

1. Initially, the output flag FGO is set to 1.

2. The computer checks the flag bit; if it is 1, the
information in the eight least significant bits
from AC is transferred in parallel to OUTR and
FGO is cleared to 0.
3. The output device accepts the coded
information, prints the corresponding character,
and when the operation is completed, it sets
FGO to 1.

The computer does not load a new character into

QUTR when FGQ is 0 because this condition
indicates that the output device is in the process of
printing the character.
 INPUT/OUTPUT INSTRUCTIONS
Used for communicating data between CPU and I/O
peripheral devices
Also, need instructions to support programmed polling.
 Polling refers to waiting for a condition to be true before proceeding

16 bit
OpCode Mnemonic Meaning
F800 INP Input ASCII char
F400 OUT Output ASCII char
F200 SKI Skip if input flag (FGI=1)
F100 SKO Skip if output flag (FGO=1)

F 8
4
2
1
15 14 12 11 0

IR 1 1 1 1 I/O operation control bits

 INPUT-OUTPUT INSTRUCTIONS
INSTRUCTIONS STARTS WITH 0111

D7IT3 = p (common to all input—output instructions)

IR(i) = Bi [bit in IR(6—11) that specifies the instruction]

p: SC 0 Clear SC
INP pB11: AC(0-7) INPR, FGI0 Input character
OUT PB10:OUTRAC(0-7),FGO 0 Output character

SKI PB9: If(FGI=1)then(PCPC+1) Skip on input flag

SKO PB8: If(FGO=1)then(PCPC+1) Skip on Output flag

ION PB7: IEN1 Interrupt enable on

IOF PB7 : IEN 0 Interrupt enable off
 INTERRUPTS
Input and Output interactions with electromechanical peripheral
devices require huge processing times compared with CPU
processing times
 I/O (milliseconds) versus CPU (nano/micro-seconds)
Interrupts permit other CPU instructions to execute while waiting
for I/O to complete
 Need an additional 1-bit IEN flip-flop to store the interrupt status (0/1)

16 bit
OpCode Mnemonic Meaning
F080 ION Interrupt Enabled (IEN  1)
F040 IOF Interrupt Disabled (IEN  0) IEN

15 14 12 11 0

IR 1 1 1 1 I/O operation control bits

INPUT- OUTPUT AND PROGRAM INTERRUPT
 INTERRUPTS
In this approach, interrupts are used only with I/O handling
 In addition to a flip-flop to store the Interrupt Enable state, one more flip-
flop (R) is needed to store the I/O Status (Ready/Not_ready).
 In general, interrupts may be used with arbitrary instructions for
exception trapping and handling

1-bit registers
We will also
require one final =0
IEN IEN
register, called All of these
TR (for transfer). =1 flipflops are
This can be 16 assumed to be
=1
bits, but must be FGI FGI
reset to 0 when
at least 12 bits.
=0 bootstrapping
the computer.
=1
FG0 FGO

=0
R1 R
Control Bus
 INTERRUPT HANDLING FLOWCHART

Instruction Cycle =0 =1 Interrupt Cycle

R

Fetch/Decode Instruction Store return address

in location 0
M[0]  PC IEN
Execute =0
IEN
Instruction
=1
FGI
=1 Branch to location 1
FGI PC  1

=0 FGO
=1 Reset Interrupt, Ready
FG0
IEN  0 R
=0 R0
R1
TR
Control Bus
 INTERRUPT HANDLING FLOWCHART

R : AR  0 , TR  PC \\ NOTE TRANSFER REG.

T0 Memory Memory
R T1 : M[AR]  TR , PC  =1
0 R 0 0 256
R T2 : PC  PC + 1 , IEN  0 , R Interrupt
 0 , Cycle
SC  0
1 0 BUN 1120 PC=1 0 BUN 1120

Store return address

Main Prog. in location 0 Main Prog.
M[0]  PC
Curr Instr. Curr Instr.
Next Instr. Next Instr.
255 255
PC=256 256
Branch to location 1
PC  1

1120 I/O Program 1120 I/O Program

Reset Interrupt, Ready
1 BUN 0 IEN  0 1 BUN 0
R0

(a) BEFORE (b) AFTER

Interrupt Interrupt
MULTIPLE INTERRUPTS
CONTROL LOGIC GATES
 CONTROL OF REGISTERS: (AC)
• Suppose that we want to derive the gate structure
associated with the control inputs of AR. We scan Table 5-
6 to find all the statements that change the content of AR:
R’T0: AR PC
R’T2: .AR IR(0—11)
D'7IT3: ARM[AR]
RT0: AR 0
D5T4: ARAR+1

• The control functions can be combined into three Boolean

expressions as follows:
LD (AR) = R’T0 + R’T2 + D'7IT3 / the load input of AR
CLR (AR) = RT0 / the clear input of AR
INR(AR) = D5T4 / the increment input of AR