Unit 3

Decoder
A decoder that has two inputs, an enable pin and four outputs is implemented in a
CPLD
using VHDL in this part of the VHDL course.
This 2x4 decoder will switch on one of the four active low outputs, depending on
the
binary value of the two inputs and if the enable input
is high.

VHDL
Behavioural

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_2x4_behavioral is
Port ( A : in STD_LOGIC_VECTOR (1 downto 0); -- 2-bit input
Y : out STD_LOGIC_VECTOR (3 downto 0)); -- 4-bit outp
end decoder_2x4_behavioral;

architecture Behavioral of decoder_2x4_behavioral is

begin
process(A)
begin
case A is
when "00" => Y <= "0001";
when "01" => Y <= "0010";

Unit 3 1
 when "10" => Y <= "0100";
when "11" => Y <= "1000";
when others => Y <= "0000";
end case;
end process;
end Behavioral;

Dataflow

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_2x4_dataflow is
Port ( A : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end decoder_2x4_dataflow;

architecture Dataflow of decoder_2x4_dataflow is

begin
Y(0) <= not A(1) and not A(0);
Y(1) <= not A(1) and A(0);
Y(2) <= A(1) and not A(0);
Y(3) <= A(1) and A(0);
end Dataflow;

Strcutural

Unit 3 2
 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_2x4_structural is
Port ( A : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end decoder_2x4_structural;

architecture Structural of decoder_2x4_structural is

signal notA0, notA1 : STD_LOGIC;
begin
-- NOT gates
notA0 <= not A(0);
notA1 <= not A(1);

-- AND gates to form the outputs

Y(0) <= notA1 and notA0;
Y(1) <= notA1 and A(0);
Y(2) <= A(1) and notA0;
Y(3) <= A(1) and A(0);
end Structural;

Verilog

module decoder_2x4_behavioral (
input [1:0] A, // 2-bit input
output reg [3:0] Y // 4-bit output
);

always @(A) begin

case (A)

Unit 3 3
 2'b00: Y = 4'b0001;
2'b01: Y = 4'b0010;
2'b10: Y = 4'b0100;
2'b11: Y = 4'b1000;
default: Y = 4'b0000;
endcase
end

endmodule

module decoder_2x4_dataflow (
input [1:0] A,
output [3:0] Y
);

assign Y[0] = ~A[1] & ~A[0];

assign Y[1] = ~A[1] & A[0];
assign Y[2] = A[1] & ~A[0];
assign Y[3] = A[1] & A[0];

endmodule

module decoder_2x4_structural (
input [1:0] A,
output [3:0] Y
);

wire notA0, notA1;

// NOT gates
not (notA0, A[0]);
not (notA1, A[1]);

Unit 3 4
 // AND gates for each output
and (Y[0], notA1, notA0);
and (Y[1], notA1, A[0]);
and (Y[2], A[1], notA0);
and (Y[3], A[1], A[0]);

endmodule

Encoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity encoder_4to2 is
Port (
I : in STD_LOGIC_VECTOR(3 downto 0); -- 4-bit input
Y : out STD_LOGIC_VECTOR(1 downto 0) -- 2-bit output
);
end encoder_4to2;

architecture Behavioral of encoder_4to2 is

begin
process(I)
begin
case I is
when "1000" => Y <= "11"; -- Input I3 is 1, outputs
when "0100" => Y <= "10"; -- Input I2 is 1, outputs
when "0010" => Y <= "01"; -- Input I1 is 1, outputs

Unit 3 5
 when "0001" => Y <= "00"; -- Input I0 is 1, outputs
when others => Y <= "00"; -- Default case
end case;
end process;
end Behavioral;

module encoder_4to2 (
input wire [3:0] I, // 4-bit input
output reg [1:0] Y // 2-bit output
);

always @(*) begin

case (I)
4'b1000: Y = 2'b11; // I3 is high, output Y = 11
4'b0100: Y = 2'b10; // I2 is high, output Y = 10
4'b0010: Y = 2'b01; // I1 is high, output Y = 01
4'b0001: Y = 2'b00; // I0 is high, output Y = 00
default: Y = 2'b00; // Default case
endcase
end

endmodule

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity encoder_4to2 is
Port (
I : in STD_LOGIC_VECTOR(3 downto 0); -- 4-bit input
Y : out STD_LOGIC_VECTOR(1 downto 0) -- 2-bit output
);
end encoder_4to2;

Unit 3 6
 architecture Dataflow of encoder_4to2 is
begin
Y(1) <= I(3) or I(2); -- Y1 is 1 if I3 or I2 is 1
Y(0) <= I(3) or (not I(2) and I(1)); -- Y0 is 1 if I3 or (I2
end Dataflow;

module encoder_4to2_dataflow (
input wire [3:0] I, // 4-bit input
output wire [1:0] Y // 2-bit output
);

assign Y[1] = I[3] | I[2]; // Y1 is 1 if I3 or I2 is 1

assign Y[0] = I[3] | (~I[2] & I[1]); // Y0 is 1 if I3 or (I2 is

endmodule

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity encoder_4to2 is
Port (
I : in STD_LOGIC_VECTOR(3 downto 0); -- 4-bit input
Y : out STD_LOGIC_VECTOR(1 downto 0) -- 2-bit output
);
end encoder_4to2;

architecture Structural of encoder_4to2 is

signal I3_or_I2 : STD_LOGIC;

Unit 3 7
 signal not_I2 : STD_LOGIC;
signal I2_and_I1 : STD_LOGIC;
begin
-- Intermediate signals for gate outputs
I3_or_I2 <= I(3) or I(2);
not_I2 <= not I(2);
I2_and_I1 <= not_I2 and I(1);

-- Outputs Y(1) and Y(0)

Y(1) <= I3_or_I2;
Y(0) <= I(3) or I2_and_I1;
end Structural;

module encoder_4to2_structural (
input wire [3:0] I, // 4-bit input
output wire [1:0] Y // 2-bit output
);

wire I3_or_I2;
wire not_I2;
wire I2_and_I1;

// Intermediate gate outputs

or (I3_or_I2, I[3], I[2]);
not (not_I2, I[2]);
and (I2_and_I1, not_I2, I[1]);

// Outputs Y[1] and Y[0]

assign Y[1] = I3_or_I2;
assign Y[0] = I[3] | I2_and_I1;

endmodule

Unit 3 8
 Mux 2x1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_2to1 is
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Sel : in STD_LOGIC;
Y : out STD_LOGIC
);
end mux_2to1;

architecture Behavioral of mux_2to1 is

begin
process (A, B, Sel)
begin
if Sel = '0' then
Y <= A;
else
Y <= B;
end if;
end process;
end Behavioral;

module mux_2to1 (
input wire A,
input wire B,
input wire Sel,
output reg Y

Unit 3 9
 );

always @(*) begin

if (Sel == 1'b0)
Y = A;
else
Y = B;
end

endmodule

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_2to1 is
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Sel : in STD_LOGIC;
Y : out STD_LOGIC
);
end mux_2to1;

architecture Dataflow of mux_2to1 is

begin
Y <= (A and not Sel) or (B and Sel);
end Dataflow;

Unit 3 10
 module mux_2to1 (
input wire A,
input wire B,
input wire Sel,
output wire Y
);

assign Y = (A & ~Sel) | (B & Sel);

endmodule

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_2to1 is
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Sel : in STD_LOGIC;
Y : out STD_LOGIC
);
end mux_2to1;

architecture Structural of mux_2to1 is

signal notSel : STD_LOGIC;
signal and1, and2 : STD_LOGIC;
begin
notSel <= not Sel;
and1 <= A and notSel;
and2 <= B and Sel;

Unit 3 11
 Y <= and1 or and2;
end Structural;

module mux_2to1 (
input wire A,
input wire B,
input wire Sel,
output wire Y
);

wire notSel, and1, and2;

not (notSel, Sel);

and (and1, A, notSel);
and (and2, B, Sel);
or (Y, and1, and2);

endmodule

Mux 4x1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_4to1 is
Port (
A : in STD_LOGIC_VECTOR(3 downto 0);
Sel : in STD_LOGIC_VECTOR(1 downto 0);

Unit 3 12
 Y : out STD_LOGIC
);
end mux_4to1;

architecture Behavioral of mux_4to1 is

begin
process (A, Sel)
begin
case Sel is
when "00" => Y <= A(0);
when "01" => Y <= A(1);
when "10" => Y <= A(2);
when "11" => Y <= A(3);
when others => Y <= '0';
end case;
end process;
end Behavioral;

module mux_4to1 (
input wire [3:0] A,
input wire [1:0] Sel,
output reg Y
);

always @(*) begin

case (Sel)
2'b00: Y = A[0];
2'b01: Y = A[1];
2'b10: Y = A[2];
2'b11: Y = A[3];
default: Y = 1'b0;
endcase
end

Unit 3 13
 endmodule

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_4to1 is
Port (
A : in STD_LOGIC_VECTOR(3 downto 0);
Sel : in STD_LOGIC_VECTOR(1 downto 0);
Y : out STD_LOGIC
);
end mux_4to1;

architecture Dataflow of mux_4to1 is

begin
Y <= (A(0) and not Sel(1) and not Sel(0)) or
(A(1) and not Sel(1) and Sel(0)) or
(A(2) and Sel(1) and not Sel(0)) or
(A(3) and Sel(1) and Sel(0));
end Dataflow;

module mux_4to1 (
input wire [3:0] A,
input wire [1:0] Sel,
output wire Y
);

assign Y = (A[0] & ~Sel[1] & ~Sel[0]) |

(A[1] & ~Sel[1] & Sel[0]) |
(A[2] & Sel[1] & ~Sel[0]) |
(A[3] & Sel[1] & Sel[0]);

Unit 3 14
 endmodule

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_4to1 is
Port (
A : in STD_LOGIC_VECTOR(3 downto 0);
Sel : in STD_LOGIC_VECTOR(1 downto 0);
Y : out STD_LOGIC
);
end mux_4to1;

architecture Structural of mux_4to1 is

signal notSel1, notSel0 : STD_LOGIC;
signal and0, and1, and2, and3 : STD_LOGIC;
begin
notSel1 <= not Sel(1);
notSel0 <= not Sel(0);

and0 <= A(0) and notSel1 and notSel0;

and1 <= A(1) and notSel1 and Sel(0);
and2 <= A(2) and Sel(1) and notSel0;
and3 <= A(3) and Sel(1) and Sel(0);

Y <= and0 or and1 or and2 or and3;

end Structural;

A 4-to-1 multiplexer (4x1 MUX) is a digital device that selects one of four input
signals and forwards it to a single output line based on a select signal. It
essentially acts as a data selector, routing one of multiple input lines to the output.

Unit 3 15
 The number of inputs to the multiplexer is \( 2^n \), where \( n \) is the number of
select lines.

How a 4x1 Multiplexer Works

A 4x1 multiplexer has:

4 input lines: typically labeled as \( I_0 \), \( I_1 \), \( I_2 \), and \( I_3 \).

2 select lines: labeled as \( S_1 \) and \( S_0 \).

1 output line: labeled as \( Y \).

The select lines control which of the inputs is connected to the output. In a 4-to-1
multiplexer:

When \( S_1S_0 = 00 \), the output \( Y = I_0 \)

When \( S_1S_0 = 01 \), the output \( Y = I_1 \)

When \( S_1S_0 = 10 \), the output \( Y = I_2 \)

When \( S_1S_0 = 11 \), the output \( Y = I_3 \)

The truth table for a 4x1 MUX is:

\( S_1 \) \( S_0 \) Output (Y)

0 0 \( I_0 \)

0 1 \( I_1 \)

1 0 \( I_2 \)

1 1 \( I_3 \)

Formula to Calculate the Number of Select Lines

To determine the number of select lines required for any multiplexer:

Let \( N \) be the number of inputs.

The number of select lines \( n \) is given by:

\[
n = \log_2(N)
\]

Unit 3 16
 For example:

For a 2-to-1 multiplexer (2 inputs), \( n = \log_2(2) = 1 \) select line.

For a 4-to-1 multiplexer (4 inputs), \( n = \log_2(4) = 2 \) select lines.

For an 8-to-1 multiplexer (8 inputs), \( n = \log_2(8) = 3 \) select lines.

For a 16-to-1 multiplexer (16 inputs), \( n = \log_2(16) = 4 \) select lines.

How to Make a Multiplexer in Digital Logic

1. Determine the number of inputs you need.

2. Calculate the number of select lines required based on the number of inputs
using \( n = \log_2(N) \).

3. Create the logic to route each input to the output based on the binary values
of the select lines.

For instance, for a 4x1 MUX:

Use 4 inputs, 2 select lines, and 1 output.

Use AND, OR, and NOT gates to design a circuit that implements the function
described in the truth table.

2 bit comparator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Comparator is
Port (
A : in STD_LOGIC_VECTOR (1 downto 0); -- 2-bit input A

Unit 3 17
 B : in STD_LOGIC_VECTOR (1 downto 0); -- 2-bit input B
A_gt_B : out STD_LOGIC; -- Output high if
A_eq_B : out STD_LOGIC; -- Output high if
A_lt_B : out STD_LOGIC -- Output high if
);
end Comparator;

architecture Behavioral of Comparator is

begin
process (A, B)
begin
if (A > B) then
A_gt_B <= '1';
A_eq_B <= '0';
A_lt_B <= '0';
elsif (A = B) then
A_gt_B <= '0';
A_eq_B <= '1';
A_lt_B <= '0';
else
A_gt_B <= '0';
A_eq_B <= '0';
A_lt_B <= '1';
end if;
end process;
end Behavioral;

module Comparator (
input [1:0] A, // 2-bit input A
input [1:0] B, // 2-bit input B
output reg A_gt_B, // Output high if A > B
output reg A_eq_B, // Output high if A = B
output reg A_lt_B // Output high if A < B
);

Unit 3 18
 always @ (A or B) begin
if (A > B) begin
A_gt_B = 1;
A_eq_B = 0;
A_lt_B = 0;
end
else if (A == B) begin
A_gt_B = 0;
A_eq_B = 1;
A_lt_B = 0;
end
else begin
A_gt_B = 0;
A_eq_B = 0;
A_lt_B = 1;
end
end

endmodule

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Comparator2Bit is
Port (
A : in STD_LOGIC_VECTOR(1 downto 0);
B : in STD_LOGIC_VECTOR(1 downto 0);
A_gt_B : out STD_LOGIC;
A_eq_B : out STD_LOGIC;
A_lt_B : out STD_LOGIC
);
end Comparator2Bit;

Unit 3 19
 architecture Dataflow of Comparator2Bit is
begin
-- A > B condition
A_gt_B <= (A(1) and not B(1)) or ((A(1) xnor B(1)) and (A(0)

-- A = B condition
A_eq_B <= (A(1) xnor B(1)) and (A(0) xnor B(0));

-- A < B condition
A_lt_B <= (not A(1) and B(1)) or ((A(1) xnor B(1)) and (not
end Dataflow;

module Comparator2Bit (
input [1:0] A,
input [1:0] B,
output A_gt_B,
output A_eq_B,
output A_lt_B
);

// A > B condition
assign A_gt_B = (A[1] & ~B[1]) | ((A[1] ~^ B[1]) & (A[0] & ~

// A = B condition
assign A_eq_B = (A[1] ~^ B[1]) & (A[0] ~^ B[0]);

// A < B condition
assign A_lt_B = (~A[1] & B[1]) | ((A[1] ~^ B[1]) & (~A[0] &

endmodule

Unit 3 20
 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Comparator2Bit is
Port (
A : in STD_LOGIC_VECTOR(1 downto 0);
B : in STD_LOGIC_VECTOR(1 downto 0);
A_gt_B : out STD_LOGIC;
A_eq_B : out STD_LOGIC;
A_lt_B : out STD_LOGIC
);
end Comparator2Bit;

architecture Structural of Comparator2Bit is

signal notA1, notA0, notB1, notB0 : STD_LOGIC;
signal A1_and_notB1, A0_and_notB0, notA1_and_B1 : STD_LOGIC;
signal A1_xnor_B1, A0_xnor_B0 : STD_LOGIC;

begin
-- NOT gates
notA1 <= not A(1);
notA0 <= not A(0);
notB1 <= not B(1);
notB0 <= not B(0);

-- XNOR gates for equality check

A1_xnor_B1 <= (A(1) xnor B(1));
A0_xnor_B0 <= (A(0) xnor B(0));

-- AND gates for specific conditions

A1_and_notB1 <= A(1) and notB1;
A0_and_notB0 <= A(0) and notB0;
notA1_and_B1 <= notA1 and B(1);

-- A > B condition

Unit 3 21
 A_gt_B <= A1_and_notB1 or (A1_xnor_B1 and A0_and_notB0);

-- A = B condition
A_eq_B <= A1_xnor_B1 and A0_xnor_B0;

-- A < B condition
A_lt_B <= notA1_and_B1 or (A1_xnor_B1 and notA0 and B(0));
end Structural;

module Comparator2Bit (
input [1:0] A,
input [1:0] B,
output A_gt_B,
output A_eq_B,
output A_lt_B
);

wire notA1, notA0, notB1, notB0;

wire A1_and_notB1, A0_and_notB0, notA1_and_B1;
wire A1_xnor_B1, A0_xnor_B0;

// NOT gates
not (notA1, A[1]);
not (notA0, A[0]);
not (notB1, B[1]);
not (notB0, B[0]);

// XNOR gates for equality check

xnor (A1_xnor_B1, A[1], B[1]);
xnor (A0_xnor_B0, A[0], B[0]);

// AND gates for specific conditions

and (A1_and_notB1, A[1], notB1);
and (A0_and_notB0, A[0], notB0);
and (notA1_and_B1, notA1, B[1]);

Unit 3 22
 // A > B condition
or (A_gt_B, A1_and_notB1, A1_xnor_B1 & A0_and_notB0);

// A = B condition
and (A_eq_B, A1_xnor_B1, A0_xnor_B0);

// A < B condition
or (A_lt_B, notA1_and_B1, A1_xnor_B1 & notA0 & B[0]);

endmodule

Half Adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Half_Adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Sum : out STD_LOGIC;
Carry : out STD_LOGIC);
end Half_Adder;

architecture Behavioral of Half_Adder is

Unit 3 23
 begin
process(A, B)
begin
Sum <= A XOR B;
Carry <= A AND B;
end process;
end Behavioral;

module Half_Adder(
input A,
input B,
output reg Sum,
output reg Carry
);

always @(*) begin

Sum = A ^ B;
Carry = A & B;
end

endmodule

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Half_Adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Sum : out STD_LOGIC;
Carry : out STD_LOGIC);
end Half_Adder;

Unit 3 24
 architecture Dataflow of Half_Adder is
begin
Sum <= A XOR B;
Carry <= A AND B;
end Dataflow;

module Half_Adder(
input A,
input B,
output Sum,
output Carry
);

assign Sum = A ^ B;
assign Carry = A & B;

endmodule

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Half_Adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Sum : out STD_LOGIC;
Carry : out STD_LOGIC);
end Half_Adder;

architecture Structural of Half_Adder is

component AND_GATE
Port ( X : in STD_LOGIC;

Unit 3 25
 Y : in STD_LOGIC;
Z : out STD_LOGIC);
end component;

component XOR_GATE
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
Z : out STD_LOGIC);
end component;

signal and_out : STD_LOGIC;

signal xor_out : STD_LOGIC;

begin

XOR1: XOR_GATE port map (A, B, xor_out);

AND1: AND_GATE port map (A, B, and_out);

Sum <= xor_out;

Carry <= and_out;

end Structural;

module Half_Adder(
input A,
input B,
output Sum,
output Carry
);

wire xor_out, and_out;

xor XOR1(xor_out, A, B);

and AND1(and_out, A, B);

Unit 3 26
 assign Sum = xor_out;
assign Carry = and_out;

endmodule

Full Adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Full_Adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC );
end Full_Adder;

architecture Behavioral of Full_Adder is

begin
Sum <= (A XOR B) XOR Cin;
Cout <= (A AND B) OR (Cin AND (A XOR B));
end Behavioral;

module Full_Adder (
input A,
input B,
input Cin,
output Sum,

Unit 3 27
 output Cout
);
assign Sum = A ^ B ^ Cin;
assign Cout = (A & B) | (Cin & (A ^ B));
endmodule

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Full_Adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC );
end Full_Adder;

architecture Dataflow of Full_Adder is

signal AB_XOR : STD_LOGIC;
begin
AB_XOR <= A XOR B;
Sum <= AB_XOR XOR Cin;
Cout <= (A AND B) OR (Cin AND AB_XOR);
end Dataflow;

module Full_Adder (
input A,
input B,
input Cin,
output Sum,

Unit 3 28
 output Cout
);
wire AB_XOR;

assign AB_XOR = A ^ B;
assign Sum = AB_XOR ^ Cin;
assign Cout = (A & B) | (Cin & AB_XOR);
endmodule

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Full_Adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC );
end Full_Adder;

architecture Structural of Full_Adder is

component Half_Adder
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
Sum : out STD_LOGIC;
Carry : out STD_LOGIC );
end component;

signal Sum1, Carry1, Carry2 : STD_LOGIC;

begin
HA1: Half_Adder port map (A, B, Sum1, Carry1);
HA2: Half_Adder port map (Sum1, Cin, Sum, Carry2);

Unit 3 29
 Cout <= Carry1 OR Carry2;
end Structural;

module Half_Adder (
input X,
input Y,
output Sum,
output Carry
);
assign Sum = X ^ Y;
assign Carry = X & Y;
endmodule

module Full_Adder (
input A,
input B,
input Cin,
output Sum,
output Cout
);
wire Sum1, Carry1, Carry2;

// Instantiate two half adders

Half_Adder HA1 (.X(A), .Y(B), .Sum(Sum1), .Carry(Carry1));
Half_Adder HA2 (.X(Sum1), .Y(Cin), .Sum(Sum), .Carry(Carry2)

// OR gate for final carry-out

assign Cout = Carry1 | Carry2;
endmodule

Unit 3 30
 Substractor

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Subtractor is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Borrow_in : in STD_LOGIC;
Diff : out STD_LOGIC;
Borrow_out : out STD_LOGIC );
end Subtractor;

architecture Behavioral of Subtractor is

begin
Diff <= A XOR B XOR Borrow_in;
Borrow_out <= (not A and B) or ((not (A XOR B)) and Borrow_i
end Behavioral;

module Subtractor(
input A,
input B,
input Borrow_in,
output Diff,
output Borrow_out
);
assign Diff = A ^ B ^ Borrow_in;
assign Borrow_out = (~A & B) | ((~(A ^ B)) & Borrow_in);
endmodule

Unit 3 31
 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Entity for the Subtractor

entity Subtractor is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Borrow_in : in STD_LOGIC;
Diff : out STD_LOGIC;
Borrow_out : out STD_LOGIC );
end Subtractor;

-- Structural Architecture for Subtractor

architecture Structural of Subtractor is

-- Declare the components for XOR, AND, NOT gates

component XOR_GATE is
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
Z : out STD_LOGIC );
end component;

component AND_GATE is
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
Z : out STD_LOGIC );
end component;

component NOT_GATE is
Port ( A : in STD_LOGIC;
Z : out STD_LOGIC );
end component;

Unit 3 32
 -- Signals for internal connections
signal xor1_out, xor2_out, and1_out, and2_out, not_a_out, no

begin
-- XOR1: First XOR for A and B
XOR1: XOR_GATE port map (A, B, xor1_out);

-- XOR2: Second XOR for xor1_out and Borrow_in

XOR2: XOR_GATE port map (xor1_out, Borrow_in, Diff);

-- NOT_GATE1: Invert A to get not_A

NOT1: NOT_GATE port map (A, not_a_out);

-- AND1: AND gate for the first borrow condition (NOT A AND
AND1: AND_GATE port map (not_a_out, B, and1_out);

-- NOT_GATE2: Invert xor1_out (A XOR B)

NOT2: NOT_GATE port map (xor1_out, not_xor_out);

-- AND2: AND gate for the second borrow condition ((NOT (A X

AND2: AND_GATE port map (not_xor_out, Borrow_in, and2_out);

-- OR Gate for Borrow_out: Combine the two AND results

Borrow_out <= and1_out or and2_out;

end Structural;

Serial Adder

Unit 3 33
 A Serial Adder adds two binary numbers one bit at a time, with each bit being
added in sequence. It requires a clock signal to synchronize the addition process.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Serial_Adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
clk : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC );
end Serial_Adder;

architecture Behavioral of Serial_Adder is

signal carry : STD_LOGIC;
begin
process(clk)
begin
if rising_edge(clk) then
Sum <= A XOR B XOR Cin;
carry <= (A AND B) OR (Cin AND (A XOR B));
end if;
end process;

Cout <= carry;

end Behavioral;

module Serial_Adder(
input A,
input B,

Unit 3 34
 input Cin,
input clk,
output reg Sum,
output reg Cout
);

reg carry;

always @(posedge clk) begin

Sum <= A ^ B ^ Cin;
carry <= (A & B) | (Cin & (A ^ B));
end

assign Cout = carry;

endmodule

Parallel Adder
A Parallel Adder adds two binary numbers all at once (i.e., all bits of the two
numbers are added simultaneously). For a 4-bit adder, each bit of the numbers is
added in parallel, and the carry propagates through each bit.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Parallel_Adder is
Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);

Unit 3 35
 Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR(3 downto 0);
Cout : out STD_LOGIC );
end Parallel_Adder;

architecture Behavioral of Parallel_Adder is

signal carry : STD_LOGIC_VECTOR(3 downto 0);
begin
process(A, B, Cin)
begin
Sum(0) <= A(0) XOR B(0) XOR Cin;
carry(0) <= (A(0) AND B(0)) OR (Cin AND (A(0) XOR B(0)))

Sum(1) <= A(1) XOR B(1) XOR carry(0);

carry(1) <= (A(1) AND B(1)) OR (carry(0) AND (A(1) XOR B

Sum(2) <= A(2) XOR B(2) XOR carry(1);

carry(2) <= (A(2) AND B(2)) OR (carry(1) AND (A(2) XOR B

Sum(3) <= A(3) XOR B(3) XOR carry(2);

carry(3) <= (A(3) AND B(3)) OR (carry(2) AND (A(3) XOR B

Cout <= carry(3);

end process;

end Behavioral;

module Parallel_Adder(
input [3:0] A,
input [3:0] B,
input Cin,
output reg [3:0] Sum,
output reg Cout
);

Unit 3 36
 reg [3:0] carry;

always @(*) begin

Sum[0] = A[0] ^ B[0] ^ Cin;
carry[0] = (A[0] & B[0]) | (Cin & (A[0] ^ B[0]));

Sum[1] = A[1] ^ B[1] ^ carry[0];

carry[1] = (A[1] & B[1]) | (carry[0] & (A[1] ^ B[1]));

Sum[2] = A[2] ^ B[2] ^ carry[1];

carry[2] = (A[2] & B[2]) | (carry[1] & (A[2] ^ B[2]));

Sum[3] = A[3] ^ B[3] ^ carry[2];

carry[3] = (A[3] & B[3]) | (carry[2] & (A[3] ^ B[3]));

Cout = carry[3];
end

endmodule

BCD Adder
A BCD Adder is a type of adder used to add Binary Coded Decimal (BCD)
numbers. In BCD, each decimal digit is represented by a 4-bit binary number,
ranging from 0000 to 1001 (0 to 9). A BCD adder adds two BCD numbers and
ensures that the result is still in valid BCD format. If the sum
exceeds 9 (i.e., 1001 in binary), an additional 6 ( 0110 in binary) is added to
correct the result back to valid BCD.
ere's an explanation of how a BCD Adder works:

The BCD numbers are added just like regular binary numbers.

Unit 3 37
 If the sum of two BCD digits is greater than 9 (i.e., 1010 or higher),
then 6 ( 0110 ) is added to correct the result.

The correction (adding 6 ) is performed using a conditional logic based on the

sum.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BCD_Adder is
Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR(3 downto 0);
Cout : out STD_LOGIC);
end BCD_Adder;

architecture Behavioral of BCD_Adder is

signal temp_sum : STD_LOGIC_VECTOR(4 downto 0); -- Temporary
begin

-- Adding A, B and Carry-In

temp_sum <= ("0" & A) + ("0" & B) + Cin;

-- Check if the sum is greater than 9 (i.e., 1010 binary or

process(temp_sum)
begin
if temp_sum > "01001" then -- Sum exceeds 9
Sum <= temp_sum(3 downto 0) + "0110"; -- Add 6 to c
Cout <= '1'; -- Carry-out will be set
else
Sum <= temp_sum(3 downto 0); -- No correction neede
Cout <= '0'; -- No carry-out

Unit 3 38
 end if;
end process;

end Behavioral;

nput Ports:

A , B : 4-bit BCD digits.

Cin : Carry-in (if adding multiple BCD digits).

Output Ports:

Sum : The 4-bit result after addition and correction (if needed).

Cout : Carry-out if the sum exceeds 9.

Internal Logic:

The two BCD numbers ( A and B ) are added along with the carry-in ( Cin )
to form a temporary 5-bit sum ( temp_sum ).

If the temp_sum is greater than 9 ( 01001 in binary), we add 6 ( 0110 in

binary) to adjust the result to valid BCD.

The Sum is assigned the lower 4 bits of the result, and the Cout (carry-out)
is set if the sum exceeds 9.

module BCD_Adder(
input [3:0] A, // 4-bit BCD input A
input [3:0] B, // 4-bit BCD input B
input Cin, // Carry-in
output reg [3:0] Sum, // 4-bit BCD sum
output reg Cout // Carry-out
);

reg [4:0] temp_sum; // 5-bit temporary sum to store carry

Unit 3 39
 always @(A or B or Cin) begin
temp_sum = A + B + Cin; // Add the inputs and carry

// Check if sum is greater than 9 (i.e., 1010 binary or

if (temp_sum > 9) begin
Sum = temp_sum[3:0] + 6; // Add 6 to correct the su
Cout = 1; // Carry-out
end
else begin
Sum = temp_sum[3:0]; // No correction needed
Cout = 0; // No carry-out
end
end

endmodule

Barrel Shifter
A Barrel Shifter is a digital circuit that can shift a data word (usually a multi-bit
binary number) by any number of positions in either direction (left or right), with
the shifted bits wrapping around to the opposite end. This is different from
traditional shift operations, where the bits that "fall off" during a shift are typically
lost. The barrel shifter handles this wrap-around operation and can shift the data
efficiently in parallel.

Types of Barrel Shifters:

1. Left Barrel Shifter: Shifts the bits to the left and wraps the leftmost bits around
to the rightmost positions.

2. Right Barrel Shifter: Shifts the bits to the right and wraps the rightmost bits
around to the leftmost positions.

Unit 3 40
 3. Bidirectional Barrel Shifter: Can shift in both left and right directions based on
the control signal.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Barrel_Shifter is
Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
Shift : in INTEGER range 0 to 3; -- Amount of shif
Direction : in STD_LOGIC; -- '0' for left shift, '1
Y : out STD_LOGIC_VECTOR(3 downto 0)
);
end Barrel_Shifter;

architecture Behavioral of Barrel_Shifter is

begin
process (A, Shift, Direction)
begin
if Direction = '0' then -- Left Shift
case Shift is
when 0 => Y <= A;
when 1 => Y <= A(2 downto 0) & A(3);
when 2 => Y <= A(1 downto 0) & A(3 downto 2);
when 3 => Y <= A(0) & A(3 downto 1);
when others => Y <= (others => '0');
end case;
else -- Right Shift
case Shift is
when 0 => Y <= A;
when 1 => Y <= A(0) & A(3 downto 1);
when 2 => Y <= A(1 downto 0) & A(3 downto 2);
when 3 => Y <= A(2 downto 0) & A(3);
when others => Y <= (others => '0');
end case;

Unit 3 41
 end if;
end process;
end Behavioral;

module Barrel_Shifter(
input [3:0] A, // 4-bit input data
input [1:0] Shift, // Amount of shift (2 bits for 0 to 3
input Direction, // Shift direction (0 for left, 1 for
output reg [3:0] Y // 4-bit shifted output
);

always @(A, Shift, Direction) begin

if (Direction == 0) begin // Left Shift
case(Shift)
2'b00: Y = A;
2'b01: Y = {A[2:0], A[3]};
2'b10: Y = {A[1:0], A[3:2]};
2'b11: Y = {A[0], A[3:1]};
default: Y = 4'b0000;
endcase
end else begin // Right Shift
case(Shift)
2'b00: Y = A;
2'b01: Y = {A[0], A[3:1]};
2'b10: Y = {A[1:0], A[3:2]};
2'b11: Y = {A[2:0], A[3]};
default: Y = 4'b0000;
endcase
end
end

endmodule

Unit 3 42
 Multiplier
A multiplier is a circuit that takes two numbers as input and produces their product
as
an output. So a binary multiplier takes binary numbers as inputs and produces a
result
in binary. Before moving forward, lets quickly recap binary multiplication first.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Multiplier_2bit_Behavioral is
Port ( A : in STD_LOGIC_VECTOR(1 downto 0); -- 2-bit input
B : in STD_LOGIC_VECTOR(1 downto 0); -- 2-bit input
P : out STD_LOGIC_VECTOR(3 downto 0) -- 4-bit output
);
end Multiplier_2bit_Behavioral;

architecture Behavioral of Multiplier_2bit_Behavioral is

begin
P <= (others => '0'); -- Initializing product
process(A, B)
begin
P(0) <= A(0) and B(0);
P(1) <= (A(1) and B(0)) or (A(0) and B(1));
P(2) <= (A(1) and B(1));
P(3) <= '0'; -- The carry out from multiplication is '0
end process;
end Behavioral;

Unit 3 43
 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Multiplier_2bit_Dataflow is
Port ( A : in STD_LOGIC_VECTOR(1 downto 0); -- 2-bit input
B : in STD_LOGIC_VECTOR(1 downto 0); -- 2-bit input
P : out STD_LOGIC_VECTOR(3 downto 0) -- 4-bit output
);
end Multiplier_2bit_Dataflow;

architecture Dataflow of Multiplier_2bit_Dataflow is

begin
P(0) <= A(0) and B(0);
P(1) <= (A(1) and B(0)) or (A(0) and B(1));
P(2) <= (A(1) and B(1));
P(3) <= '0'; -- No carry out bit in this simple 2-bit multi
end Dataflow;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Multiplier_2bit_Structural is
Port ( A : in STD_LOGIC_VECTOR(1 downto 0); -- 2-bit input
B : in STD_LOGIC_VECTOR(1 downto 0); -- 2-bit input
P : out STD_LOGIC_VECTOR(3 downto 0) -- 4-bit output
);
end Multiplier_2bit_Structural;

architecture Structural of Multiplier_2bit_Structural is

component AND_GATE
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
Z : out STD_LOGIC );

Unit 3 44
 end component;

component OR_GATE
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
Z : out STD_LOGIC );
end component;

signal and1, and2, and3, or1, or2 : STD_LOGIC;

begin
-- First AND Gate for A(0) and B(0)
AND1: AND_GATE port map (A(0), B(0), and1);

-- Second AND Gate for A(1) and B(0)

AND2: AND_GATE port map (A(1), B(0), and2);

-- Third AND Gate for A(0) and B(1)

AND3: AND_GATE port map (A(0), B(1), and3);

-- OR Gate to combine and2 and and3 to generate P(1)

OR1: OR_GATE port map (and2, and3, or1);

-- Assign final outputs

P(0) <= and1; -- P(0) is the result of A(0) and B(0)
P(1) <= or1; -- P(1) is the result of (A(1) and B(0)) or
P(2) <= A(1) and B(1); -- P(2) is the result of A(1) and B(
P(3) <= '0'; -- No carry out for this 2-bit multiplier

end Structural;

Unit 3 45
 module Multiplier_2bit_Behavioral (
input [1:0] A, // 2-bit input A
input [1:0] B, // 2-bit input B
output [3:0] P // 4-bit output product
);

assign P = (A[0] & B[0]) | (A[1] & B[0]) | (A[0] & B[1]) | (A[1]

endmodule

module Multiplier_2bit_Dataflow (
input [1:0] A, // 2-bit input A
input [1:0] B, // 2-bit input B
output [3:0] P // 4-bit output product
);

assign P[0] = A[0] & B[0]; // A(0) * B(0)

assign P[1] = (A[1] & B[0]) | (A[0] & B[1]); // A(1) * B(0) + A
assign P[2] = A[1] & B[1]; // A(1) * B(1)
assign P[3] = 0; // No carry out in this simple 2-bit multiplie

endmodule

module Multiplier_2bit_Structural (
input [1:0] A, // 2-bit input A
input [1:0] B, // 2-bit input B
output [3:0] P // 4-bit output product
);

wire and1, and2, and3, or1;

// AND gates to multiply individual bits

AND_GATE and_gate1 (A[0], B[0], and1);
AND_GATE and_gate2 (A[1], B[0], and2);

Unit 3 46
 AND_GATE and_gate3 (A[0], B[1], and3);

// OR gate to combine the results

OR_GATE or_gate (and2, and3, or1);

// Assign the outputs

assign P[0] = and1;
assign P[1] = or1;
assign P[2] = A[1] & B[1];
assign P[3] = 0; // No carry out

endmodule

module AND_GATE (
input X,
input Y,
output Z
);
assign Z = X & Y;
endmodule

module OR_GATE (
input X,
input Y,
output Z
);
assign Z = X | Y;
endmodule

ALU

Unit 3 47
 ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic operations lie
addition, subtraction, division, multiplication and logical operations like AND, OR,
XOR,
NAND, NOR etc. Arithmetic Logic Unit (ALU) is a critical component of a
microprocessor
and is the core component of central processing unit. ALU can perform all the 16
possible
logic operations or 16 different arithmetic operations on active HIGH or active LOW
operands.
To design a 4-bit Arithmetic Logic Unit (ALU) in VHDL and Verilog, we will create
an ALU that performs basic operations like addition, subtraction, AND, OR, and
XOR based on the control signals provided.

VHDL Design for 4-bit ALU

VHDL Code (Behavioral Model)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU_4bit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Ctrl : in STD_LOGIC_VECTOR (2 downto 0);
Result : out STD_LOGIC_VECTOR (3 downto 0);
Zero : out STD_LOGIC );
end ALU_4bit;

architecture Behavioral of ALU_4bit is

begin
process(A, B, Ctrl)
begin
case Ctrl is
when "000" => -- Addition

Unit 3 48
 Result <= A + B;
when "001" => -- Subtraction
Result <= A - B;
when "010" => -- AND
Result <= A and B;
when "011" => -- OR
Result <= A or B;
when "100" => -- XOR
Result <= A xor B;
when others => -- Default case for unrecognized
control signals
Result <= (others => '0');
end case;

-- Zero flag: If the result is all zeroes, set Zero f

lag to '1'
if Result = "0000" then
Zero <= '1';
else
Zero <= '0';
end if;
end process;
end Behavioral;

Explanation of VHDL Code:

Ports: The entity has inputs for two 4-bit vectors ( A and B ), a 3-bit control
signal ( Ctrl ) to choose the operation, and the 4-bit output ( Result ).
Additionally, a Zero flag is provided to indicate if the result is zero.

Process: The process block is sensitive to the inputs ( A , B , Ctrl ). Based on

the control signals, it performs the corresponding arithmetic or logic
operation.

"000" : Add A and B .

"001" : Subtract B from A .

Unit 3 49
 "010" : Perform AND operation between A and B .

"011" : Perform OR operation between A and B .

"100" : Perform XOR operation between A and B .

Zero Flag: If the result is all zeroes, the Zero flag is set to '1'.

Verilog Design for 4-bit ALU

Verilog Code (Behavioral Model)

module ALU_4bit (
input [3:0] A, // 4-bit input A
input [3:0] B, // 4-bit input B
input [2:0] Ctrl, // 3-bit control signal
output reg [3:0] Result, // 4-bit result
output reg Zero // Zero flag
);

always @ (A, B, Ctrl) begin

case (Ctrl)
3'b000: Result = A + B; // Addition
3'b001: Result = A - B; // Subtraction
3'b010: Result = A & B; // AND
3'b011: Result = A | B; // OR
3'b100: Result = A ^ B; // XOR
default: Result = 4'b0000; // Default case
endcase

// Zero flag: If result is zero, set Zero flag

if (Result == 4'b0000)
Zero = 1;
else
Zero = 0;
end

Unit 3 50
 endmodule

Explanation of Verilog Code:

Inputs and Outputs: The module takes two 4-bit inputs ( A and B ), a 3-bit
control signal ( Ctrl ), and produces a 4-bit result ( Result ). It also has a Zero
flag output.

Always Block: The always block triggers on any change in A , B , or Ctrl . It

performs the required operation based on the control signal ( Ctrl ).

3'b000 : Addition ( A + B ).

3'b001 : Subtraction ( A - B ).

3'b010 : AND operation ( A & B ).

3'b011 : OR operation ( A | B ).

3'b100 : XOR operation ( A ^ B ).

Zero Flag: If the Result is 4'b0000 , the Zero flag is set to 1 ; otherwise, it's 0 .

Structural Model Design for ALU (Both VHDL and Verilog)

In the structural model, you would break the ALU into smaller components such as
adders, subtractors, AND gates, OR gates, etc., and then instantiate these
components in the ALU. Here's a simplified example of how this might look in both
VHDL and Verilog:

VHDL Code (Structural)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU_4bit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);

Unit 3 51
 B : in STD_LOGIC_VECTOR (3 downto 0);
Ctrl : in STD_LOGIC_VECTOR (2 downto 0);
Result : out STD_LOGIC_VECTOR (3 downto 0);
Zero : out STD_LOGIC );
end ALU_4bit;

architecture Structural of ALU_4bit is

component Adder
Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
Sum : out STD_LOGIC_VECTOR(3 downto 0);
Carry : out STD_LOGIC );
end component;

component AND_Gate
Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
Result : out STD_LOGIC_VECTOR(3 downto 0) );
end component;

-- Declare internal signals

signal sum_result : STD_LOGIC_VECTOR(3 downto 0);
signal and_result : STD_LOGIC_VECTOR(3 downto 0);
signal or_result : STD_LOGIC_VECTOR(3 downto 0);
signal xor_result : STD_LOGIC_VECTOR(3 downto 0);

begin
-- Adders and logic gates instantiation
Adder1: Adder port map (A, B, sum_result, carry_out);
AND1: AND_Gate port map (A, B, and_result);
OR1: OR_Gate port map (A, B, or_result);
XOR1: XOR_Gate port map (A, B, xor_result);

-- Select result based on Ctrl

process (Ctrl)
begin

Unit 3 52
 case Ctrl is
when "000" => Result <= sum_result;
when "001" => Result <= sum_result; -- Subtractio
n can be implemented using two's complement
when "010" => Result <= and_result;
when "011" => Result <= or_result;
when "100" => Result <= xor_result;
when others => Result <= (others => '0');
end case;
end process;

-- Zero flag logic

process (Result)
begin
if Result = "0000" then
Zero <= '1';
else
Zero <= '0';
end if;
end process;

end Structural;

Verilog Code (Structural)

module ALU_4bit (
input [3:0] A,
input [3:0] B,
input [2:0] Ctrl,
output reg [3:0] Result,
output reg Zero
);

wire [3:0] sum_result, and_result, or_result, xor_result;

wire carry_out;

Unit 3 53
 // Instantiate components
Adder add1 (.A(A), .B(B), .Sum(sum_result), .Carry(carry_
out));
AND_Gate and1 (.A(A), .B(B), .Result(and_result));
OR_Gate or1 (.A(A), .B(B), .Result(or_result));
XOR_Gate xor1 (.A(A), .B(B), .Result(xor_result));

always @ (Ctrl, sum_result, and_result, or_result, xor_re

sult) begin
case (Ctrl)
3'b000: Result = sum_result;
3'b001: Result = sum_result; // Subtraction is tw
o's complement of sum
3'b010: Result = and_result;
3'b011: Result = or_result

;
3'b100: Result = xor_result;
default: Result = 4'b0000;
endcase
end

// Zero flag logic

always @ (Result) begin
if (Result == 4'b0000)
Zero = 1;
else
Zero = 0;
end

endmodule

Explanation of Structural Model:

Unit 3 54
 Component Instantiation: Each operation (Adder, AND gate, OR gate, XOR
gate) is defined as a separate component and instantiated within the ALU.

Result Selection: The appropriate result (sum, and, or, xor) is selected based
on the control signal Ctrl .

This is a basic structural design that can be extended by implementing each logic
operation in a separate module.

Unit 3 55