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Interrupts in The 8051 Microcontroller

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14 views3 pages

Interrupts in The 8051 Microcontroller

Uploaded by

Abhishek Perera
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Interrupts in the 8051 Microcontroller

Interrupts are a mechanism in the 8051 microcontroller that allow it to respond to external
events or internal triggers, temporarily suspending the main program's execution to handle
these events. This provides a way to handle time-critical tasks or unexpected events without
constantly polling for them in the main program loop.

Interrupt Sources

The 8051 has five hardware resources that can generate interrupt requests:

1. External Interrupt 0 (INT0) - Triggered by a low-level signal or a falling edge on the


INT0 pin (P3.2).
2. Timer 0 Interrupt (TF0) - Triggered when Timer 0 overflows.
3. External Interrupt 1 (INT1) - Triggered by a low-level signal or a falling edge on the
INT1 pin (P3.3).
4. Timer 1 Interrupt (TF1) - Triggered when Timer 1 overflows.
5. Serial Port Interrupt - when a byte is received (RI) or transmitted (TI) through the
serial port.

Interrupt Service Routines (ISRs)

Each interrupt source has a dedicated address in program memory where its corresponding
interrupt service routine (ISR) is located. When an interrupt occurs, the program counter
(PC) is pushed onto the stack, and the CPU jumps to the ISR's address to execute the code
that handles the interrupt.

Interrupt Source Starting Address (Hex)


External Interrupt 0 0003
Timer/Counter 0 Overflow 000B
External Interrupt 1 0013
Timer/Counter 1 Overflow 001B
Serial Port 0023

Interrupt Enable and Priority

Interrupts can be individually enabled or disabled using the Interrupt Enable (IE) register.
Additionally, each interrupt can be assigned a priority level (high or low) using the Interrupt
Priority (IP) register. High-priority interrupts can interrupt low-priority interrupt service
routines, but not vice versa.

Interrupt Handling Process


Interrupt Request: A hardware resource sets its interrupt request flag in the TCON or SCON
register.
👇
Interrupt Acknowledge: If the interrupt is enabled and has the highest priority among
pending interrupts, the CPU acknowledges it.
👇

Context Saving: The current program counter (PC) is pushed onto the stack.
👇

Vectoring to ISR: The CPU jumps to the starting address of the ISR for the triggered
interrupt.
👇

ISR Execution: The ISR code is executed to handle the interrupt.


👇

Return from Interrupt (RETI): The RETI instruction is executed at the end of the ISR, restoring
the PC from the stack and resuming the main program.

Essential reading: 2.8 INTERRUPT SYSTEM of the INTEL 8051 Architectural Specification
Chapter 10 in suppliementary material

What are the five hardware resources that can generate an interrupt request in the 8051 and
list the vector address (sources).

1. Timer 0 overflow interrupt- TF0

Interrupt vector address-000BH

2. Timer 1 overflow interrupt-TF1

Interrupt vector address-001BH

3. External hardware interrupt- INT0

Interrupt vector address-0003H

4. External hardware interrupt- INT1

Interrupt vector address-0013H


5. Serial communication interrupt- RI/TI

Interrupt vector address-0023H

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