Laboratory Exercise 1

Switches, Lights, and Multiplexers

The purpose of this exercise is to learn how to connect simple input and output devices to an FPGA chip and
implement a circuit that uses these devices. We will use the switches on the DE-series boards as inputs to the
circuit. We will use light emitting diodes (LEDs) and 7-segment displays as output devices.

Part I
The DE10-Lite, DE0-CV, and DE1-SoC boards provide ten switches and lights, called SW9−0 and LEDR9−0 .
Similarly, the DE2-115 provides eighteen switches and lights. The switches can be used to provide inputs, and the
lights can be used as output devices. Figure 1 shows a simple VHDL entity that uses ten switches and shows their
states on the LEDs. Since there are multiple switches and lights it is convenient to represent them as vectors in the
VHDL code, as shown. We have used a single assignment statement for all LEDR outputs, which is equivalent to
the individual assignments:
LEDR(9) <= SW(9);
LEDR(8) <= SW(8);
...
LEDR(0) <= SW(0);
The DE-series boards have hardwired connections between its FPGA chip and the switches and lights. To use
the switches and lights it is necessary to include in your Quartus R project the correct pin assignments, which
are given in your board’s user manual. For example, the DE1-SoC manual specifies that SW0 is connected to
the FPGA pin AB12 and LEDR0 is connected to pin V16. A good way to make the required pin assignments is to
import into the Quartus software the pin assignment file for your board, which is provided on the FPGA University
Program section of Intel’s web site. The procedure for making pin assignments is described in the tutorial Quartus
Introduction using VHDL Design, which is also available from Intel.

It is important to realize that the pin assignments in the file are useful only if the pin names that appear in this file
are exactly the same as the port names used in your VHDL entity. For example, if the pin assignment file uses the
names SW(0), . . ., SW(9) and LEDR(0), . . ., LEDR(9), then these are the names that must be used for input and
output ports in the VHDL code, as we have done in Figure 1.

LIBRARY ieee;
USE ieee.std_logic_1164.all;

- - Simple entity that connects the SW switches to the LEDR lights

ENTITY part1 IS
PORT ( SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
END part1;

ARCHITECTURE Behavior OF part1 IS

BEGIN
LEDR <= SW;
END Behavior

Figure 1: VHDL code that uses ten switches and lights.

1
Perform the following steps to implement a circuit corresponding to the code in Figure 1 on the DE-series boards.
1. Create a new Quartus project for your circuit. Select the target chip that corresponds to your DE-series
board. Refer to Table 1 for a list of devices.
2. Create a VHDL entity for the code in Figure 1 and include it in your project.

3. Include in your project the required pin assignments for your DE-series board, as discussed above. Compile
the project.
4. Download the compiled circuit into the FPGA chip by using the Quartus Programmer tool (the procedure
for using the Programmer tool is described in the tutorial Quartus Introduction). Test the functionality of
the circuit by toggling the switches and observing the LEDs.

Board Device Name

DE10-Lite MAX R 10 10M50DAF484C6GES
DE0-CV Cyclone R V 5CEBA4F23C7
DE1-SoC Cyclone R V SoC 5CSEMA5F31C6
DE2-115 Cyclone R IVE EP4CE115F29C7

Table 1: DE-series FPGA device names

Part II
Figure 2a shows a sum-of-products circuit that implements a 2-to-1 multiplexer with a select input s. If s = 0 the
multiplexer’s output m is equal to the input x, and if s = 1 the output is equal to y. Part b of the figure gives a
truth table for this multiplexer, and part c shows its circuit symbol.

s
y

a) Circuit

s
s m
0 x x 0
m
1 y y 1

b) Truth table c) Symbol

Figure 2: A 2-to-1 multiplexer.

The multiplexer can be described by the following VHDL statement:

m <= (NOT (s) AND x) OR (s AND y);

2
You are to write a VHDL entity that includes four assignment statements like the one shown above to describe the
circuit given in Figure 3a. This circuit has two four-bit inputs, X and Y , and produces the four-bit output M . If
s = 0 then M = X, while if s = 1 then M = Y . We refer to this circuit as a four-bit wide 2-to-1 multiplexer. It
has the circuit symbol shown in Figure 3b, in which X, Y , and M are depicted as four-bit wires.

x3 0
m3
y3 1

x2 0
m2 s
y2 1

4
X 0 4
M
Y 1
4

x0 0
m0
y0 1

a) Circuit b) Symbol

Figure 3: A four-bit wide 2-to-1 multiplexer.

Perform the steps listed below.

1. Create a new Quartus project for your circuit.

2. Include your VHDL file for the four-bit wide 2-to-1 multiplexer in your project. Use switch SW9 as the s
input, switches SW3−0 as the X input and SW7−4 as the Y input. Display the value of the input s on LEDR9 ,
connect the output M to LEDR3−0 , and connect the unused LEDR lights to the constant value 0.
3. Include in your project the required pin assignments for your DE-series board. As discussed in Part I, these
assignments ensure that the ports of your VHDL code will use the pins on the FPGA chip that are connected
to the SW switches and LEDR lights.
4. Compile the project, and then download the resulting circuit into the FPGA chip. Test the functionality of
the four-bit wide 2-to-1 multiplexer by toggling the switches and observing the LEDs.

Part III
In Figure 2 we showed a 2-to-1 multiplexer that selects between the two inputs x and y. For this part consider a
circuit in which the output m has to be selected from four inputs u, v, w, and x. Part a of Figure 4 shows how we
can build the required 4-to-1 multiplexer by using three 2-to-1 multiplexers. The circuit uses a 2-bit select input
s1 s0 and implements the truth table shown in Figure 4b. A circuit symbol for this multiplexer is given in part c of
the figure.

Recall from Figure 3 that a four-bit wide 2-to-1 multiplexer can be built by using four instances of a 2-to-1
multiplexer. Figure 5 applies this concept to define a two-bit wide 4-to-1 multiplexer. It contains two instances of
the circuit in Figure 4a.

3
 s1
s0

u 0
v 1

0
m
1

w 0
x 1

a) Circuit

s1
s0
s1 s0 m
0 0 u
0 1 v u 00
1 0 w v 01
1 1 x w 10 m
x 11

b) Truth table c) Symbol

Figure 4: A 4-to-1 multiplexer.

s1
s0
2
U
2 00
V 2
01
2 10 M
W 11
2
X

Figure 5: A two-bit wide 4-to-1 multiplexer.

Perform the following steps to implement the two-bit wide 4-to-1 multiplexer.
1. Create a new Quartus project for your circuit.
2. Create a VHDL entity for the two-bit wide 4-to-1 multiplexer. Connect its select inputs to switches SW9−8 ,
and use switches SW7−0 to provide the four 2-bit inputs U to X. Connect the output M to the red lights
LEDR1−0 .

3. Include in your project the required pin assignments for your DE-series board. Compile the project.
4. Download the compiled circuit into the FPGA chip. Test the functionality of the two-bit wide 4-to-1 mul-
tiplexer by toggling the switches and observing the LEDs. Ensure that each of the inputs U to X can be
properly selected as the output M .

4
Part IV
The objective of this part is to display a character on a 7-segment display. The specific character displayed de-
pends on a two-bit input. Figure 6 shows a 7-segment decoder entity that has the two-bit input c1 c0 . This decoder
produces seven outputs that are used to display a character on a 7-segment display. Table 2 lists the characters
that should be displayed for each valuation of c1 c0 for your DE-series board. Note that in some cases the ‘blank’
character is selected for code 11.

The seven segments in the display are identified by the indices 0 to 6 shown in the figure. Each segment is
illuminated by driving it to the logic value 0. You are to write a VHDL entity that implements logic functions to
activate each of the seven segments. Use only simple VHDL assignment statements in your code to specify each
logic function using a Boolean expression.

5 1
c1 7-segment 6
c0 decoder
4 2

Figure 6: A 7-segment decoder.

c1 c0 DE10-Lite DE0-CV DE1-SoC DE2-115

00 d d d d
01 E E E E
10 1 0 1 2
11 0

Table 2: Character codes for the DE-series boards.

Perform the following steps:

1. Create a new Quartus project for your circuit.

2. Create a VHDL entity for the 7-segment decoder. Connect the c1 c0 inputs to switches SW1−0 , and connect
the outputs of the decoder to the HEX0 display on your DE-series board. The segments in this display are
called HEX00 , HEX01 , . . ., HEX06 , corresponding to Figure 6. You should declare the 7-bit port

HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6);

in your VHDL code so that the names of these outputs match the corresponding names in your board’s user
manual and pin assignment file.
3. After making the required pin assignments, compile the project.
4. Download the compiled circuit into the FPGA chip. Test the functionality of the circuit by toggling the
SW1−0 switches and observing the 7-segment display.

5
Part V
Consider the circuit shown in Figure 7. It uses a two-bit wide 4-to-1 multiplexer to enable the selection of four
characters that are displayed on a 7-segment display. Using the 7-segment decoder from Part IV this circuit can
display the characters d, E, 0, 1, 2, or ‘blank’ depending on your DE-series board. The character codes are set
according to Table 2 by using the switches SW7−0 , and a specific character is selected for display by setting the
switches SW9−8 .

An outline of the VHDL code that represents this circuit is provided in Figure 8. Note that we have used the
circuits from Parts III and IV as subcircuits in this code. You are to extend the code in Figure 8 so that it uses
four 7-segment displays rather than just one. You will need to use four instances of each of the subcircuits. The
purpose of your circuit is to display any word on the three 7-segment displays that is composed of the characters
in Table 2, and be able to rotate this word in a circular fashion across the displays when the switches SW9−8
are toggled. As an example, if the displayed word is dE10, then your circuit should produce the output patterns
illustrated in Table 3.

SW 9
SW 8
2 0
SW 7 – 6
SW 5 – 4
2 00 5 1
01 2 7-segment 7 6
SW 3 – 2 2 10 decoder
11 4 2
2
SW 1 – 0
3

Figure 7: A circuit that can select and display one of four characters.

SW9−8 Characters
00 d E 1 0
01 E 1 0 d
10 1 0 d E
11 0 d E 1

Table 3: Rotating the word dE10 on four displays.

Perform the following steps.

1. Create a new Quartus project for your circuit.

2. Include your VHDL entity in the Quartus project. Connect the switches SW9−8 to the select inputs of each
of the three instances of the two-bit wide 3-to-1 multiplexers. Also connect SW5−0 to each instance of the
multiplexers as required to produce the patterns of characters shown in Table 2. Connect the SW switches
to the red lights LEDR, and connect the outputs of the three multiplexers to the 7-segment displays HEX2,
HEX1, and HEX0.

3. Include the required pin assignments for your DE-series board for all switches, LEDs, and 7-segment dis-
plays. Compile the project.
4. Download the compiled circuit into the FPGA chip. Test the functionality of the circuit by setting the proper
character codes on the switches SW5−0 and then toggling SW9−8 to observe the rotation of the characters.

6
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY part5 IS
PORT ( SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6) );
END part5;

ARCHITECTURE Behavior OF part5 IS

COMPONENT mux_2bit_4to1
PORT ( S, U, V, W, X : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END COMPONENT;
COMPONENT char_7seg
PORT ( C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Display : OUT STD_LOGIC_VECTOR(0 TO 6));
END COMPONENT;
SIGNAL M0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
U0: mux_2bit_4to1 PORT MAP (SW(9 DOWNTO 8), SW(7 DOWNTO 6), SW(5 DOWNTO 4),
SW(3 DOWNTO 2), SW(1 DOWNTO 0), M0);
H0: char_7seg PORT MAP (M0, HEX0);
...
END Behavior;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

- - implements a 2-bit wide 4-to-1 multiplexer

ENTITY mux_2bit_4to1 IS
PORT ( S, U, V, W, X : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END mux_2bit_4to1;

ARCHITECTURE Behavior OF mux_2bit_4to1 IS

. . . code not shown

END Behavior;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY char_7seg IS
PORT ( C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Display : OUT STD_LOGIC_VECTOR(0 TO 6));
END char_7seg;

ARCHITECTURE Behavior OF char_7seg IS

. . . code not shown

END Behavior;

Figure 8: VHDL code for the circuit in Figure 7

7
Part VI
Extend your design from Part V so that is uses all 7-segment displays on your DE-series board. Your circuit needs
to display a three- or four-letter word, corresponding to Table 2, using ’blank’ characters for unused displays.
Implement rotation of this word from right-to-left as indicated in Table 4 and Table 5. To do this, you will need to
connect 6-to-1 multiplexers to each of six 7-segment display decoders for the DE10-Lite, DE0-CV and DE1-SoC.
Note that for the DE10-Lite you will need to use 3-bit codes for your characters, because five characters are needed
when including the ’blank’ character (your 7-segment decoder will have to use 3-bit codes, and you will need to
use 3-bit wide 6-to-1 multiplexers). For the DE2-115, you will need to connect 8-to-1 multiplexers to each of the
eight 7-segment display decoders. You will need to use three select lines for each of the multiplexers: connect the
select lines to switches SW9−7 . In your VHDL code connect constants to the 6-to-1 (or 8-to-1) multiplexers that
select each character, because there are not enough SW switches.

SW9−7 Character pattern

000 d E 1 0
001 d E 1 0
010 d E 1 0
011 E 1 0 d
100 1 0 d E
101 0 d E 1

Table 4: Rotating the word dE10 on six displays.

SW9−7 Character pattern

000 d E 2
001 d E 2
010 d E 2
011 d E 2
100 d E 2
101 d E 2
110 E 2 d
111 2 d E

Table 5: Rotating the word dE2 on eight displays.

Perform the following steps:

1. Create a new Quartus project for your circuit.

2. Include your VHDL entity in the Quartus project. Connect the switches SW9−7 to the select inputs of each
instance of the multiplexers in your circuit. Connect constants in your VHDL code to the multiplexers as
required to produce the patterns of characters shown in Table 4 or Table 5 depending on your DE-series
board. Connect the outputs of your multiplexers to the 7-segment displays HEX5, . . ., HEX0 of the DE10-
Lite, DE0-CV and DE1-SoC or HEX7, . . ., HEX0 for the DE2-115.

3. Include the required pin assignments for your DE-series board for all switches, LEDs, and 7-segment dis-
plays. Compile the project.
4. Download the compiled circuit into the FPGA chip. Test the functionality of the circuit by toggling SW9−7
to observe the rotation of the characters.

8
Copyright c Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Avalon, Cyclone, En-
pirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in
the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products
and services at any time without notice. Intel assumes no responsibility or liability arising out of the application
or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
Intel customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

9
 Laboratory Exercise 2
Numbers and Displays

This is an exercise in designing combinational circuits that can perform binary-to-decimal number conversions
and binary-coded-decimal (BCD) addition.

Part I
We wish to display on the 7-segment displays HEX1 and HEX0 the values set by the switches SW7−0 . Let the
values denoted by SW7−4 and SW3−0 be displayed on HEX1 and HEX0, respectively. Your circuit should be able
to display the digits from 0 to 9, and should treat the valuations 1010 to 1111 as don’t-cares.

1. Create a new project which will be used to implement the desired circuit on your Intel R FPGA DE-series
board. The intent of this exercise is to manually derive the logic functions needed for the 7-segment displays.
Therefore, you should use only simple VHDL assignment statements in your code and specify each logic
function as a Boolean expression.
2. Write a VHDL file that provides the necessary functionality. Include this file in your project and assign the
pins on the FPGA to connect to the switches and 7-segment displays. Make sure to include the necessary
pin assignments.
3. Compile the project and download the compiled circuit into the FPGA chip.
4. Test the functionality of your design by toggling the switches and observing the displays.

Part II
You are to design a circuit that converts a four-bit binary number V = v3 v2 v1 v0 into its two-digit decimal equiv-
alent D = d1 d0 . Table 1 shows the required output values. A partial design of this circuit is given in Figure 1. It
includes a comparator that checks when the value of V is greater than 9, and uses the output of this comparator in
the control of the 7-segment displays. You are to complete the design of this circuit.

v3 v2 v1 v0 d1 d0
0000 0 0
0001 0 1
0010 0 2
... ... ...
1001 0 9
1010 1 0
1011 1 1
1100 1 2
1101 1 3
1110 1 4
1111 1 5

Table 1: Binary-to-decimal conversion values.

The output z for the comparator circuit can be specified using a single Boolean expression, with the four inputs
V3−0 . Design this Boolean expression by making a truth table that shows the valuations of the inputs V3−0 for
which z has to be 1.

1
 d1

z 5 1
Comparator 7 6
>9
4 2

d0

4 5 1
V 0 4 7 6
1
4 4 2

3
A
Circuit A

Figure 1: Partial design of the binary-to-decimal conversion circuit.

Notice that the circuit in Figure 1 includes a 4-bit wide 2-to-1 multiplexer (a similar multiplexer was described
as part of Laboratory Exercise 1). The purpose of this multiplexer is to drive digit d0 with the value of V when
z = 0, and the value of A when z = 1. To design circuit A consider the following. For the input values V ≤ 9, the
circuit A does not matter, because the multiplexer in Figure 1 just selects V in these cases. But for the input values
V > 9, the multiplexer will select A. Thus, A has to provide output values that properly implement Table 1 when
V > 9. You need to design circuit A so that the input V = 1010 gives an output A = 0000, the input V = 1011
gives the output A = 0001, . . ., and the input V = 1111 gives the output A = 0101. Design circuit A by making
a truth table with the inputs V3−0 and the outputs A3−0 .

Perform the following steps:

1. Write VHDL code to implement your design. The code should have the 4-bit input SW3−0 , which should
be used to provide the binary number V , and the two 7-bit outputs HEX1 and HEX0, to show the values
of decimal digits d1 and d0 . The intent of this exercise is to use simple VHDL assignment statements to
specify the required logic functions using Boolean expressions. Your VHDL code should not include any
IF-ELSE, CASE, or similar statements.
2. Make a Quartus R project for your VHDL entity.

3. Compile the circuit and use functional simulation to verify the correct operation of your comparator, multi-
plexers, and circuit A.
4. Download the circuit into an FPGA board. Test the circuit by trying all possible values of V and observing
the output displays.

Part III
Figure 2a shows a circuit for a full adder, which has the inputs a, b, and ci , and produces the outputs s and co .
Parts b and c of the figure show a circuit symbol and truth table for the full adder, which produces the two-bit
binary sum co s = a + b + ci . Figure 2d shows how four instances of this full adder module can be used to design
a circuit that adds two four-bit numbers. This type of circuit is usually called a ripple-carry adder, because of

2
the way that the carry signals are passed from one full adder to the next. Write VHDL code that implements this
circuit, as described below.

ci
a s ci
s
a FA
b 0
co
b
co
1

a) Full adder circuit b) Full adder symbol

b a ci co s b3 a3 c b2 a2 c b1 a1 c b 0 a 0 c in
3 2 1
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0 FA FA FA FA
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1 c out s 3 s2 s1 s0

c) Full adder truth table d) Four-bit ripple-carry adder circuit

Figure 2: A ripple-carry adder circuit.

1. Create a new Quartus project for the adder circuit. Write a VHDL entity for the full adder subcircuit and
write a top-level VHDL entity that instantiates four instances of this full adder.
2. Use switches SW7−4 and SW3−0 to represent the inputs A and B, respectively. Use SW8 for the carry-in
cin of the adder. Connect the outputs of the adder, cout and S, to the red lights LEDR.
3. Include the necessary pin assignments for your DE-series board, compile the circuit, and download it into
the FPGA chip.
4. Test your circuit by trying different values for numbers A, B, and cin .

Part IV
In Part II we discussed the conversion of binary numbers into decimal digits. For this part you are to design a
circuit that has two decimal digits, X and Y , as inputs. Each decimal digit is represented as a 4-bit number. In
technical literature this is referred to as the binary coded decimal (BCD) representation.
You are to design a circuit that adds the two BCD digits. The inputs to your circuit are the numbers X and Y ,
plus a carry-in, cin . When these inputs are added, the result will be a 5-bit binary number. But this result is to
be displayed on 7-segment displays as a two-digit BCD sum S1 S0 . For a sum equal to zero you would display
S1 S0 = 00, for a sum of one S1 S0 = 01, for nine S1 S0 = 09, for ten S1 S0 = 10, and so on. Note that the
inputs X and Y are assumed to be decimal digits, which means that the largest sum that needs to be handled by
this circuit is S1 S0 = 9 + 9 + 1 = 19.
Perform the steps given below.

1. Create a new Quartus project for your BCD adder. You should use the four-bit adder circuit from Part III to
produce a four-bit sum and carry-out for the operation X + Y .

3
 A good way to work out the design of your circuit is to first make it handle only sums (X + Y ) ≤ 15. With
these values, your circuit from Part II can be used to convert the 4-bit sum into the two decimal digits S1 S0 .
Then, once this is working, modify your design to handle values of 15 < (X + Y ) ≤ 19. One way to do
this is to still use your circuit from Part II, but to modify its outputs before attaching them to the 7-segment
display to make the necessary adjustments when the sum from the adder exceeds 15.
Write your VHDL code using simple assignment statements to specify the required logic functions–do not
use other types of VHDL statements such as IF-ELSE or CASE statements for this part of the exercise.
2. Use switches SW7−4 and SW3−0 for the inputs X and Y , respectively, and use SW8 for the carry-in.
Connect the four-bit sum and carry-out produced by the operation X + Y to the red lights LEDR. Display
the BCD values of X and Y on the 7-segment displays HEX5 and HEX3, and display the result S1 S0 on
HEX1 and HEX0.
3. Since your circuit handles only BCD digits, check for the cases when the input X or Y is greater than nine.
If this occurs, indicate an error by turning on the red light LEDR9 .
4. Include the necessary pin assignments for your DE-series board, compile the circuit, and download it into
the FPGA chip.

5. Test your circuit by trying different values for numbers X, Y , and cin .

Part V
In Part IV you created VHDL code for a BCD adder. A different approach for describing the adder in VHDL code
is to specify an algorithm like the one represented by the following pseudo-code:

1 T0 = A + B + c0
2 if (T0 > 9) then
3 Z0 = 10;
4 c1 = 1;
5 else
6 Z0 = 0;
7 c1 = 0;
8 end if
9 S0 = T0 − Z0
10 S1 = c1

It is reasonably straightforward to see what circuit could be used to implement this pseudo-code. Lines 1 and 9
represent adders, lines 2-8 correspond to multiplexers, and testing for the condition T0 > 9 requires comparators.
You are to write VHDL code that corresponds to this pseudo-code. Note that you can perform addition operations
in your VHDL code instead of the subtraction shown in line 9. The intent of this part of the exercise is to examine
the effects of relying more on the VHDL compiler to design the circuit by using IF-ELSE statements along with
the VHDL > and + operators. Perform the following steps:

1. Create a new Quartus project for your VHDL code. Use switches SW7−4 and SW3−0 for the inputs A and
B, respectively, and use SW8 for the carry-in. The value of A should be displayed on the 7-segment display
HEX5, while B should be on HEX3. Display the BCD sum, S1 S0 , on HEX1 and HEX0.
2. Use the Quartus RTL Viewer tool to examine the circuit produced by compiling your VHDL code. Compare
the circuit to the one you designed in Part IV.
3. Download your circuit onto your DE-series board and test it by trying different values for numbers A and
B.

4
Part VI
Design a combinational circuit that converts a 6-bit binary number into a 2-digit decimal number represented in
the BCD form. Use switches SW5−0 to input the binary number and 7-segment displays HEX1 and HEX0 to
display the decimal number. Implement your circuit on the DE1-SoC board and demonstrate its functionality.

5
 Laboratory Exercise 3
Latches, Flip-flops, and Registers

The purpose of this exercise is to investigate latches, flip-flops, and registers.

Part I
Intel R FPGAs include flip-flops that are available for implementing a user’s circuit. We will show how to make
use of these flip-flops in Part IV of this exercise. But first we will show how storage elements can be created in an
FPGA without using its dedicated flip-flops.
Figure 1 depicts a gated RS latch circuit. A style of VHDL code that uses logic expressions to describe this circuit
is given in Figure 2. If this latch is implemented in an FPGA that has 4-input lookup tables (LUTs), then only one
lookup table is needed, as shown in Figure 3a.

R R_g
Qa (Q)

Clk

Qb
S S_g

Figure 1: A gated RS latch circuit.

- - A gated RS latch desribed the hard way

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY part1 IS
PORT ( Clk, R, S : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END part1;

ARCHITECTURE Structural OF part1 IS

SIGNAL R_g, S_g, Qa, Qb : STD_LOGIC ;
ATTRIBUTE KEEP : BOOLEAN;
ATTRIBUTE KEEP OF R_g, S_g, Qa, Qb : SIGNAL IS TRUE;
BEGIN
R_g <= R AND Clk;
S_g <= S AND Clk;
Qa <= NOT (R_g OR Qb);
Qb <= NOT (S_g OR Qa);

Q <= Qa;

END Structural;

Figure 2: Specifying the RS latch by using logic expressions.

1
Although the latch can be correctly realized in one 4-input LUT, this implementation does not allow its internal
signals, such as R_g and S_g, to be observed, because they are not provided as outputs from the LUT. To preserve
these internal signals in the implemented circuit, it is necessary to include a compiler directive in the code. In
Figure 2 the directive KEEP is included by using a VHDL ATTRIBUTE statement to instruct the Quartus R
compiler to use separate logic elements for each of the signals R_g, S_g, Qa, and Qb. Compiling the code
produces the circuit with four 4-LUTs depicted in Figure 3b.

R
Qa (Q)
Clk
4-LUT
S

(a) Using one 4-input lookup table for the RS latch.

R R_g
4-LUT
Qa (Q)
4-LUT

Clk

S_g
4-LUT
S 4-LUT
Qb

(b) Using four 4-input lookup tables for the RS latch.

Figure 3: Implementation of the RS latch from Figure 1.

Create a Quartus project for the RS latch circuit as follows:

1. Create a new Quartus project for your DE-series board.
2. Generate a VHDL file with the code in Figure 2 and include it in the project.

3. Compile the code. Use the Quartus RTL Viewer tool to examine the gate-level circuit produced from the
code, and use the Technology Map Viewer tool to verify that the latch is implemented as shown in Figure 3b.
4. Simulate the behavior of your VHDL code by using the simulation feature provided in the Modelsim soft-
ware. Use the testbench provided in the laboratory materials to drive the signals for your simulation. The
procedure for using Modelsim for simulation is described in the tutorial Introduction to Simulation of VHDL
Designs Using ModelSim Graphical Waveform Editor. An example of a vector waveform file is displayed
in Figure 4. The waveforms in the figure begin by setting Clk = 1 and R = 1, which allows the simulation
tool to initialize all of the signals inside of the latch to known values.

2
 Figure 4: Simulation waveforms for the RS latch.

Part II
Figure 5 shows the circuit for a gated D latch.

S
D S_g
Qa (Q)

Clk

Qb
R
R_g

Figure 5: Circuit for a gated D latch.

Perform the following steps:

1. Create a new Quartus project. Generate a VHDL file using the style of code in Figure 2 for the gated D
latch. Use the KEEP directive to ensure that separate logic elements are used to implement the signals
R, S_g, R_g, Qa, and Qb.

2. Compile your project and then use the Technology Map Viewer tool to examine the implemented circuit.
3. Verify that the latch works properly for all input conditions by using functional simulation. Examine the
timing characteristics of the circuit by using timing simulation.
4. Create a new Quartus project which will be used for implementation of the gated D latch on your DE-series
board. This project should consist of a top-level module that contains the appropriate input and output ports
(pins) for your board. Instantiate your latch in this top-level module. Use switch SW0 to drive the D input
of the latch, and use SW1 as the Clk input. Connect the Q output to LEDR0 .
5. Include the required pin assignments and then compile your project and download the compiled circuit onto
your DE-series board.

6. Test the functionality of your circuit by toggling the D and Clk switches and observing the Q output.

Part III
Figure 6 shows the circuit for a master-slave D flip-flop.

3
 Master Slave
Qm Qs
D D Q D Q Q

Clock Clk Q Clk Q Q

Figure 6: Circuit for a master-slave D flip-flop.

Perform the following:

1. Create a new Quartus project. Generate a VHDL file that instantiates two copies of your gated D latch
module from Part II to implement the master-slave flip-flop.
2. Include in your project the appropriate input and output ports for your DE-series board. Use switch SW0 to
drive the D input of the flip-flop, and use SW1 as the Clock input. Connect the Q output to LEDR0 .

3. Include the required pin assignments and then compile your project.
4. Use the Technology Viewer to examine the D flip-flop circuit, and use simulation to verify its correct oper-
ation.
5. Download the circuit onto your DE-series board and test its functionality by toggling the D and Clock
switches and observing the Q output.

4
Part IV
Figure 7 shows a circuit with three different storage elements: a gated D latch, a positive-edge triggered D flip-flop,
and a negative-edge triggered D flip-flop.

D D Q Qa

Clock Clk Q Qa

D Q Qb

Q Qb

D Q Qc

Q Qc

(a) Circuit

Clock

Qa

Qb

Qc

(b) Timing diagram

Figure 7: Circuit and waveforms for Part IV.

Implement and simulate this circuit using the Quartus software as follows:

1. Create a new Quartus project.

2. Write a VHDL file that instantiates the three storage elements. For this part you should no longer use the
KEEP directive (that is, the VHDL ATTRIBUTE statement) from Parts I to III. Figure 8 gives a behavioral
style of VHDL code that specifies the gated D latch in Figure 5. This latch can be implemented in one
4-input lookup table. Use a similar style of code to specify the flip-flops in Figure 7.

3. Compile your code and use the Technology Map Viewer to examine the implemented circuit. Verify that
the latch uses one lookup table and that the flip-flops are implemented using the flip-flops provided in the
target FPGA.

5
 4. Use Modelsim to simulate the circuit you created. Use the included testbench file to specify the inputs
D and Clock as indicated in Figure 7. Make sure that the testbench correctly instantiates the module you
created and run the simulation to observe the different behavior of the three storage elements.

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY latch IS
PORT ( D, Clk : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END latch ;

ARCHITECTURE Behavior OF latch IS

BEGIN
PROCESS ( D, Clk )
BEGIN
IF Clk = ’1’ THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;

Figure 8: A behavioral style of VHDL code that specifies a gated D latch.

Part V
We wish to display the hexadecimal value of an 8-bit number A on the two 7-segment displays HEX3 − 2. We
also wish to display the hex value of an 8-bit number B on the two 7-segment displays HEX1 − 0. The values
of A and B are inputs to the circuit which are provided by means of switches SW7−0 . To input the values of A
and B, first set the switches to the desired value of A, store these switch values in a register, and then change the
switches to the desired value of B. Finally, use an adder to generate the arithmetic sum S = A + B, and display
this sum on the 7-segment displays HEX5 − 4. Show the carry-out produced by the adder on LEDR(0).
1. Create a new Quartus project which will be used to implement the desired circuit on your DE-series board.

2. Write a VHDL file that provides the necessary functionality. Use KEY0 as an active-low asynchronous reset,
and use KEY1 as a clock input.
3. Include the necessary pin assignments for the pushbutton switches and 7-segment displays, and then compile
the circuit.

4. Download the circuit onto your DE-series board and test its functionality by toggling the switches and
observing the output displays.

6
Copyright c Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Avalon, Cyclone, En-
pirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in
the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products
and services at any time without notice. Intel assumes no responsibility or liability arising out of the application
or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
Intel customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

7
 Laboratory Exercise 4
Counters

The purpose of this exercise is to build and use counters. The designed circuits are to be implemented on an
Intel R FPGA DE10-Lite, DE0-CV, DE1-SoC, or DE2-115 Board.

Students are expected to have a basic understanding of counters and sufficient familiarity with the VHDL hardware
description language to implement various types of latches and flip-flops.

Part I
Consider the circuit in Figure 1. It is a 4-bit synchronous counter which uses four T-type flip-flops. The counter
increments its value on each positive edge of the clock signal if the Enable signal is high. The counter is reset to
0 on the next positive clock edge if the synchronous Clear input is low. You are to implement an 8-bit counter of
this type.

Enable T Q T Q T Q T Q

Clock Q Q Q Q

Clear

Figure 1: A 4-bit counter.

1. Write a VHDL file that defines an 8-bit counter by using the structure depicted in Figure 1. Your code
should include a T flip-flop entity that is instantiated eight times to create the counter. Compile the circuit.
How many logic elements (LEs) are used to implement your circuit?
2. Simulate your circuit to verify its correctness.
3. Augment your VHDL file to use the pushbutton KEY0 as the Clock input and switches SW1 and SW0 as
Enable and Clear inputs, and 7-segment displays HEX1-0 to display the hexadecimal count as your circuit
operates. Make the necessary pin assignments needed to implement the circuit on your DE-series board,
and compile the circuit.
4. Download your circuit into the FPGA chip and test its functionality by operating the switches.
5. Implement a four-bit version of your circuit and use the Quartus R RTL Viewer to see how the Quartus
software synthesized the circuit. What are the differences in comparison with Figure 1?

Part II
Another way to specify a counter is by using a register and adding 1 to its value. This can be accomplished using
the following VHDL statement:
Q <= Q + 1;
Compile a 16-bit version of this counter and determine the number of LEs needed. Use the RTL Viewer to see
the structure of this implementation and comment on the differences with the design from Part I. Implement the
counter on your DE-series board, using the displays HEX3-0 to show the counter value.

1
Part III
Design and implement a circuit that successively flashes digits 0 through 9 on the 7-segment display HEX0. Each
digit should be displayed for about one second. Use a counter to determine the one-second intervals. The counter
should be incremented by the 50-MHz clock signal provided on the DE-series boards. Do not derive any other
clock signals in your design–make sure that all flip-flops in your circuit are clocked directly by the 50-MHz clock
signal. A partial design of the required circuit is shown in Figure 2. The figure shows how a large bit-width counter
can be used to produce an enable signal for a smaller counter. The rate at which the smaller counter increments
can be controlled by choosing an appropriate number of bits in the larger counter.

Counter
50 MHz Clock

E
Counter

Slow count

Figure 2: Making a slow counter.

Part IV
Design and implement a circuit that displays a word on four 7-segment displays HEX3 − 0. The word to be
displayed for your DE-series board is given in Table 1. Make the letters rotate from right to left in intervals of
about one second. The rotating pattern for the DE10-Lite is given in Table 2. If you are using the DE0-CV, DE1-
SoC, or DE2-115, use the word given in Table 1. There are many ways to design the required circuit. One solution
is to re-use the VHDL code designed in Laboratory Exercise 1, Part V. Using that code, the main change needed is
to replace the two switches that are used to select the characters being rotated on the displays with a 2-bit counter
that increments at one-second intervals.

Board Word
DE10-Lite dE10
DE0-CV dE0
DE1-SoC dE1
DE2-115 dE2

Table 1: DE-series boards and corresponding word to display

Count Characters
00 d E 1 0
01 E 1 0 d
10 1 0 d E
11 0 d E 1

Table 2: Rotating the word dE10 on four displays.

2
Part V
Augment your circuit from Part IV so that it can rotate the word over all of the 7-segment displays on your
DE-series board. The shifting pattern for the DE10-Lite is shown in Table 3.

Count Character pattern

000 d E 1 0
001 d E 1 0
010 d E 1 0
011 E 1 0 d
100 1 0 d E
101 0 d E 1

Table 3: Rotating the word dE10 on six displays.

3
Copyright c Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Avalon, Cyclone, En-
pirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in
the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products
and services at any time without notice. Intel assumes no responsibility or liability arising out of the application
or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
Intel customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

4
 Laboratory Exercise 5
Timers and Real-time Clock

The purpose of this exercise is to study the use of clocks in timed circuits. The designed circuits are to be
implemented on an Intel R FPGA DE10-Lite, DE0-CV, DE1-SoC, or DE2-115 board.

Background
In the VHDL hardware description language we can describe a variable-size counter by using a GENERIC decla-
ration. An example of an n-bit counter is shown in Figure 1.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY counter IS
GENERIC ( n : NATURAL := 4 );
PORT ( clock : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(n−1 DOWNTO 0) );
END ENTITY;

ARCHITECTURE Behavior OF counter IS

SIGNAL value : STD_LOGIC_VECTOR(n−1 DOWNTO 0));
BEGIN
PROCESS (clock, reset_n)
BEGIN
IF (reset_n = ’0’) THEN
value <= (OTHERS => ’0’);
ELSIF ((clock’EVENT) AND (clock = 1 )) THEN
value <= value + 1;
END IF
END PROCESS
Q <= value;
END Behavior;

Figure 1: A VHDL description of an n-bit counter.

The parameter n specifies the number of bits in the counter. A particular value of this parameter is defined by
using a GENERIC MAP statement. For example, an 8-bit counter can be specified as:

eight_bit: counter
GENERIC MAP ( n => 8 )
PORT MAP eight_bit (clock, reset_n, Q);

By using parameters we can instantiate counters of different sizes in a logic circuit, without having to create a new
module for each counter.

1
Part I
Create a modulo-k counter by modifying the design of an 8-bit counter to contain an additional parameter. The
counter should count from 0 to k − 1. When the counter reaches the value k − 1, then the next counter value should
be 0. Include an output from the counter called rollover and set this output to 1 in the clock cycle where the count
value is equal to k − 1.
Perform the following steps:
1. Create a new Quartus R project which will be used to implement the desired circuit on your DE-series board.
2. Write a Verilog file that specifies the circuit for k = 20, and an appropriate value of n. Your circuit should use
pushbutton KEY0 as an asynchronous reset and KEY1 as a manual clock input. The contents of the counter
should be displayed on the red lights LEDR. Also display the rollover signal on one of the LEDR lights.
3. Include the VHDL file in your project and compile the circuit.
4. Simulate the designed circuit to verify its functionality.

5. Make the necessary pin assignments needed to implement the circuit on your DE-series board, and compile
the circuit.
6. Verify that your circuit works correctly by observing the lights.

Part II
Using your modulo-counter from Part I as a subcircuit, implement a 3-digit BCD counter (hint: use multiple
counters, not just one). Display the contents of the counter on the 7-segment displays, HEX2−0. Connect all
of the counters in your circuit to the 50-MHz clock signal on your DE-series board, and make the BCD counter
increment at one-second intervals. Use the pushbutton switch KEY0 to reset the BCD counter to 0.

Part III
Design and implement a circuit on your DE-series board that acts as a real-time clock. It should display the
minutes (from 0 to 59) on HEX5 − 4, the seconds (from 0 to 59) on HEX3 − 2, and hundredths of a second (from
0 to 99) on HEX1 − 0. Use the switches SW7−0 to preset the minute part of the time displayed by the clock when
KEY1 is pressed. Stop the clock whenever KEY0 is being pressed and continue the clock when KEY0 is released.

Part IV
An early method of telegraph communication was based on the Morse code. This code uses patterns of short and
long pulses to represent a message. Each letter is represented as a sequence of dots (a short pulse), and dashes (a
long pulse). For example, the first eight letters of the alphabet have the following representation:

A •—
B —•••
C —•—•
D —••
E •
F ••—•
G ——•
H ••••

2
 Pushbuttons and switches

Letter size register

Data
Enable
Load
Letter
Selection Logic LEDR0
Logic Letter symbols shift register
Data
Enable
Load

2-bit counter
Reset
Enable

Figure 2: High-level schematic diagram of the circuit for part IV.

Design and implement a circuit that takes as input one of the first eight letters of the alphabet and displays the
Morse code for it on a red LED. Your circuit should use switches SW2−0 and pushbuttons KEY1−0 as inputs. When
a user presses KEY1 , the circuit should display the Morse code for a letter specified by SW2−0 (000 for A, 001 for
B, etc.), using 0.5-second pulses to represent dots, and 1.5-second pulses to represent dashes. Pushbutton KEY0
should function as an asynchronous reset. A high-level schematic diagram of the circuit is shown in Figure 2.

Hint: Use a counter to generate 0.5-second pulses, and another counter to keep the LEDR0 light on for either
0.5 or 1.5 seconds.

3
Copyright c Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Avalon, Cyclone, En-
pirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in
the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products
and services at any time without notice. Intel assumes no responsibility or liability arising out of the application
or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
Intel customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

4
 Laboratory Exercise 6
Adders, Subtractors, and Multipliers

The purpose of this exercise is to examine arithmetic circuits that add, subtract, and multiply numbers. Each
circuit will be described in VHDL and implemented on an Intel R FPGA DE10-Lite, DE0-CV, DE1-SoC, or DE2-
115 board.

Part I
Consider again the four-bit ripple-carry adder circuit used in lab exercise 2; its diagram is reproduced in Figure 1.

b3 a3 c b2 a2 c b1 a1 c b 0 a 0 c in
3 2 1

carry FA FA FA FA

s3 s2 s1 s0

a) Four-bit ripple-carry adder circuit

Figure 1: A four-bit ripple carry adder.
A
This circuit can be implemented using a ’+’ sign in VHDL.8 For example, the following code fragment adds n-bit
numbers A and B to produce outputs sum and carry:
R
LIBRARY ieee;
Clock Q
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all; 8
USE ieee.std_logic_signed.all;
... overflow c in
Q D 0
SIGNAL sum : STD_LOGIC_VECTOR(n-1 + DOWNTO 0);
... 8
sum <= A + B;
R
Q
Use this construct to implement a circuit shown in Figure 2. This circuit, which is often called an accumulator, is
used to add the value of an input A to itself repeatedly. The circuit includes a carry out from the adder, as well as
Overflow S
an overflow output signal. If the input A is considered as a 2’s-complement number, then overflow should be set
to 1 in the case where the output sum produced does not represent a correct 2’s-complement result.
b) Eight-bit registered adder circuit

Perform the following steps:

1. Create a new Quartus R project. Write VHDL code that describes the circuit in Figure 2.

2. Connect input A to switches SW7−0 , use KEY0 as an active-low asynchronous reset, and use KEY1 as a
manual clock input. The sum from the adder should be displayed on the red lights LEDR7−0 , the registered
carry signal should be displayed on LEDR8 , and the registered overflow signal should be displayed on
LEDR9 . Show the registered values of A and S as hexadecimal numbers on the 7-segment displays HEX3−2
and HEX1 − 0.

1
 b3 a3 c b2 a2 c b1 a1 c b 0 a 0 c in
3 2 1

3. Make the necessary pin assignments needed to implement the circuit on your DE-series board, and compile
carry FA FA FA FA
the circuit.
4. Use timing simulation to verify the correct operation of the circuit. Once the simulation works properly,
download the circuit onto your DE-series board s 1 values of A.
s 3 and test it bys 2using different s 0 Be sure to check
that the overflow output works correctly.
a) Four-bit ripple-carry adder circuit

A
8

R
Clock Q

Logic
Q D
circuit 0
+

8
Q D
R
Q

overflow carry S

Figure 2: An eight-bit accumulator circuit.

Part II
Extend the circuit from Part I to be able to both add and subtract numbers. To do so, introduce an add_sub input
to your circuit. When add_sub is 1, your circuit should subtract A from S, and when add_sub is 0 your circuit
should add A to S as in Part I.

Part III
Figure 3a gives an example of paper-and-pencil multiplication P = A × B, where A = 11 and B = 12.

a3 a2 a1 a0
x b3 b2 b1 b0

1 0 1 1 a3 b0 a2 b0 a1 b0 a0 b0
1 1 x 1 1 0 0
x 1 2 a3 b1 a2 b1 a1 b1 a0 b1
0 0 0 0
2 2 0 0 0 0 a3 b2 a2 b2 a1 b2 a0 b2
1 1 1 0 1 1 a3 b3 a2 b3 a1 b3 a0 b3
1 0 1 1
1 3 2 p7 p6 p5 p4 p3 p2 p1 p0
1 0 0 0 0 1 0 0

a) Decimal b) Binary c) Implementation

Figure 3: Multiplication of binary numbers.

2
We compute P = A × B as an addition of summands. The first summand is equal to A times the ones digit of B.
The second summand is A times the tens digit of B, shifted one position to the left. We add the two summands to
form the product P = 132.

Part b of the figure shows the same example using four-bit binary numbers. To compute P = A × B, we first form
summands by multiplying A by each digit of B. Since each digit of B is either 1 or 0, the summands are either
shifted versions of A or 0000. Figure 3c shows how each summand can be formed by using the Boolean AND
operation of A with the appropriate bit of B.

A four-bit circuit that implements P = A × B is illustrated in Figure 4. Because of its regular structure, this type
of multiplier circuit is called an array multiplier. The shaded areas correspond to the shaded columns in Figure 3c.
In each row of the multiplier AND gates are used to produce the summands, and full adder modules are used to
generate the required sums.

a3 a2 a3 a1 a2 a0 a1 a0
b0

b1

b a b a b a b a
c o FA c i c o FA c i c o FA c i c o FA c i 0
s s s s
a3 a2 a1 a0
b2

b a b a b a b a
c o FA c i c o FA c i c o FA c i c o FA c i 0
s s s s
a3 a2 a1 a0
b3

b a b a b a b a
c o FA c i c o FA c i c o FA c i c o FA c i 0
s s s s

p7 p6 p5 p4 p3 p2 p1 p0

Figure 4: An array multiplier circuit.

Perform the following steps to implement the array multiplier circuit:

1. Create a new Quartus project.

2. Generate the required VHDL file. Use switches SW7−4 to represent the number A and switches SW3−0 to
represent B. The hexadecimal values of A and B are to be displayed on the 7-segment displays HEX2 and

3
 HEX0, respectively. The result P = A × B is to be displayed on HEX5 − 4.
3. Make the necessary pin assignments needed to implement the circuit on your DE-series board, and compile
the circuit.
4. Use simulation to verify your design.

5. Download your circuit onto your DE-series board and test its functionality.

Part IV
In Part III, an array multiplier was implemented using full adder modules. At a higher level, a row of full adders
functions as an n-bit adder and the array multiplier circuit can be represented as shown in Figure 5.

a3 a2 a1 a0

b0

a3 a2 a1 a0

b1

b3 a3 b2 a2 b1 a1 b0 a0
co n-bit Adder ci 0
s3 s2 s1 s0
a3 a2 a1 a0
b2

b3 a3 b2 a2 b1 a1 b0 a0
co n-bit Adder ci 0
s3 s2 s1 s0
a3 a2 a1 a0
b3

b3 a3 b2 a2 b1 a1 b0 a0
co n-bit Adder ci 0
s3 s2 s1 s0

p7 p6 p5 p4 p3 p2 p1 p0

Figure 5: An array multiplier implemented using n-bit adders.

Each n-bit adder adds a shifted version of A for a given row and the partial product of the row above. Abstracting
the multiplier circuit as a sequence of additions allows us to build larger multipliers. The multiplier should consist

4
of n-bit adders arranged in a structure shown in Figure 5. Use this approach to implement an 8 x 8 multiplier
circuit with registered inputs and outputs, as shown in Figure 6.

Data inputs

8 8

EA E D D E EB
Clock Q Q

A B

Multiplier

16

D
R
Q

Figure 6: A registered multiplier circuit.

Perform the following steps:

1. Create a new Quartus project and write the required VHDL file.
2. Use switches SW7−0 to provide the data inputs to the circuit. Use SW9 as the enable signal EA for register A,
and use SW8 as the enable for register B. When SW9 = 1 display the contents of register A on the red lights
LEDR, and display the contents of register B on these lights when SW8 = 1. Use KEY0 as a synchronous
reset input, and use KEY1 as a manual clock signal. Show the product P = A × B as a hexadecimal number
on the 7-segment displays HEX3-0.
3. Make the necessary pin assignments needed to implement the circuit on your DE-series board, and compile
the circuit.

4. Test the functionality of your design by inputting various data values and observing the generated products.

Part V
Part IV showed how to implement multiplication A × B as a sequence of additions, by accumulating the shifted
versions of A one row at a time. Another way to implement this circuit is to perform addition using an adder tree.
An adder tree is a method of adding several numbers together in a parallel fashion. This idea is illustrated in
Figure 7. In the figure, numbers A, B, C, D, E, F , G, and H are added together in parallel. The addition A + B
happens simultaneously with C + D, E + F and G + H. The result of these operations are then added in parallel
again, until the final sum P is computed.

5
 A B C D E F G H

+ + + +

+ +

+
P

Figure 7: An example of adding 8 numbers using an adder tree.

In this part you are to implement an 8 x 8 multiplier circuit by using the adder-tree approach. Inputs A and B, as
well as the output P should be registered as in Part IV.

6
Copyright c Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Avalon, Cyclone, En-
pirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in
the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products
and services at any time without notice. Intel assumes no responsibility or liability arising out of the application
or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
Intel customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

7
 Laboratory Exercise 7
Finite State Machines

This is an exercise in using finite state machines.

Part I
We wish to implement a finite state machine (FSM) that recognizes two specific sequences of applied input sym-
bols, namely four consecutive 1s or four consecutive 0s. There is an input w and an output z. Whenever w = 1 or
w = 0 for four consecutive clock pulses the value of z has to be 1; otherwise, z = 0. Overlapping sequences are
allowed, so that if w = 1 for five consecutive clock pulses the output z will be equal to 1 after the fourth and fifth
pulses. Figure 1 illustrates the required relationship between w and z.

Clock

Figure 1: Required timing for the output z.

A state diagram for this FSM is shown in Figure 2. For this part you are to manually derive an FSM circuit that
implements this state diagram, including the logic expressions that feed each of the state flip-flops. To implement
the FSM use nine state flip-flops called y8 , . . . , y0 and the one-hot state assignment given in Table 1.

1
 Reset

A/0
w=0 w=1
1
B/0 0 F/0

w=0 1
1 0
C/0 G/0

w=0 1 0 1

D/0 1 0 H/0

w=0 1

0 E/1 I/1 1

Figure 2: A state diagram for the FSM.

State Code
Name y8 y7 y6 y5 y4 y3 y2 y1 y0
A 000000001
B 000000010
C 000000100
D 000001000
E 000010000
F 000100000
G 001000000
H 010000000
I 100000000

Table 1: One-hot codes for the FSM.

Design and implement your circuit on your DE-series board as follows:

1. Create a new Quartus R project for the FSM circuit.

2. Write a VHDL file that instantiates the nine flip-flops in the circuit and which specifies the logic expressions
that drive the flip-flop input ports. Use only simple assignment statements in your VHDL code to specify the
logic feeding the flip-flops. Note that the one-hot code enables you to derive these expressions by inspection.
Use the toggle switch SW0 as an active-low synchronous reset input for the FSM, use SW1 as the w input,
and the pushbutton KEY0 as the clock input which is applied manually. Use the red light LEDR9 as the
output z, and assign the state flip-flop outputs to the red lights LEDR8 to LEDR0 .
3. Include the VHDL file in your project, and assign the pins on the FPGA to connect to the switches and the
LEDs.

2
 4. Simulate the behavior of your circuit.
5. Once you are confident that the circuit works properly as a result of your simulation, download the circuit
into the FPGA chip. Test the functionality of your design by applying the input sequences and observing
the output LEDs. Make sure that the FSM properly transitions between states as displayed on the red LEDs,
and that it produces the correct output values on LEDR9 .

6. Finally, consider a modification of the one-hot code given in Table 1. It is often desirable to set all flip-flop
outputs to the value 0 in the reset state.
Table 2 shows a modified one-hot state assignment in which the reset state, A, uses all 0s. This is accom-
plished by inverting the state variable y0 . Create a modified version of your VHDL code that implements
this state assignment. (Hint: you should need to make very few changes to the logic expressions in your
circuit to implement the modified state assignment.)
7. Compile your new circuit and test it.

State Code
Name y8 y7 y6 y5 y4 y3 y2 y1 y0
A 000000000
B 000000011
C 000000101
D 000001001
E 000010001
F 000100001
G 001000001
H 010000001
I 100000001

Table 2: Modified one-hot codes for the FSM.

Part II
For this part you are to write another style of Verilog code for the FSM in Figure 2. In this version of the code
you should not manually derive the logic expressions needed for each state flip-flop. Instead, describe the state
table for the FSM by using a VHDL CASE statement in a PROCESS block, and use another PROCESS block to
instantiate the state flip-flops. You can use a third PROCESS block or simple assignment statements to specify the
output z. To implement the FSM, use four state flip-flops y3 , . . . , y0 and binary codes, as shown in Table 3.

State Code
Name y3 y2 y1 y0
A 0000
B 0001
C 0010
D 0011
E 0100
F 0101
G 0110
H 0111
I 1000

Table 3: Binary codes for the FSM.

3
A suggested skeleton of the VHDL code is given in Figure 3.

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY part2 IS
PORT ( . . . define input and output ports
. . .);
END part2;

ARCHITECTURE Behavior OF part2 IS

. . . declare signals
TYPE State_type IS (A, B, C, D, E, F, G, H, I);
– Attribute to declare a specific encoding for the states
attribute syn_encoding : string;
attribute syn_encoding of State_type : type is "0000 0001 0010 0011 0100 0101 0110 0111 1000";

SIGNAL y_Q, Y_D : State_type; - - y_Q is present state, y_D is next state
BEGIN
...
PROCESS (w, y_Q) - - state table
BEGIN
case y_Q IS
WHEN A IF (w = ’0’) THEN Y_D <= B;
ELSE Y_D <= F;
END IF;
. . . other states
END CASE;
END PROCESS; - - state table

PROCESS (Clock) - - state flip-flops

BEGIN
...
END PROCESS;

. . . assignments for output z and the LEDs

END Behavior;

Figure 3: Skeleton VHDL code for the FSM.

Implement your circuit as follows.

1. Create a new project for the FSM.

2. Include in the project your VHDL file that uses the style of code in Figure 3. Use the same switches,
pushbuttons, and lights that were used in Part I.

3. Before compiling your code it is necessary to explicitly tell the Synthesis tool in Quartus that you wish to
have the finite state machine implemented using the state assignment specified in your VHDL code. If you
do not explicitly give this setting to Quartus, the Synthesis tool will automatically use a state assignment
of its own choosing, and it will ignore the state codes specified in your VHDL code. To make this setting,
choose Assignments > Settings in Quartus, and click on the Compiler Settings item on the left side of

4
 the window, then click on the Advanced Settings (Synthesis) button. As indicated in Figure 4, change
the parameter State Machine Processing to the setting User-Encoded.
4. Compile your project. To examine the circuit produced by Quartus open the RTL Viewer tool. Double-click
on the box shown in the circuit that represents the finite state machine, and determine whether the state
diagram that it shows properly corresponds to the one in Figure 2. To see the state codes used for your FSM,
open the Compilation Report, select the Analysis and Synthesis section of the report, and click on State
Machines.
5. Download the circuit into the FPGA chip and test its functionality.
6. In step 3 you instructed the Quartus Synthesis tool to use the state assignment given in your VHDL code. To
see the result of removing this setting, open again the Quartus settings window by choosing Assignments >
Settings, and Compiler Settings item on the left side of the window, then click on the Advanced Settings
(Synthesis) button. Change the setting for State Machine Processing from User-Encoded to One-Hot.
Recompile the circuit and then open the report file, select the Analysis and Synthesis section of the report,
and click on State Machines. Compare the state codes shown to those given in Table 2, and discuss any
differences that you observe.

Figure 4: Specifying the state assignment method in Quartus.

Part III
The sequence detector can be implemented in a straightforward manner using shift registers, instead of using the
more formal approach described above. Create VHDL code that instantiates two 4-bit shift registers; one is for
recognizing a sequence of four 0s, and the other for four 1s. Include the appropriate logic expressions in your
design to produce the output z. Make a Quartus project for your design and implement the circuit on your DE-
series board. Use the switches and LEDs on the board in a similar way as you did for Parts I and II and observe
the behavior of your shift registers and the output z. Answer the following question: could you use just one 4-bit
shift register, rather than two? Explain your answer.

5
Part IV
In this part of the exercise you are to implement a Morse-code encoder using an FSM. The Morse code uses pat-
terns of short and long pulses to represent a message. Each letter is represented as a sequence of dots (a short
pulse), and dashes (a long pulse). For example, the first eight letters of the alphabet have the following represen-
tation:

A •—
B —•••
C —•—•
D —••
E •
F ••—•
G ——•
H ••••

Design and implement a Morse-code encoder circuit using an FSM. Your circuit should take as input one of
the first eight letters of the alphabet and display the Morse code for it on a red LED. Use switches SW2−0 and
pushbuttons KEY1−0 as inputs. When a user presses KEY1 , the circuit should display the Morse code for a letter
specified by SW2−0 (000 for A, 001 for B, etc.), using 0.5-second pulses to represent dots, and 1.5-second pulses
to represent dashes. Pushbutton KEY0 should function as an asynchronous reset.
A high-level schematic diagram of a possible circuit for the Morse-code encoder is shown in Figure 5.

Pushbuttons and switches

Morse code length counter

Data
Enable
Load
Letter
selection FSM LEDR0
logic Morse code shift register
Data
Enable
Load

Half-second counter

Figure 5: High-level schematic diagram of the circuit for Part IV.

6
Copyright c Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Avalon, Cyclone, En-
pirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in
the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products
and services at any time without notice. Intel assumes no responsibility or liability arising out of the application
or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
Intel customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

7
 Laboratory Exercise 8
Memory Blocks

In computer systems it is necessary to provide a substantial amount of memory. If a system is implemented

using FPGA technology it is possible to provide some amount of memory by using the memory resources that
exist in the FPGA device. In this exercise we will examine the general issues involved in implementing such
memory.

A diagram of the random access memory (RAM) module that we will implement is shown in Figure 1a. It contains
32 four-bit words (rows), which are accessed using a five-bit address port, a four-bit data port, and a write control
input.

The FPGAs that are included on the Intel R FPGA DE10-Lite, DE0-CV, DE1-SoC, and DE2-115 boards provide
dedicated memory resources. The MAX R 10 FPGA on the DE10-Lite, and Cyclone R IV FPGA on the DE2-115
contain dedicated memory resources called M9K blocks. The Cyclone V FPGA on the DE0-CV and DE1-SoC
boards have M10K blocks. Each M9K block contains 9216 memory bits, while each M10K block contains 10240
memory bits. Both M9K and M10k blocks can be configured to implement memories of various sizes. A common
term used to specify the size of a memory is its aspect ratio, which gives the depth in words and the width in bits
(depth x width). In this exercise we will use an aspect ratio that is four bits wide, and we will use only the first 32
words in the memory. Although the M9K and M10K blocks support many other modes of operation, we will not
discuss them here.

5
Address
4
32 x 4 RAM Data
Write

(a) RAM organization

5 5
Address

4 4
DataIn 32 x 4 RAM 4
DataOut

Write
Clock

(b) RAM implementation

Figure 1: A 32 x 4 RAM module.

1
There are two important features of the M9K and M10K blocks that have to be mentioned. First, they includes
registers that can be used to synchronize all of the input and output signals to a clock input. The registers on the
input ports must always be used, and the registers on the output ports are optional. Second, the blocks have separate
ports for data being written to the memory and data being read from the memory. Given these requirements, we
will implement the modified 32 x 4 RAM module shown in Figure 1b. It includes registers for the address, data
input, and write ports, and uses a separate unregistered data output port.

Part I
Commonly used logic structures, such as adders, registers, counters and memories, can be implemented in an
FPGA chip by using prebuilt modules that are provided in libraries. In this exercise we will use such a module to
implement the memory shown in Figure 1b.

1. Create a new Quartus R project to implement the memory module.

2. To open the IP Catalog in the Quartus software click on Tools > IP Catalog. In the IP Catalog window
choose the RAM: 1-PORT module, which is found under the Basic Functions > On Chip Memory cate-
gory. Select VHDL as the type of output file to create, give the file the name ram32x4.vhd, and click OK.
As shown in Figure 2 specify a memory size of 32 four-bit words. Select M9K if your DE-series board
has a MAX 10 or Cyclone IV FPGA, otherwise select M10K. Also on this screen accept the default setting
to use a single clock for the memory’s registers, and then advance to the page shown in Figure 3. On this
page deselect the setting called ’q’ output port under the category Which ports should be registered?.
This setting creates a RAM module that matches the structure in Figure 1b, with registered input ports and
unregistered output ports. Accept defaults for the rest of the settings in the Wizard, and click the Finish
button to exit from this tool. Examine the ram32x4.vhd VHDL file which defines the following subcircuit:

ENTITY ram32x4 IS
PORT ( address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC := ’1’;
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
END ram32x4;

3. Instantiate this subcircuit in a top-level VHDL file that includes appropriate input and output signals for the
memory ports given in Figure 1b.
4. Compile the circuit. Observe in the Compilation Report that the Quartus Compiler uses 128 bits in one of
the FPGA memory blocks to implement the RAM circuit.

5. Simulate the behavior of your circuit using Modelsim and ensure that you can read and write data in the
memory. Use the included testbench file as a baseline for your simulation inputs. An example simulation
output is given in Figure 4.

2
Figure 2: Configuring the size of the memory module.

Figure 3: Configuring input and output ports.

3
 Figure 4: An example of simulation output.

Part II
Now, we want to realize the memory circuit in the FPGA on your DE-series board, and use slide switches to load
some data into the created memory. We also want to display the contents of the RAM on the 7-segment displays.
1. Make a new Quartus project which will be used to implement the desired circuit on your DE-series board.

2. Create another VHDL file that instantiates the ram32x4 module and that includes the required input and
output pins on your DE-series board. Use slide switches SW3−0 to provide input data for the RAM, and
use switches switches SW8−4 to specify the address. Use SW9 as the Write signal and use KEY0 as the
Clock input. Show the address value on the 7-segment displays HEX5 − 4, show the data being input to the
memory on HEX2, and show the data read out of the memory on HEX0.

3. Test your circuit and make sure that data can be stored into the memory at various locations.

Part III
Instead of creating a memory module subcircuit by using the IP Catalog, we can implement the required memory
by specifying its structure in VHDL code. In a VHDL-specified design it is possible to define the memory as a
multidimensional array. A 32 x 4 array, which has 32 words with 4 bits per word, can be declared by the statement

TYPE mem IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL memory_array : mem;

In an FPGA such an array can be implemented either by using the flip-flops that each logic element contains or,
more efficiently, by using the built-in memory blocks. The Quartus Help provides other examples of VHDL code
that show how memory can be specified (search in the Help for “Inferred memory”).

Perform the following steps:

1. Create a new project which will be used to implement the desired circuit on your DE-series board.
2. Write a VHDL file that provides the necessary functionality, including the ability to load the RAM and read
its contents as was done in Part II.

3. Assign the pins on the FPGA to connect to the switches and the 7-segment displays.
4. Compile the circuit and download it into the FPGA chip.
5. Test the functionality of your design by applying some inputs and observing the output.

4
Part IV
The SRAM block in Figure 1 has a single port that provides the address for both read and write operations. For
this part you will create a different type of memory module, in which there is one port for supplying the address
for a read operation, and a separate port that gives the address for a write operation. Perform the following steps.

1. Create a new Quartus project for your circuit. To generate the desired memory module open the IP Catalog
and select the RAM: 2-PORT module in the Basic Functions > On Chip Memory category. As shown in
Figure 5, choose With one read port and one write port in the category called How will you be using
the dual port ram?
Configure the memory size, clocking method, and registered ports the same way as Part II. As shown in
Figure 6 select I do not care (The outputs will be undefined) for Mixed Port Read-During-Write for
Single Input Clock RAM. This setting specifies that it does not matter whether the memory outputs the
new data being written, or the old data previously stored, in the case that the write and read addresses are
the same during a write operation.
Figure 7 shows how the memory words can be initialized to specific values. It makes use of a feature that
allows the memory module to be loaded with data when the circuit is programmed into the FPGA chip.
As shown in the figure, choose the setting Yes, use this file for the memory content data, and specify
the filename ram32x4.mif. An example of a MIF file is provided in Figure 8. You can also learn about the
format of a memory initialization file (MIF) by using the Quartus Help. You will need to create a MIF file
like the one in Figure 8 to test your circuit. Finish the Wizard and then examine the generated memory
module in the file ram32x4.vhd.
2. Write a VHDL file that instantiates your dual-port memory. To see the RAM contents, add to your design
a capability to display the content of each four-bit word (in hexadecimal format) on the 7-segment display
HEX0. Use a counter as a read address, and scroll through the memory locations by displaying each word
for about one second. As each word is being displayed, show its address (in hex format) on the 7-segment
displays HEX3−2. Use the 50 MHz clock, CLOCK_50, and use KEY0 as a reset input. For the write address
and corresponding data use switches SW8−4 and SW3−0 . Show the write address on HEX5 − 4 and show the
write data on HEX1. Make sure that you properly synchronize the slide switch inputs to the 50 MHz clock
signal.

3. Test your circuit and verify that the initial contents of the memory match your ram32x4.mif file. Make sure
that you can independently write data to any address by using the slide switches.

5
 Figure 5: Configuring the two input ports of the RAM.

Figure 6: Configuring the output of the RAM when reading and writing to the same address.

6
Figure 7: Specifying a memory initialization file (MIF).

DEPTH = 32;
WIDTH = 4;
ADDRESS_RADIX = HEX;
DATA_RADIX = BIN;
CONTENT
BEGIN

0 : 0000;
1 : 0001;
2 : 0010;
3 : 0011;
. . . (some lines not shown)
1E : 1110;
1F : 1111;

END;

Figure 8: An example memory initialization file (MIF).

7
Copyright c Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Avalon, Cyclone, En-
pirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in
the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products
and services at any time without notice. Intel assumes no responsibility or liability arising out of the application
or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
Intel customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

8
 Laboratory Exercise 9
A Simple Processor

Figure 1 shows a digital system that contains a number of 16-bit registers, a multiplexer, an adder/subtracter,
and a control unit (finite state machine). Information is input to this system via the 16-bit DIN input, which is
loaded into the IR register. Data can be transferred through the 16-bit wide multiplexer from one register in the
system to another, such as from register IR into one of the general purpose registers r0, . . . , r7. The multiplexer’s
output is called Buswires in the figure because the term bus is often used for wiring that allows data to be trans-
ferred from one location in a system to another. The FSM controls the Select lines of the multiplexer, which allows
any of its inputs to be transferred to any register that is connected to the bus wires.

The system can perform different operations in each clock cycle, as governed by the FSM. It determines when
particular data is placed onto the bus wires and controls which of the registers is to be loaded with this data. For
example, if the FSM selects r0 as the output of the bus multiplexer and also asserts Ain , then the contents of
register r0 will be loaded on the next active clock edge into register A.

Addition or subtraction of signed numbers is performed by using the multiplexer to first place one 16-bit number
onto the bus wires, and then loading this number into register A. Once this is done, a second 16-bit number is
placed onto the bus, the adder/subtracter performs the required operation, and the result is loaded into register G.
The data in G can then be transferred via the multiplexer to one of the other registers, as required.
16

16 16 16 16
A in
r 0 in r 7 in
r0 r7 A

Clock
AddSub
Adder/Subtracter

16
Multiplexer G in
G

16

Select Buswires

4
IR in

16
DIN IR

Control unit FSM

Run
Resetn
Done

Figure 1: A digital system.

1
A system like the one in Figure 1 is often called a processor. It executes operations specified in the form of
instructions. Table 1 lists the instructions that this processor supports. The left column shows the name of an
instruction and its operands. The meaning of the syntax rX ← Op2 is that the second operand, Op2, is loaded into
register rX. The operand Op2 can be either a register, rY, or immediate data, #D.

Instruction Function performed

mv rX, Op2 rX ← Op2
mvt rX, #D rX15−8 ← D15−8
add rX, Op2 rX ← rX + Op2
sub rX, Op2 rX ← rX − Op2

Table 1: Instructions performed in the processor.

Instructions are loaded from the external input DIN, and stored into the IR register, using the connection indicated
in Figure 1. Each instruction is encoded using a 16-bit format. If Op2 specifies a register, then the instruction
encoding is III0XXX000000YYY, where III specifies the instruction, XXX gives the rX register, and YYY gives
the rY register. If Op2 specifies immediate data #D, then the encoding is III1XXXDDDDDDDDD, where the 9-bit
field DDDDDDDDD represents the constant data. Although only two bits are needed to encode our four instructions,
we are using three bits because other instructions will be added to the processor later. Assume that III = 000 for
the mv instruction, 001 for mvt, 010 for add, and 011 for sub.

The mv instruction (move) copies the contents of one register into another, using the syntax mv rX,rY. It can
also be used to initialize a register with immediate data, as in mv rX,#D. Since the data D is represented inside
the encoded instruction using only nine bits, the processor has to zero-extend the data, as in 0000000D8−0 ,
before loading it into register rX. The mvt instruction (move top) is used to initialize the most-significant byte
of a register. For mvt, only eight bits of the D field in the instruction are used, so that mvt rX,#D loads the
value D15−8 00000000 into rX. As an example, to load register r0 with the value 0xFF00, you would use the
instruction mvt r0,#0xFF00. The instruction add rX,rY produces the sum rX + rY and loads the result into
rX. The instruction add rX,#D produces the sum rX + D, where D is zero-extended to 16 bits, and saves the
result in rX. Similarly, the sub instruction generates either rX − rY, or rX − #D and loads the result into rX.

Some instructions, such as an add or sub, take a few clock cycles to complete, because multiple transfers have to
be performed across the bus. The finite state machine in the processor “steps through” such instructions, asserting
the control signals needed in successive clock cycles until the instruction has completed. The processor starts
executing the instruction on the DIN input when the Run signal is asserted and the processor asserts the Done
output when the instruction is finished. Table 2 indicates the control signals from Figure 1 that have to be asserted
in each time step to implement the instructions in Table 1. The only control signal asserted in time step T0 , for all
instructions, is IRin . The meaning of Select = rY or IR in the table is that the multiplexer selects either register
rY or the immediate data in IR, depending on the value of Op2. For the mv instruction, when IR is selected the
multiplexer outputs 0000000DDDDDDDDD, and for mvt the multiplexer outputs DDDDDDDD00000000. Only
signals from Figure 1 that have to be asserted in each time step are listed in Table 1; all other signals are not
asserted. The meaning of AddSub in step T2 of the sub instruction is that this signal is set to 1, and this setting
causes the adder/subtracter unit to perform subtraction using 2’s-complement arithmetic.

The processor in Figure 1 can perform various tasks by using a sequence of instructions. For example, the sequence
below loads the number 28 into register r0 and then calculates, in register r1, the 2’s complement value −28.

mv r0, #28 // original number = 28

mvt r1, #0xFF00
add r1, #0x00FF // r1 = 0xFFFF
sub r1, r0 // r1 = 1’s-complement of r0
add r1, #1 // r1 = 2’s-complement of r0 = -28

2
 T0 T1 T2 T3
mv IRin Select = rY or IR,
rXin , Done
mvt IRin Select = IR,
rXin , Done
add IRin Select = rX, Select = rY or IR, Select = G, rXin ,
Ain Gin Done
sub IRin Select = rX, Select = rY or IR, Select = G, rXin ,
Ain AddSub, Gin Done

Table 2: Control signals asserted in each instruction/time step.

Part I
Implement the processor shown in Figure 1 using VHDL code, as follows:
1. Make a new folder for this part of the exercise. Part of the VHDL code for the processor is shown in parts
a to c of Figure 2, and a more complete version of the code is provided with this exercise, in a file named
proc.vhd. You can modify this code to suit your own coding style if desired—the provided code is just a
suggested solution. Fill in the missing parts of the VHDL code to complete the design of the processor.

ENTITY proc IS
PORT ( DIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Resetn, Clock, Run : IN STD_LOGIC;
Done : BUFFER STD_LOGIC);
END proc;

ARCHITECTURE Behavior OF proc IS

. . . declare components

TYPE State_type IS (T0, T1, T2, T3);

SIGNAL Tstep_Q, Tstep_D: State_type;
...
CONSTANT mv : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
CONSTANT mvt : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
CONSTANT add : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
CONSTANT sub : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
CONSTANT Sel_R0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
...
CONSTANT Sel_R7 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0111";
CONSTANT Sel_G : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";
CONSTANT Sel_D : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1001";
CONSTANT Sel_D8 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1010" ;
-- Sel_D is immediate data , Sel_D8 is immediate data << 8
BEGIN

Figure 2: Skeleton VHDL code for the processor. (Part a)

3
III <= IR(15 DOWNTO 13);
IMM <= IR(12);
rX <= IR(11 DOWNTO 9);
rY <= IR(2 DOWNTO 0);
decX: dec3to8 PORT MAP (rX, Xreg);

statetable: PROCESS(Tstep_Q, Run, Done)

BEGIN
CASE Tstep_Q IS
WHEN T0 => -- data is loaded into IR in this time step
IF Run = ’0’ THEN Tstep_D <= T0;
ELSE Tstep_D <= T1; END IF;
WHEN T1 =>
...
END CASE;
END PROCESS;

controlsignals: PROCESS (Tstep_Q, III, IMM, Xreg, rX, rY)

BEGIN
Done <= ’0’; Ain <= ’0’; . . . default values for signals
CASE Tstep_Q IS
WHEN T0 => -- store DIN in IR as long as Tstep_Q = 0
IRin <= ’1’;
WHEN T1 => -- define signals in time step T1
CASE III IS
WHEN mv =>
IF IMM = ’0’ THEN Sel <= ’0’ & rY;
ELSE Sel <= Sel_D; END IF;
Rin <= Xreg;
Done <= ’1’;
WHEN mvt =>
...
END CASE;
WHEN T2 => -- define signals in time step T2
CASE III IS
...
END CASE;
WHEN T3 => -- define signals in time step T3
...
END CASE;
END PROCESS;

fsmflipflops: PROCESS (Clock, Resetn, Tstep_D)

BEGIN
IF (Resetn = ’0’) THEN
...
reg_0: regn PORT MAP (BusWires, Rin(0), Clock, R0);
reg_1: regn PORT MAP (BusWires, Rin(1), Clock, R1);
...
reg_7: regn PORT MAP (BusWires, Rin(7), Clock, R7);
. . . instantiate other registers and the adder/subtracter unit

Figure 2: Skeleton VHDL code for the processor. (Part b)

4
 -- define the internal bus
busmux: PROCESS (Sel, R0, R1, R2, R3, R4, R5, R6, R7, G, IR)
BEGIN
CASE Sel IS
WHEN Sel_R0 => BusWires <= R0;
WHEN Sel_R1 => BusWires <= R1;
...
WHEN Sel_R7 => BusWires <= R7;
WHEN Sel_G => BusWires <= G;
WHEN Sel_D => BusWires <= "0000000" & IR(8 DOWNTO 0);
WHEN Sel_D8 => BusWires <= IR(7 DOWNTO 0) & "00000000";
WHEN OTHERS => BusWires <= (OTHERS => ’-’);
END CASE;
END PROCESS;
END Behavior;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY dec3to8 IS
PORT ( W : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Y : OUT STD_LOGIC_VECTOR(0 TO 7));
END dec3to8;

ARCHITECTURE Behavior OF dec3to8 IS

BEGIN
PROCESS (W)
BEGIN
CASE W IS
WHEN "000" => Y <= "10000000";
WHEN "001" => Y <= "01000000";
WHEN "010" => Y <= "00100000";
...
WHEN "110" => Y <= "00000010";
WHEN "111" => Y <= "00000001";
WHEN OTHERS => Y <= "00000000";
END CASE;
END PROCESS;
END Behavior;

Figure 2: Skeleton VHDL code for the processor. (Part c)

2. Set up the required subfolder and files so that your VHDL code can be compiled and simulated using the
ModelSim Simulator to verify that your processor works properly. An example result produced by using
ModelSim for a correctly-designed circuit is given in Figure 3. It shows the value 0x101C being loaded
into IR from DIN at time 30 ns. This pattern represents the instruction mv r0,#28, where the immediate
value D = 28 (0x1C) is loaded into r0 on the clock edge at 50 ns. The simulation results then show the
instruction mvt r1,#0xFF00 at 70 ns, add r0,#0xFF at 110 ns, and sub r1,r0 at 190 ns.
You should perform a thorough simulation of your processor with the ModelSim simulator. A sample VHDL
testbench file, testbench.vht, execution script, testbench.tcl, and waveform file, wave.do are provided along
with this exercise.

5
 Figure 3: Simulation results for the processor.

Part II
In this part we will implement the circuit depicted in Figure 4, in which a memory unit and counter are connected
to the processor. The counter is used to read the contents of successive locations in the memory, and this data is
provided to the processor as a stream of instructions. To simplify the design and testing of this circuit we have
used separate clock signals, PClock and MClock, for the processor and memory. Do the following:
1. A Quartus project file is provided along with this part of the exercise. Use the Quartus software to open this
project, which is called part2.qpf.
2. A sample top-level VHDL file that instantiates the processor, memory unit, and counter is shown in Figure 5.
This code is provided in a file named part2.vhd; it is the top-level file for the Quartus project part2.qpf. The
code instantiates a memory unit called inst_mem. You have to create a VHDL file that represents this
memory unit by using the Quartus software, as described below.

Processor
Memory
Counter

n 16
addr data DIN
Done Done
Resetn

Run

MClock
PClock
Resetn
Run

Figure 4: Connecting the processor to a memory unit and counter.

6
ENTITY part2 IS
PORT ( KEY : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
END part2;

ARCHITECTURE Behavior OF part2 IS

. . . declare components and signals
BEGIN
Resetn <= SW(0);
MClock <= KEY(0);
PClock <= KEY(1);
Run <= SW(9);
U1: proc PORT MAP (DIN, Resetn, PClock, Run, Done);
LEDR(0) <= Done;
LEDR(9) <= Run;

U2: inst_mem PORT MAP (pc, MClock, DIN);

U3: count5 PORT MAP (Resetn, MClock, pc);
END Behavior;
...
ENTITY count5 IS
PORT ( Resetn, Clock : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
END count5;

ARCHITECTURE Behavior OF count5 IS

SIGNAL Count : STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
PROCESS (Clock, Resetn)
BEGIN
IF (Resetn = ’0’) THEN
Count <= "00000";
ELSIF (rising_edge(Clock)) THEN
Count <= Count + ’1’;
END IF;
END PROCESS;
Q <= Count;
END Behavior;

Figure 5: VHDL code for the top-level entity.

3. A diagram of the memory unit that you need to create is depicted in Figure 6. Since this memory unit has
only a read port, and no write port, it is called a synchronous read-only memory (synchronous ROM). Note
that the memory unit includes a register for synchronously loading addresses. This register is required due
to the design of the memory resources in the Intel FPGA chip.
Use the Quartus IP Catalog tool to create the memory unit, by clicking on Tools > IP Catalog in the
Quartus software. In the IP Catalog window choose the ROM: 1-PORT unit, which is found under the
Basic Functions > On Chip Memory category. Select VHDL as the type of output file to create, and
give the file the name inst_mem.vhd. Follow through the provided dialogue to create a memory that has
one 16-bit wide read data port and is 32 words deep. Figures 7 and 8 show the relevant pages and how to
properly configure the memory.

7
 5 5
Address
Clock 16
32 x 16 ROM DataOut

Figure 6: The 32 x 16 ROM with address register.

Figure 7: Specifying memory size.

To place processor instructions into the memory, you need to specify initial values that should be stored
in the memory when your circuit is programmed into the FPGA chip. This can be done by initializing
the memory using the contents of a memory initialization file (MIF). The appropriate screen is illustrated
in Figure 9. We have specified a file named inst_mem.mif, which then has to be created in the folder
that contains the Quartus project. Clicking Next two more times will advance to the Summary screen,
which lists the names of files that will be created for the memory IP. You should select only the VHDL file
inst_mem.vhd. Make sure that none of the other types of files are selected, and then click Finish.
An example of a memory initialization file is given in Figure 10. Note that comments (% . . . %) are included
in this file as a way of documenting the meaning of the provided instructions. Set the contents of your MIF
file such that it provides enough processor instructions to test your circuit.
4. The code in Figure 5, and the Quartus project, includes the necessary port names and pin location assign-
ments to implement the circuit on a DE-series board. The switch SW9 drives the processor’s Run input, SW0
is connected to Resetn, KEY0 to MClock, and KEY1 to PClock. The Run signal is displayed on LEDR0 and
Done is connected to LEDR9 .

8
Figure 8: Specifying which memory ports are registered.

Figure 9: Specifying a memory initialization file (MIF).

9
 5. Use the ModelSim Simulator to test your VHDL code. Ensure that instructions are read properly out of the
ROM and executed by the processor. An example of simulation results produced using ModelSim with the
MIF file from Figure 10 is shown in Figure 11. The corresponding ModelSim setup files are provided along
with this exercise.
6. Once your simulations show a properly-working circuit, you may wish to download it into a DE-series
board. The functionality of the circuit on the board can be tested by toggling the switches and observing the
LEDs. Since the circuit’s clock inputs are controlled by pushbutton switches, it is possible to step through
the execution of instructions and observe the behavior of the circuit.

DEPTH = 32;
WIDTH = 16;
ADDRESS_RADIX = HEX;
DATA_RADIX = BIN;
CONTENT
BEGIN
00 : 0001000000011100; % mv r0, #28 %
01 : 0011001011111111; % mvt r1, #0xFF00 %
02 : 0101001011111111; % add r1, #0xFF %
03 : 0110001000000000; % sub r1, r0 %
04 : 0101001000000001; % add r1, #1 %
05 : 0000000000000000;
. . . (some lines not shown)
1F : 0000000000000000;
END;

Figure 10: An example memory initialization file (MIF).

Figure 11: An example simulation output using the MIF in Figure 10.

Enhanced Processor
It is possible to enhance the capability of the processor so that the counter in Figure 4 is no longer needed, and
so that the processor has the ability to perform read and write operations using memory or other devices. These
enhancements involve adding new instructions to the processor, as well as other capabilities—they are discussed
in the next lab exercise.

10
 Laboratory Exercise 10
An Enhanced Processor

In Laboratory Exercise 1 we described a simple processor. In Part I of that exercise the processor itself was
designed, and in Part II the processor was connected to an external counter and a memory unit. This exercise de-
scribes subsequent parts of the processor design. The numbering of figures and tables in this exercise are continued
from those in Parts I and II of the preceding lab exercise.

In this exercise we will extend the capability of the processor so that the external counter is no longer needed, and
so that the processor can perform read and write operations using memory or other devices. A schematic of the
enhanced processor is given in Figure 12. In the figure registers r0 to r6 are the same as in Figure 1 of Lab 1, but
register r7 has been changed to a counter. This counter is used to provide the addresses in the memory from which
the processor’s instructions are read; in the preceding lab exercise, a counter external to the processor was used
for this purpose. We will refer to r7 as the processor’s program counter (pc), because this terminology is common
for real processors available in the industry. When the processor is reset, pc is set to address 0. At the start of
each instruction (in time step T0 ) the value of pc is used as an address to read an instruction from the memory.
The instruction returned from the memory is stored into the IR register and the pc is automatically incremented to
point to the next instruction.

The processor’s control unit increments pc by using the incr_pc signal, which is just an enable on this counter. It
is also possible to load an arbitrary address into pc by having the processor execute an instruction in which the
destination register is specified as pc. In this case the control unit uses r7in to perform a load of the counter. Thus,
the processor can execute instructions at any address in the memory, as opposed to only being able to execute
instructions that are stored at successive addresses. The current content of pc, which always has the address of the
next instruction to be executed, can be copied into another register if needed by using a mv instruction.

The enhanced processor will have four new instructions, which are listed in Table 3. The ld (load) instruction
reads data into register rX from the external memory address specified in register rY. Thus, the syntax [rY] means
that the content of register rY is used as an external address. The st (store) instruction writes the data contained in
register rX into the memory address found in rY. The and instruction is similar to the add and sub instructions that
were introduced in Lab 1. This instruction extends the adder/subtracter unit in the processor into an arithmetic
logic unit. Besides performing addition and subtraction, it has the ability to generate a bit-wise logical AND (&)
of the destination register rX with the second operand Op2. As discussed in Lab 1, the operand Op2 can be either
another register rY, or immediate data #D.

The b{cond} instruction is used to cause a processor branch, which means to change the program counter (pc) to
the address of a specific instruction. The cond part of the branch instruction is optional and represents a condition.
The instruction loads the constant #Label into pc only if the specified condition evaluates to true. An example of
a condition is eq, which stands for equal (to zero). The instruction beq #Label will load the constant Label
into pc if the last result produced by the arithmetic logic unit, which is stored in register G, was 0. The b{cond}
instruction is discussed in more detail in Part V of this exercise.

Operation Function performed

ld rX, [rY] rX ← [rY]
st rX, [rY] [rY] ← rX
and rX, Op2 rX ← rX & Op2
b{cond} #Label if (cond), pc ← #Label

Table 3: New instructions in the enhanced processor.

1
 16

16
incr_pc
16 16 16
E A in
Counter
r 0 in r 7 in L
r0 (r7) A

Clock

ADDR
AddSub A DDR
Adder/Subracter

16
G in
Multiplexers G
16

DOUT
DOUT
4 16
Buswires
Select
IR in

ADDR in
DIN IR DOUT in

Control FSM W_D

W
Run
Resetn
Done

Figure 12: An enhanced version of the processor.

Recall from Lab 1 that instructions are encoded using a 16-bit format. For instructions that specify Op2 as a register
the encoding is III0XXX000000YYY, and if Op2 is an immediate constant the format is III1XXXDDDDDDDDD.
You should use these same encodings for this exercise. Assume that III = 100 for the ld instruction, 101 for st,
110 for and, and 111 for b{cond}.

Figure 12 shows two registers in the processor that are used for data transfers. The ADDR register is used to
send addresses to an external device, such as a memory unit, and the DOUT register is used by the processor to
provide data that is to be stored outside of the processor. One use of the ADDR register is for reading, or fetching,
instructions from memory; when the processor wants to fetch an instruction, the content of pc is transferred across
the bus and loaded into ADDR. This address is provided to the memory.

In addition to fetching instructions, the processor can read data at any address by using the ADDR register. Both
data and instructions are read into the processor on the DIN input port. The processor can write data for storage
at an external address by placing this address into the ADDR register, placing the data to be stored into its DOUT
register, and asserting the output of the W (Write) flip-flop to 1.

Connecting the Processor to External Devices

Figure 13 illustrates how the enhanced processor can be connected to memory and other devices. The memory
unit in the figure is 16-bits wide and 256-words deep. A diagram of this memory is given in Figure 14. It supports
both read and write operations and therefore has both address and data inputs, as well as a write-enable input. As

2
depicted in Figure 14, the memory has a clock input that is used to store the address, data, and write enable inputs
into registers. This type of memory unit is called a synchronous static random access memory (SSRAM).

Figure 13 also includes a 9-bit output port (register) that can be used to store data from the processor. In the
figure this output port is connected to a set of LEDs, like the ones available on the DE1-SoC board. To allow
the processor to select either the memory unit or output port when performing a write operation, the circuit in-
cludes address decoding, which is done using NOR gates and AND gates. If the processor’s upper address lines
A15 A14 A13 A12 = 0000, then the memory unit can be written. Figure 13 shows n lower address lines connected
from the processor to the memory; since the memory has 256 words, then n = 8 and the memory’s address port is
driven by the processor address lines A7 . . . A0 . For addresses in which A15 A14 A13 A12 = 0001, the data written
by the processor is loaded into the output port connected to LEDs in Figure 13.

A15
A14
A13
Processor A12 Memory
16 4 n
ADDR address
16
DOUT data 16
q
DIN
W wren
4
A15
Resetn

Done A14
Run

A13
A12

Clock
E
Resetn 9
9
Run D Q LEDs

Figure 13: Connecting the enhanced processor to a memory unit and output register.

8
address 8

16
16 16 256 x 16 RAM q
data

wren
clock

Figure 14: The synchronous SRAM unit.

3
Part III
Figure 15 gives VHDL code for a top-level file that you can use for this part of the exercise. The input and output
ports for this entity are chosen so that it can be implemented on a DE1-SoC board. The VHDL code corresponds
to the circuit in Figure 13, plus an additional input port that is connected to switches SW8 . . . SW0 . This input port
can be read by the processor at addresses in which A15 . . . A12 = 0011. (Switch SW9 is not a part of the input
port, because it is dedicated for use as the processor’s Run input.) To support reading from both the SW input
port and the memory unit, the top-level circuit includes a multiplexer that feeds the processor’s DIN input. This
multiplexer is described by using an if-else statement inside the PROCESS block in Figure 15.

The code in Figure 15 is provided with this exercise, along with a few other source-code files: flipflop.v, inst_mem.v,
inst_mem.mif, and (part of) proc.v. The inst_mem.v source-code file was created by using the Quartus IP Catalog
to instantiate a RAM:1-PORT memory unit. It has a 16-bit wide read/write data port and is 256-words deep,
corresponding to Figure 14.

ENTITY part3 IS
PORT ( KEY : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
CLOCK_50 : IN STD_LOGIC;
LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) );
END part3;

ARCHITECTURE Behavior OF part3 IS

. . . declare components and signals
BEGIN
U3: proc PORT MAP (DIN, KEY(0), CLOCK_50, Run, DOUT, ADDR, W);

inst_mem_cs <= ’1’ WHEN (ADDR(15 DOWNTO 12) = "0000") ELSE ’0’;
LED_reg_cs <= ’1’ WHEN (ADDR(15 DOWNTO 12) = "0001") ELSE ’0’;
SW_cs <= ’1’ WHEN (ADDR(15 DOWNTO 12) = "0011") ELSE ’0’;

W_mem <= inst_mem_cs AND W;

U4: inst_mem PORT MAP (ADDR(7 DOWNTO 0), CLOCK_50, DOUT, W_mem, inst_mem_q);

multiplexer: PROCESS (inst_mem_cs, SW_cs, inst_mem_q, SW_reg)

BEGIN
IF inst_mem_cs = ’1’ THEN
DIN <= inst_mem_q;
ELSIF SW_cs = ’1’ THEN
DIN <= "0000000" & SW_reg;
ELSE
DIN <= (OTHERS => ’-’);
END IF;
END PROCESS;
W_LED <= LED_reg_cs AND W;
U5: regn GENERIC MAP (n => 9) PORT MAP (DOUT(8 DOWNTO 0), W_LED, CLOCK_50,
LED_reg);
LEDR(8 DOWNTO 0) <= LED_reg;
LEDR(9) <= Run;
High <= ’1’;
U6: regn GENERIC MAP (n => 9) PORT MAP (SW(8 DOWNTO 0), High, CLOCK_50,
SW_reg);
END Behavior;

Figure 15: VHDL code for the top-level file.

4
The VHDL code in the proc.v file implements register r7 as a program counter, as discussed above, and includes
a number of changes that are needed to support the new ld, st, and, and b{cond} instructions. In this part you
are to augment this VHDL code to complete the implementation of the ld and st instructions, as well as the and
instruction. You do not need to work on the b{cond} instruction for this part.

Perform the following:

1. Extend the code in proc.v so that the enhanced processor fully implements the ld, st, and and instructions.
Test your VHDL code by using the ModelSim simulator. Sample setup files for ModelSim, including a
testbench, are provided along with the other files for this exercise. The sample testbench first resets the
processor system and then asserts the Run switch, SW9 , to 1. A sample program to test your processor is
also provided, in a file called inst_mem.mif. This file represents the assembly-language program shown in
Figure 16, which tests the ld and st instructions by reading the values of the SW switches and writing these
values to the LEDs, in an endless loop. At the beginning of a simulation, ModelSim loads the contents of
the file inst_mem.mif into the inst_mem memory unit, so that the program can be executed by the processor.
Examine the signals inside your processor, as well as the external LEDR values, as the program executes
within the ModelSim simulation.
An assembler software tool, called sbasm.py, can be used with your processor. The Assembler is written in
Python and is available at https://github.com/profbrown/sbasm.git. To use this Assembler
you have to first install Python (version 3) on your computer. The Assembler includes a README file
that explains how to install and use it. The sbasm.py Assembler can generate machine code for all of the
processor’s instructions. The provided file inst_mem.mif was created by using sbasm.py to assemble the
program in Figure 16. As the figure indicates, you can define symbolic constants in your code by using the
.define directive, and you can use labels to refers to lines of code, such as MAIN. Comments are specified
in the code by using //. The assembler ignores anything on a line following //.

.define LED_ADDRESS 0x1000

.define SW_ADDRESS 0x3000

// Read SW switches and display on LEDs

mvt r3, #LED_ADDRESS // point to LED port
mvt r4, #SW_ADDRESS // point to SW port
MAIN: ld r0, [r4] // read SW values
st r0, [r3] // light up LEDs
mv pc, #MAIN

Figure 16: Assembly-language program that uses ld and st instructions.

An example result produced by using ModelSim for a correctly-designed circuit is given in Figure 17. It
shows the execution of the first four instructions in Figure 16.
2. Once your simulation results are correct, use the Quartus Prime software to implement your VHDL code on
a DE1-SoC board. A sample Quartus project file, part3.qpf, and Quartus settings file, part3.qsf, are provided
with the exercise. Compile your code using the Quartus software, and download the resulting circuit into
the DE1-SoC board. Toggle the SW switches and observe the LEDs to test your circuit.

5
 Figure 17: Simulation results for the processor.

Part IV
In this part you are to create a new VHDL entity that represents an output port called seg7. It will allow your
processor to write data to each of the six 7-segment displays on a DE1-SoC board. The seg7 entity will include
six write-only seven-bit registers, one for each display. Each register should directly drive the segment lights for
one seven-segment display, so that the processor can write characters onto the displays.

Perform the following:

1. A top-level file is provided for this part called part4.v. The top-level entity has output ports for connecting
to each of the 7-segment displays. Pin assignments for these ports, which are called HEX0[6:0], HEX1[6:0],
. . ., HEX6[6:0], are included in the Quartus settings file part4.qsf. For each display, segment 0 is on the top
of the display, and then segments 1 to 5 are assigned in a clockwise fashion, with segment 6 being in the
middle of the display.
The part4.v VHDL code includes address decoding for the new seg7 module, so that processor addresses in
which A15 A14 A13 A12 = 0010 select this module. The intent is that address 0x2000 should write to the
register that controls display HEX0, 0x2001 should select the register for HEX1, and so on. For example, if
your processor writes 0 to address 0x2000, then the seg7 module should turn off all of the segment-lights
in the HEX0 display; writing 0x7f should turn on all of the lights in this display.
2. You are to complete the partially-written VHDL code in the file seg7.v, so that it contains the required six
registers—one for each 7-segment display.

3. You can compile and test your VHDL code by using the ModelSim setup files that are provided for this part
of the exercise. An inst_mem.mif file is also provided that corresponds to the assembly-language program
shown in Figure 18. This program works as follows: it reads the SW switch port and lights up a seven-
segment display corresponding to the value read on SW2−0 . For example, if SW2−0 = 000, then the digit 0
is shown on HEX0. If SW2−0 = 001, then the digit 1 is displayed on HEX1, and so on, up to the digit 5
which would be shown on HEX5 if SW2−0 = 101.
4. Once your simulation results look correct, you should compile the provided Quartus project, and then down-
load and test the circuit on a DE1-SoC board.

6
.define HEX_ADDRESS 0x2000
.define SW_ADDRESS 0x3000

// This program shows the digits 543210 on the HEX displays. Each digit has to
// be selected by using the SW switches.
mv r5, pc // return address for subroutine
mv pc, #BLANK // call subroutine to blank the HEX displays
MAIN: mvt r2, #HEX_ADDRESS // point to HEX port
mv r3, #DATA // used to get 7-segment display pattern

mvt r4, #SW_ADDRESS // point to SW port

ld r0, [r4] // read switches
and r0, #0x7 // use only SW2-0
add r2, r0 // point to correct HEX display
add r3, r0 // point to correct 7-segment pattern

ld r0, [r3] // load the 7-segment pattern

st r0, [r2] // light up HEX display

mv pc, #MAIN

// subroutine BLANK
// This subroutine clears all of the HEX displays
// input: none
// returns: nothing
// changes: r0 and r1. Register r5 provides the return address
BLANK: mv r0, #0 // used for clearing
mvt r1, #HEX_ADDRESS // point to HEX displays
st r0, [r1] // clear HEX0
add r1, #1
st r0, [r1] // clear HEX1
add r1, #1
st r0, [r1] // clear HEX2
add r1, #1
st r0, [r1] // clear HEX3
add r1, #1
st r0, [r1] // clear HEX4
add r1, #1
st r0, [r1] // clear HEX5

add r5, #1
mv pc, r5 // return from subroutine

DATA: .word 0b00111111 // ’0’

.word 0b00000110 // ’1’
.word 0b01011011 // ’2’
.word 0b01001111 // ’3’
.word 0b01100110 // ’4’
.word 0b01101101 // ’5’

Figure 18: Assembly-language program that tests the seven-segment displays.

7
Part V
In this part you are to enhance your processor so that it implements the b{cond} instruction. The conditions
supported by the processor are called eq, ne, cc, and cs, which means that the variations of the branch instruction
are b, beq, bne, bcc, and bcs. The b instruction always branches. For example, b #MAIN loads the address MAIN
into the program counter. The meanings of the conditional versions are explained below.

The instruction beq means branch if equal (to zero). This instruction performs a branch operation (i.e., loads
the provided #LABEL into the program counter) if the most recent result of an instruction executed using the
arithmetic logic unit (ALU), which is stored in register G, was 0. Similarly, bne means branch if not equal (to
zero). It performs a branch only if the contents of G are not equal to 0. The instruction bcc stands for branch
if carry clear. It branches if the last add/subtract operation did not produce a carry-out. The opposite branch
condition, bcs, branch if carry set, performs a branch if the most recent add/sub generated a carry-out. To support
the conditional branch instructions, you should create two condition-code flags in your processor. One flag, z,
should have the value 1 when the ALU generates a result of zero; otherwise z should be 0. The other flag, c,
should be 1 when the adder/subtracter in the ALU produces a carry-out; otherwise c should be 0. Thus, c should
be 1 when an add instruction generates a carry-out, or when a sub operation requires a borrow for the most-
significant bit. Your FSM controller should examine these flags in the appropriate clock cycles when executing
the b{cond} instructions.

The branch instructions are encoded using the format III1XXXDDDDDDDDD, where DDDDDDDDD is the branch
address and XXX is the branch condition. Assume that conditions are encoded as none (always branch) = 000,
eq = 001, ne = 010, cc = 011, and cs = 100.

Perform the following:

1. Enhance your processor so that it implements the condition-code flags z and c, and supports the b{cond}
instruction. To help with testing and debugging of your processor, setup files for ModelSim are provided,
including a testbench. It simulates your processor instantiated in the top-level file part5.v, which is the
same as the one from Part IV. An example inst_mem.mif file is also provided, which corresponds to the
program in Figure 19. This program is quite short, which makes it suitable for visual inspection of the
waveforms produced by a ModelSim simulation. The program uses a sequence of instructions that test
the various conditional branches. If the program reaches the line of code labelled DEAD, then at least one
instruction has not worked properly. An example of ModelSim output for a correctly-working processor
is given in Figure 20. It shows the processor executing instructions near the end of the code in Figure 19.
The instruction that is completed at simulation time 1030 ns is add r0, #1 (0x5001). As shown in the
figure, this instruction causes the carry flag, c, to become 1. The next instruction loaded into IR, at time
1090 ns, is bcs #0xC (0xF80C). Finally, the instruction loaded at 1170 ns is b #0 (0xF000).

MAIN: mv r0, #2
LOOP: sub r0, #1 // subtract to test bne
bne #LOOP
beq #T1 // r0 == 0, test beq
mv pc, #DEAD
T1: mvt r0, #0xFF00
add r0, #0xFF // r0 = 0xFFFF
bcc #T2 // carry = 0, test bcc
mv pc, #DEAD
T2: add r0, #1
bcs #T3 // carry = 1, test bcs
mv pc, #DEAD
T3: b #MAIN
DEAD: mv pc, #DEAD

Figure 19: Assembly-language program that uses various branches.

8
 Figure 20: Simulation results for the processor.

2. Once your ModelSim simulation indicates a correctly-functioning processor you should implement it on a
DE1-SoC board. A Quartus project file part5.qpf and settings file part5.qsf are provided for this purpose.
To test your processor, you can use the assembly-language program displayed in Figure 21. It provides code
that tests for the correct operation of instructions supported by the enhanced processor. If all of the tests pass,
then the program shows the word PASSEd on the seven-segment displays. It also shows a binary value on
the LEDs that represents the number of successful tests performed. If any test fails, then the program shows
the word FAILEd on the seven-segment displays and places on the LEDs the address in the memory of the
instruction that caused the failure. Assemble the program, which is provided in a file called sitbooboosit.s,
by using the sbasm.py assembler.
Use the output produced by sbasm.py to overwrite the file inst_mem.mif that you used in the beginning
of this part of the exercise to simulate your processor system with ModelSim. Open the Quartus software,
compile the part5 project, and download it onto your DE1-SoC board. If the Run signal is asserted, then your
processor should execute the sitbooboosit program. If a failure is encountered, then the offending instruction
can be identified by cross-referencing the LED pattern with the addresses in the file inst_mem.mif.

.define LED_ADDRESS 0x1000

.define HEX_ADDRESS 0x2000
mv r2, #0 // used to count number of successful tests
mv r6, #T1 // save address of next test
sub r0, r0 // set the z flag
T1: bne #FAIL // test bne; should not take the branch!
mv r6, #C1 // save address of next test
C1: beq #C2 // test beq; should take the branch
b #FAIL // Argh!
C2: add r2, #2 // count the last two successful tests

Figure 21: Assembly-language program that tests various instructions. (Part a)

9
 mv r6, #T2 // save address of next test
T2: bne #S1 // test bne; should take the branch!
mv pc, #FAIL
S1: mv r6, #C3 // save address of next test
C3: beq #FAIL // test beq; should not take the branch
add r2, #2 // count the last two successful tests

mv r6, #T3 // save address of next test

mv r3, #ALLONES
ld r3, [r3]
add r3, #1 // set the c flag

T3: bcc #FAIL // test bcc; should not take the branch!
mv r6, #C4 // save address of next test
C4: bcs #C5 // test bcs; should take the branch
b #FAIL // Argh!
C5: add r2, #2 // count the last two successful tests

mv r6, #T4
mv r3, #0
add r3, r3 // clear carry flag

T4: bcc #S2 // test bcc; should take the branch!

mv pc, #FAIL
S2: mv r6, #C6 // save address of next test
C6: bcs #FAIL // test bcs; should bot take the branch!
add r2, #2 // count the last two successes

// finally, test ld and st from/to memory

mv r6, #T5 // save address of next test
mv r4, #_LDTEST
ld r4, [r4]
mv r3, #0x1A5
sub r3, r4
T5: bne #FAIL // should not take the branch!
add r2, #1 // increment success count

mv r6, #T6 // save address of next test

mv r3, #0x1A5
mv r4, #_STTEST
st r3, [r4]
ld r4, [r4]
sub r3, r4
T6: bne #FAIL // should not take the branch!
add r2, #1 // increment success count

mv pc, #PASS
// Loop over the six HEX displays
FAIL: mvt r3, #LED_ADDRESS
st r6, [r3] // show address of failed test on LEDs
mv r5, #_FAIL
mv pc, #PRINT
PASS: mvt r3, #LED_ADDRESS
st r2, [r3] // show success count on LEDs
mv r5, #_PASS

Figure 21: Assembly-language program that tests various instructions. (Part b)

10
 PRINT: mvt r4, #HEX_ADDRESS // address of HEX0
// We would normally use a loop counting down from 6
// with bne to display the six letters. But in this
// testing code we can’t assume that bne even works!

ld r3, [r5] // get letter

st r3, [r4] // send to HEX display
add r5, #1 // ++increment character pointer
add r4, #1 // point to next HEX display
ld r3, [r5] // get letter
st r3, [r4] // send to HEX display
add r5, #1 // ++increment character pointer
add r4, #1 // point to next HEX display
ld r3, [r5] // get letter
st r3, [r4] // send to HEX display
add r5, #1 // ++increment character pointer
add r4, #1 // point to next HEX display
ld r3, [r5] // get letter
st r3, [r4] // send to HEX display
add r5, #1 // ++increment character pointer
add r4, #1 // point to next HEX display
ld r3, [r5] // get letter
st r3, [r4] // send to HEX display
add r5, #1 // ++increment character pointer
add r4, #1 // point to next HEX display
ld r3, [r5] // get letter
st r3, [r4] // send to HEX display
add r5, #1 // ++increment character pointer
add r4, #1 // point to next HEX display

HERE: mv pc, #HERE

_PASS: .word 0b0000000001011110 // d

.word 0b0000000001111001 // E
.word 0b0000000001101101 // S
.word 0b0000000001101101 // S
.word 0b0000000001110111 // A
.word 0b0000000001110011 // P

_FAIL: .word 0b0000000001011110 // d

.word 0b0000000001111001 // E
.word 0b0000000000111000 // L
.word 0b0000000000110000 // I
.word 0b0000000001110111 // A
.word 0b0000000001110001 // F

ALLONES: .word 0xFFFF

_LDTEST: .word 0x1A5
_STTEST: .word 0x15A

Figure 21: Assembly-language program that tests various instructions. (Part c)

Part VI
Write an assembly-language program that displays a binary counter on the LED port. Initialize the counter to 0,
and then increment the counter by one in an endless loop. You should be able to control the speed at which the
counter is incremented by using nested delay loops, along with the SW switches. If the SW switches are set to

11
their maximum value, 0b111111111, then the delay loops should cause the counter to increment slowly enough
so that each change in the counter can be visually observed on the LEDs. Lowering the value of the SW switches
should make the counter increment more quickly up to some maximum speed.

You can assemble your program by using the sbasm.py assembler, and then run it on your processor system from
Part V. To do this, use the output produced by sbasm.py to overwrite the file inst_mem.mif in the folder that holds
your Quartus project for Part V. To make use of the new inst_mem.mif file you do not need to completely recom-
pile your VHDL code from Part V. Instead, execute the Quartus command Processing > Update Memory
Initialization File, to include the new inst_mem.mif file in your Quartus project. Next, select the Quar-
tus command Processing > Start > Start Assembler to produce a new programming bitstream for
your DE1-SoC board. Finally, use the Quartus Programmer to download the new bitstream onto your board. If the
Run signal is asserted, your processor should execute the new program.

Part VII
Augment your assembly-language program from Part VI so that counter values are displayed on the seven-segment
display port rather than on the LED port. You should display the counter values as decimal numbers from 0 to
65535. The speed of counting should be controllable using the SW switches in the same way as for Part VI. As
part of your solution you may want to make use of the code shown in Figure 22. This code provides a subroutine
that divides the number in register r0 by 10, returning the quotient in r1 and the remainder in r0. Dividing by 10
is a useful operation when performing binary-to-decimal conversion. The DIV10 subroutine assumes that r6 is
set up to be used as a stack pointer. Register r2 is saved on the stack at the beginning of the subroutine, and then
restored before returning. This is done so that r2 is not unnecessarily changed by the subroutine. A skeleton of
the required code for this part is shown in Figure 23.

// subroutine DIV10
// This subroutine divides the number in r0 by 10
// The algorithm subtracts 10 from r0 until r0 < 10, and keeps count in r1
// This subroutine assumes that r6 can be used as a stack pointer
// input: r0
// returns: quotient Q in r1, remainder R in r0
DIV10:
sub r6, #1 // save registers that are modified
st r2, [r6] // save on the stack

mv r1, #0 // init Q
DLOOP: mv r2, #9 // check if r0 is < 10 yet
sub r2, r0
bcc #RETDIV // if so, then return

INC: add r1, #1 // but if not, then increment Q

sub r0, #10 // r0 -= 10
b #DLOOP // continue loop
RETDIV:
ld r2, [r6] // restore from the stack
add r6, #1
add r5, #1 // adjust the return address
mv pc, r5 // return results

Figure 22: A subroutine that divides by 10

As described previously, assemble your program with sbasm.py, update your MIF file in the Quartus software,
generate a new bitstream file by using the Quartus Assembler, and then download the new bitstream onto your
DE1-SoC board to run your new program.

12
.define HEX_ADDRESS 0x2000
.define SW_ADDRESS 0x3000
.define STACK 256 // bottom of memory

// This program shows a decimal counter on the HEX displays

mv r6, #STACK // stack pointer
mv r5, pc // return address for subroutine
mv pc, #BLANK // call subroutine to blank the HEX displays
MAIN: mv r0, #0 // initialize counter
LOOP: mvt r1, #HEX_ADDRESS // point to HEX port
...
... use a loop to extract and display each digit
...

// Delay loop for controlling the rate at which the HEX displays are updated
...
... read from SW switches, and use a nested delay loop
...

add r0, #1 // counter += 1

bcc #LOOP // continue until counter overflows

mv r5, pc // return address for subroutine

mv pc, #BLANK // call subroutine to blank the HEX displays
b #MAIN

// subroutine DIV
...
... code not shown here
...
add r5, #1 // adjust the return address
mv pc, r5 // return results

// subroutine BLANK
...
... code not shown here
...
add r5, #1
mv pc, r5 // return from subroutine

DATA: .word 0b00111111 // ’0’

....

Figure 23: Skeleton code for displaying decimal digits.

13
 Laboratory Exercise 11
Implementing Algorithms in Hardware

This is an exercise in using algorithmic state machine charts to implement algorithms as hardware circuits.

Background
Algorithmic State Machine (ASM) charts are a design tool that allow the specification of digital systems in a form
similar to a flow chart. An example of an ASM chart is shown in Figure 1. It represents a circuit that counts
the number of bits set to 1 in an n-bit input A (A = an−1 an−2 . . .a1 a0 ). The rectangular boxes in this diagram
represent the states of the digital system, and actions specified inside of a state box occur on each active clock
edge in this state. Transitions between states are specified by arrows. The diamonds in the ASM chart represent
conditional tests, and the ovals represent actions taken only if the corresponding conditions are either true (on an
arrow labeled 1) or false (on an arrow labeled 0).

Reset

S1

Load A result = 0

0 0
s
1
s
1

S2 S3

right-shift A Done

1
result++ A==0

0
a0

Figure 1: ASM chart for a bit counting circuit.

1
In this ASM chart, state S1 is the initial state. In this state the result is initialized to 0, and data is loaded into
a register A, until a start signal, s, is asserted. The ASM chart then transitions to state S2, where it increments
the result to count the number of 1’s in register A. Since state S2 specifies a shifting operation, then A should be
implemented as a shift register. Also, since the result is incremented, then this variable should be implemented as
a counter. When register A contains 0 the ASM chart transitions to state S3, where it sets an output Done = 1 and
waits for the signal s to be deasserted.

A key distinction between ASM charts and flow charts is a concept known as implied timing. The implied timing
specifies that all actions associated with a given state take place only when the system is in that state when an
active clock edge occurs. For example, when the system is in state S1 and the start signal s becomes 1, then the
next active clock edge performs the following actions: initializes result to 0, and transitions to state S2. The action
right-shift A does not happen yet, because the system is not yet in state S2. For each active clock cycle in state
S2, the actions highlighted in Figure 1 take place, as follows: increment result if bit a0 = 1, change to state S3 if
A = 0 (or else remain in state S2), and shift A to the right.

The implementation of the bit counting circuit includes the counter to store the result and the shift register A, as
well as a finite state machine. The FSM is often referred to as the control circuit, and the other components as the
datapath circuit.

Part I
Write VHDL code to implement the bit-counting circuit using the ASM chart shown in Figure 1 on a DE-series
board. Include in your VHDL code the datapath components needed, and make an FSM for the control circuit.
The inputs to your circuit should consist of an 8-bit input connected to slide switches SW7−0 , a synchronous reset
connected to KEY0 , and a start signal (s) connected to switch SW9 . Use the 50 MHz clock signal provided on the
board as the clock input for your circuit. Be sure to synchronize the s signal to the clock. Display the number of 1s
counted in the input data on the 7-segment display HEX0, and signal that the algorithm is finished by lighting up
LEDR9 .

Part II
We wish to implement a binary search algorithm, which searches through an array to locate an 8-bit value A
specified via switches SW7−0 . A block diagram for the circuit is shown in Figure 2.

A7-0 Start Reset

Control
32 x 8
Memory n

Address
Data_out
Datapath

L4-0 Found

Figure 2: A block diagram for a circuit that performs a binary search.

2
The binary search algorithm works on a sorted array. Rather than comparing each value in the array to the one
being sought, we first look at the middle element and compare the sought value to the middle element. If the
middle element has a greater value, then we know that the element we seek must be in the first half of the array.
Otherwise, the value we seek must be in the other half of the array. By applying this approach recursively, we can
locate the sought element in only a few steps.

In this circuit, the array is stored in a memory module that is implemented inside the FPGA chip. A diagram of
the memory module that we need to create is depicted in Figure 3. This memory module has one read port and
one write port, and is called a synchronous random-access memory (synchronous RAM). Note that the memory
module includes registers for synchronously loading addresses, input data, and the Write input. These registers
are required due to the design of the memory resources in the Intel R FPGA chip. Use the Quartus R IP Catalog
tool to create the memory module, by clicking on Tools > IP Catalog. In the IP Catalog window choose the
RAM: 1-PORT module, which is found under the Basic Functions > On Chip Memory category. Select VHDL
as the type of output file to create, and give the file the name memory_block.vhd.

Follow through the provided sequence of dialogs to create a memory that is eight-bits wide and 32 words deep.
Figures 4 and 5 show the relevant pages and how to properly configure the memory.

5 5
Address

8 8
DataIn 32 x 8 RAM 8
DataOut

Write
Clock

Figure 3: The 32 x 8 RAM with address register.

To place data into the memory, you need to specify initial values that should be stored in the memory once your
circuit has been programmed into the FPGA chip. This can be done by initializing the memory using the contents
of a memory initialization file (MIF). The appropriate screen is illustrated in Figure 6. We have specified a file
named my_array.mif, which then has to be created in the folder that contains the Quartus project. An example of
a memory initialization file is given in Figure 7. Set the contents of your MIF file such that it contains a sorted
collection of integers.

3
 Figure 4: Specifying memory size.

Figure 5: Specifying which memory ports are registered.

4
 Figure 6: Specifying a memory initialization file (MIF).

DEPTH = 32;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = BIN;
CONTENT
BEGIN

00 : 01;
01 : 02;
02 : 03
03 : 05;
04 : 06;
05 : 06;
06 : 07;
. . . (some lines not shown)
1E : 1F;
1F : 20;

END;

Figure 7: An example memory initialization file (MIF).

Your circuit should produce a 5-bit output L, which specifies the address in the memory where the number A is
located. In addition, a signal Found should be set high to indicate that the number A was found in the memory,
and set low otherwise.

5
Perform the following steps:
1. Create an ASM chart for the binary search algorithm. Keep in mind that the memory has registers on its
input ports. Assume that the array has a fixed size of 32 elements.
2. Implement the FSM and the datapath for your circuit.

3. Connect your FSM and datapath to the memory block as indicated in Figure 2.
4. Include in your project the necessary pin assignments to implement your circuit on your DE-series board.
Use switch SW9 to drive the Start input, use SW7...0 to specify the value A, use KEY0 for Resetn, and use
the board’s 50 MHz clock signal as the Clock input (be sure to synchronize the Start input to the clock).
Display the address of the data A, if found, on 7-segment displays HEX1 and HEX0, as a hexadecimal
number. Finally, use LEDR9 for the Found signal.
5. Create a file called my_array.mif and fill it with an ordered set of 32 eight-bit integer numbers.
6. Compile your design, and then download and test it.

6
Copyright c Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Avalon, Cyclone, En-
pirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in
the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products
and services at any time without notice. Intel assumes no responsibility or liability arising out of the application
or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
Intel customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

7
 Laboratory Exercise 12
Basic Digital Signal Processing

This is an exercise in using the audio coder/decoder (CODEC) on the Intel R DE1-SoC or DE2-115 board. The
exercise involves connecting a microphone to the audio CODEC to provide input sound, altering the received
sound by filtering out noise, and then playing the resulting sound through speakers/headphones. In addition to a
DE-series board, a microphone and speakers or headphones are required.

Background
Sounds, such as speech and music, are signals that change over time. The amplitude of a signal determines the
volume at which we hear it. The way the signal changes over time determines the type of sounds we hear. For
example, an ’ah’ sound is represented by a waveform shown in Figure 1.

Figure 1: A waveform for an ’ah’ sound.

The waveform is an analog signal, which can be stored in a digital form by using a relatively small number of
samples that represent the analog values at certain points in time. The process of producing such digital signals is
called sampling.

Figure 2: A sampled waveform for an ’ah’ sound.

1
The points in Figure 2 provide a sampled waveform. All points are spaced equally in time and they trace the
original waveform.

The Intel DE1-SoC, and DE2-115 board are equipped with an audio CODEC capable of sampling sound from a
microphone and providing it as input to a circuit. By default, the CODEC provides 48000 samples per second,
which is sufficient to accurately represent audible sounds.

This exercise involves the design of several circuits that take input from a microphone through the CODEC, record
and process this sound data, and then play it back through speakers. To simplify the task, a simple system that can
record and playback sounds on your DE-series board is provided as a "starter kit". The system, shown in Figure 3,
comprises a Clock Generator, an Audio CODEC Interface, and an Audio/Video Configuration modules. This
interface is a simplified version of the Intel University Program Audio IP Core that is provided on Intel’s FPGA
University Program website.

I2C_SCLK
Audio/Video
I2C_SDAT Configuration

CLOCK_50
read_ready
write_ready
AUD_BCLK
read
AUD_ADCLRCK Audio write
AUD_DACLRCK CODEC readdata_left Your Circuit
AUD_ADCDAT Interface readdata_right
AUD_DACDAT writedata_left
writedata_right

AUD_XCK

CLOCK2_50 Clock Generator

Figure 3: Audio System for this exercise.

The left-hand side of Figure 3 shows the inputs and outputs of the system. These I/O ports supply the clock inputs,
as well as connect the Audio CODEC and Audio/Video Configuration modules to the corresponding peripheral
devices on the Intel DE1-SoC and DE2-115 board. In the middle of the figure, a set of signals to and from the
Audio CODEC Interface module is shown. These signals allow the circuit depicted on the right-hand side to
record sounds from a microphone and play them back via speakers.

The system works as follows. Upon reset, the Audio/Video Configuration begins an autoinitialization sequence.
The sequence sets up the audio device to sample microphone input at a rate of 48kHz and produce output through
the speakers at the same rate. Once the autoinitialization is complete, the Audio CODEC begins reading the
data from the microphone once every 48000th of a second, and sends it to the Audio CODEC Interface core
in the system. Once received, the sample is stored in a 128-element buffer in the Audio CODEC Interface
core. The first element of the buffer is always visible on the readdata_left and readdata_right outputs when the
read_ready signal is asserted. The next element can be read by asserting the read signal, which ejects the current
sample and a new one appears one or more clock cycles later, if the read_ready signal is asserted.

To output sound through the speakers a similar procedure is followed. Your circuit should observe the write_ready
signal, and if asserted write a sample to the Audio CODEC by providing it at the writedata_left and write-

2
data_right inputs and asserting the write signal. This operation stores a sample in a buffer inside of the Audio
CODEC Interface, which will then send the sample to the speakers at the right time.

A starter kit that contains this design is provided as part of this exercise.

Part I
In this part of the exercise, you are to make a simple modification to the provided starter kit circuit to pass the
input from the microphone to the speakers. You should take care to read data from and write data to the Audio
CODEC Interface only when its ready signals are asserted.

Compile your circuit and download it onto an Intel DE1-SoC or DE2-115 board. Connect microphone and speak-
ers to the Mic and Line Out ports of the board and speak to the microphone to hear your voice through the
speakers.

Part II
In this part, you will learn a basic signal processing technique known as filtering. Filtering is a process of adjusting
a signal - for example, removing noise. Noise in a sound waveform is represented by small, but frequent changes
to the amplitude of the signal. A simple logic circuit that achieves the task of noise-filtering is an averaging Finite
Impulse Response (FIR) filter. The schematic diagram of the filter is shown in Figure 4.

Data in DQ DQ DQ DQ DQ DQ DQ
24

÷8 ÷8 ÷8 ÷8 ÷8 ÷8 ÷8 ÷8

+ + + + + + + Data out
24

Figure 4: A simple averaging FIR filter.

An averaging filter, like the one shown in Figure 4, removes noise from a sound by averaging the values of adjacent
samples. In this particular case, it removes small deviations in sound by looking at changes in the adjacent 8
samples. When using low-quality microphones, this filter should remove the noise produced when you speak to
the microphone, making your voice sound clearer.

You are to implement the circuit shown in Figure 4 to process the sound from the microphone, and output the
filtered sound through the speakers. Do you notice any difference between the quality of sound in this part as
compared to Part I?

NOTE:
It is possible to obtain high-quality microphones with noise-canceling capabilities. In such circumstances, you are
unlikely to hear any effect from using this filter. If this is the case, we suggest introducing some noise into the
sound by adding the output of the circuit in Figure 5 to the sample produced by the Audio CODEC.
The circuit is a simple counter, whose value should be interpreted as a signed value. The circuit should be clocked
by a 50MHz clock, and the enable signal should be driven high when the Audio CODEC module can both produce
and accept a new sample.

3
 LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;

ENTITY noise_generator IS
PORT ( CLOCK_50, read_s : IN STD_LOGIC;
noise : OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END noise_generator;

ARCHITECTURE Behavior OF upcount IS

SIGNAL counter : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL Q : STD_LOGIC_VECTOR(9 DOWNTO 0);

BEGIN
PROCESS (Clock_50)
BEGIN
IF (Clock’EVENT AND Clock = ’1’) THEN
IF (read_s = ’1’) THEN
counter <= counter + 1;
END IF;
END IF;
END PROCESS;
Q <= (OTHERS => counter(2));
noise <= Q&counter&"00000000000";
END Behavior;

Figure 5: Circuit to generate some noise.

To hear the effect of the noise generator, add the values produced by the circuit to each sample of sound from the
Audio CODEC in the circuit in Part I.

Part III
The implementation of the averaging filter in Part II may have been effective in removing some of the noise, and
all of the noise produced by the noise generator. However, if your microphone is of low-quality or you increase
the width of the counter in the noise generator, the filter in Part II would be insufficient to remove the noise. The
reason for this is because the filter in Part II only looked at a very small time frame over which the sound waveform
was changing. This can be remedied by making the filter larger, taking an average of more samples.

In this part, you are to experiment with the size of the filter to determine the number of samples over which
you have to average sound input to remove background noise. To do this more effectively, use the design of an
averaging FIR filter shown in Figure 6.

4
 Data in ÷N Datain Dataout
24
FIFO of size N

Accumulator
QD
*(-1)

+ + Data out
24

Figure 6: N-sample averaging FIR filter.

To compute the average of the last N samples, this circuit first divides the input sample by N . Then, the resulting
value is stored it in a First-In First-out (FIFO) buffer of length N and added to the accumulator. To make sure the
value in the accumulator is the average of the last N samples, the circuit subtracts the value that comes out of the
FIFO, which represents the (n + 1)th sample.

Implement, compile and download the circuit onto an Intel DE1-SoC, or DE2-115 board. Connect microphone
and speakers to the Mic and Line Out ports of the board and speak to the microphone to hear your voice through
the speakers. Experiment with different values of N to see what happens to your voice and any background noise,
remembering to divide the samples by appropriate value. We recommend experimenting with values of N that are
a power of 2, to make the division easier.

If you have a portable music player, with a connector such that you can supply input to your circuit through the
Mic port, try experimenting with different sizes of the filter and its effect on the song you play.

5
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