MP5416

2.8V-5.5V, Power Management IC with

Four 2A/2.5A/4A/4.5A Buck Converters, 5 LDOs,
And Flexible System Settings via I2C and OTP
The Future of Analog IC Technology

DESCRIPTION FEATURES
The MP5416 is a complete power management  Four High-Efficiency Step-Down Converters
solution that integrates four high-efficiency, o Buck1: 4.5ADC/DC Converter
step-down, DC/DC converters, five low-dropout o Buck2: 2.5A DC/DC Converter
regulators, and a flexible logic interface. o Buck3: 4A DC/DC Converter
A constant-on-time (COT) control DC/DC o Buck4: 2A DC/DC Converter
converter provides fast transient response. The o 2.8V to 5.5V Operating Input Range
1.5MHz default fixed switching frequency during o Adjustable Switching Frequency
continuous conduction mode (CCM) reduces o Programmable Forced PWM, Auto
the external inductor and capacitor values PFM/PWM Mode
greatly. Full protection features include under- o Hiccup Over-Current Protection (OCP)
voltage lockout (UVLO), over-current protection  Five Low-Dropout Regulators
(OCP), and thermal shutdown. o One RTC Dedicate LDO
o Four Low Noise LDOs
The output voltage is adjustable through the I2C o Two Separate Input Power Supplies
bus or pre-set by the one-time programmable o 100mV Dropout at 300mA Load
(OTP) function. In order to determine the most  System
optimal output voltage configurations supported o I2C Bus and OTP
by this device, refer to application note AN139. o Power-On/-Off Button
The power on/off sequence is also o Power-On Reset Output
programmable by the OTP or can be controlled o Flexible Power-On/-Off Sequence via
through the I2C bus online. OTP
The MP5416 requires a minimal number of o Flexible DC/DC, LDO On/Off via OTP
external components and is available in a o ±4kVHBM and ±2kV CDM ESD Rating
space-saving, 28-pin QFN (4mmx4mm) For All Pins
package.
APPLICATIONS
By using I2C or OTP, users can use the  Cable Modems, Set-Top Boxes
MP5416 to program the buck and LDO output  Televisions
voltages, MODE, current limit of buck1 and
 MID, Tablets
buck 3, and the enable function of all the bucks
 POS Machines
and LDO (ENBUCK/LDO).
 SSD
When using just I2C and no OTP, the MP5416  IP Cameras
allows users to program current limit of buck 2 All MPS parts are lead-free, halogen-free, and adhere to the RoHS
and 4, slew rate (DVS Slew rate), Discharge directive. For MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
(DISCHG), system enable (SYSEN), and trademarks of Monolithic Power Systems, Inc.
software reset (SFRST). Status and ID2
registers can also be read via I2C.
Some other features, such as AUTOON,
Frequency, PWR on delay, RST delay,
pushbutton time, LDORTC output voltage, OTP
version, and I2C slave address can only be
programmed via OTP.

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 MP5416 – 5V, DIGITAL PMIC WITH 9 OUTPUTS

TYPICAL APPLICATION

OTP-EFUSE SELECTED TABLE BY DEFAULT (MP5416-0000)

OTP Items Buck1 Buck2 Buck3 Buck4 LDORTC LDO2 LDO3 LDO4 LDO5

Output Voltage 1.2V 1.5V 1.8V 3.3V 3.2V 3.3V 3.3V 1.1V 1.8V
Initial On/Off On On On On On On Off On On
Mode FPWM PFM FPWM FPWM N/A
Power-On Delay/Time Slot # 2ms/1 4ms/2 4ms/2 0ms/0 Always on 4ms/2 6ms/3 2ms/1 4ms/2
Automatic Turn-On Yes
Switching Frequency 1.5MHz
Push-Button Timer 2 seconds
RSTO Delay 10ms
Buck 1 Peak Current Limit 6.8A
Buck 3 Peak Current Limit 5.6A
2
I C Slave Address 0x69
OTP Version 0000

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 MP54
416 – 5V, DIG
GITAL PMIC
C WITH 9 OUTPUTS

ORDERING
G INFORM
MATION
Pa
art Number* Package Top Marking
g
MP5416
6GR-xxxx** QF
FN-28 (4mmx4 4mm) See Below
MP5416
6GR-0000 QF
FN-28 (4mmx4 4mm) See Below
EVKT-5
5416 Evaluation Kit
K
* For Tape & Reel, add su
uffix –Z (e.g. MP5416GR-X
M XXXX–Z)
** “xxxx” is the
t configurattion code iden
ntifier for the register settin
ng stored in th
he OTP.
The default number
n is “00
000”. Each “x”” can be a hexxadecimal vaalue between 0 and F. Plea
ase work with an MPS
FAE to creeate this uniquue number, evven if orderingg the “0000” code.
c MP5416GR-0000 is the default version.

TOP MARKIN
NG

MPS: MPS prefix

Y: Year code
WW: We eek code
MP5416 6: Product cod
de
LLLLLL: Lot number

EVA
ALUATIO
ON KIT EV
VKT-5416
6
E
EVKT-5416 K contents: (IItems below can
Kit c be ordere
ed separately)).
# Part Number
P Item
m Quantity
1 E
EV5416-R-00DD MP5 5416GR-CCC CC evaluation n board 1
Inclu
udes one USB B to I2C donggle, one USB cable, and one
2 E
EVKT-USBI2C
C-02 1
ribbon cable
3 M
MP5416GR-CCCC MP5 5416 IC whichh can be used d for OTP pro
ogramming 2
USBB flash drive that
t stores the
e GUI installa
ation file and
4 Tdrive-5416 1
suppplemental doccuments
Orde
er direct fro
om Monolith
hicPower.co
om or our distributors
d .

Figurre 1: EVKT-5416 Evaluation Kit Set-Up

MP5416 Rev. 1.2

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etary Information
n. Patent Protecte
ed. Unauthorized d Photocopy and
d Duplication Prohibited.
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 MP5416 – 5V, DIGITAL PMIC WITH 9 OUTPUTS

PACKAGE REFERENCE
TOP VIEW

QFN-28 (4mmx4mm)

ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance

(4)
θJA θJC
VIN1, VIN2, VIN3, VIN4, VIN5, AVIN.................. QFN-28 (4mmx4mm) ............. 44 ........ 9 .... °C/W
...................................................... 0.3V to 6.25V
NOTES:
VSWx ............................... -0.6V (-5V for <10ns) to 1) Exceeding these ratings may damage the device.
VIN+0.3V (7V for <10ns) 2) The maximum allowable power dissipation is a function of the
All other pins ................................ -0.3V to 6.25V maximum junction temperature TJ (MAX), the junction-to-
(2) ambient thermal resistance θJA, and the ambient temperature
Continuous power dissipation (TA = +25°C) TA. The maximum allowable continuous power dissipation at
................................................................. 2.84W any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
Junction temperature ................................150°C dissipation produces an excessive die temperature, causing
Lead temperature .....................................260°C the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
Storage temperature .................. -65°C to 150°C damage.
(3) 3) The device is not guaranteed to function outside of its
Recommended Operating Conditions operating conditions.
Step-down regulator (VIN) .............. 2.8V to 5.5V 4) Measured on JESD51-7, 4-layer PCB.
Step-down regulator (VOUT1/3) ........ 0.6V to 2.18V
Step-down regulator (VOUT2/4) .......... 0.8V to 3.9V
LDO regulator (VOUTL) ..................... 0.8V to 3.9V
Operating junction temp. (TJ) .. -40°C to +125°C

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 MP5416 – 5V, DIGITAL PMIC WITH 9 OUTPUTS

ELECTRICAL CHARACTERISTICS
(5)
VIN1 = VIN2 = VIN3 = VIN4 =VIN5 =AVIN =5V, TJ = -40°C to 125°C , unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
No switching, feedback is
Supply current (no switching) IIN 350 480 μA
highTJ=+25°C
Default oscillation frequency fSW 1.2 1.5 1.8 MHz
Thermal shutdown entry
TOTP_R 145 153 162 °C
threshold (6)
Thermal shutdown recovery
THys 121 130 139 °C
threshold (6)
Step-Down Regulator
AVIN UVLO rising VAIN1 R 2.4 2.55 2.7 V
AVIN UVLO hysteresis VAIN1 HYS 300 mV
VIN1 UVLO rising VIN1 R 2.3 2.45 2.6 V
VIN1 UVLO hysteresis VIN1 HYS 300 mV
VIN2 UVLO rising(7) VIN2 R 2.3 2.45 2.6 V
VIN2 UVLO hysteresis(7) VIN2 HYS 300 mV
VIN3 UVLO rising VIN3 R 2.3 2.45 2.6 V
VIN3 UVLO hysteresis VIN3 HYS 300 mV
VIN5 UVLO rising VIN5 R 2.3 2.45 2.6 V
VIN5 UVLO hysteresis VIN5 HYS 300 mV
VFB1 Default output of Buck1 1.1820 1.2 1.2180 V
VFB2 Default output of Buck2 1.4775 1.5 1.5225 V
Feedback voltage accuracy
VFB3 Default output of Buck3 1.7730 1.8 1.8270 V
VFB4 Default output of Buck4 3.2505 3.3 3.3495 V
Maximum duty cycle Dmax CH2 and CH4 only 100 %
Buck1, Buck3 (4.5A/4A)
HSRDS-ON1
500mA, TJ=+25°C 20 30 40 mΩ
HSRDS-ON3
HS switch on resistance
HSRDS-ON1
500mA, TJ = -40°C to 125°C 10 30 50 mΩ
HSRDS-ON3
LSRDS-ON1
500mA, TJ=+25°C 12 16 mΩ
LSRDS-ON3
LS switch on resistance
LSRDS-ON1
500mA, TJ = -40°C to 125°C 12 20 mΩ
LSRDS-ON3
HSWILK1 EN=0V, VIN=5.5V, SW=0V or
Switch leakage1 0 1 μA
HSWILK3 5.5V, TJ=+25°C
LSWILK1 EN=0V, VIN=5.5V, SW=0V or
Switch leakage2 0 1 μA
LSWILK3 5.5V, TJ=+25°C
ILIMIT1 Under 20% duty cycle, 5.5 6.8 8.3 A
High-side current limit
ILIMIT3 TJ=+25°C 4.5 5.6 7 A

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 MP5416 – 5V, DIGITAL PMIC WITH 9 OUTPUTS

ELECTRICAL CHARACTERISTICS (continued)

(5)
VIN1 = VIN2 = VIN3 = VIN4 =VIN5 =AVIN =5V, TJ = -40°C to 125°C , unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
tON MIN1 40 ns
Minimum on time(8)
tON MIN3 33 ns
tOFF MIN1 120 ns
Minimum off time(8)
tOFF MIN3 120 ns
Output discharge resistance RO DIS1 7 Ω
tSS_B1 VOUT=10% to 90% 450 μs
Soft-start time
tSS_B3 VOUT=10% to 90% 450 μs
Buck2, Buck4 (2.5A/2A)
HSRDS-ON2
500mA, TJ=+25°C 35 50 65 mΩ
HSRDS-ON4
HS switchon resistance
HSRDS-ON2
500mA, TJ = -40°C to 125°C 20 50 80 mΩ
HSRDS-ON4
LSRDS-ON2
500mA, TJ=+25°C 65 80 mΩ
LSRDS-ON4
LS switchon resistance
LSRDS-ON2
500mA, TJ = -40°C to 125°C 65 105 mΩ
LSRDS-ON4
HSWILK2 Shutdown, VIN=5.5V,
Switch leakage3 0 1 μA
HSWILK4 SW=0V or 5.5V, TA=+25°C
LSWILK2 Shutdown, VIN=5.5V,
Switch leakage 4 0 1 μA
LSWILK4 SW=0V or 5.5V, TA=+25°C
ILIMIT2 Under 20% duty cycle,
High-side current limit 3 4.2 5.4 A
ILIMIT4 TJ=+25°C
tON MIN2 32 ns
Minimum on time(8)
tON MIN4 32 ns
tOFF MIN2 100 ns
Minimum off time(8)
tOFF MIN4 100 ns
Output discharge resistance RO DIS2 7 Ω
tSS_B2 VOUT=10 to 90% 450 μs
Soft-start time
tSS_B4 VOUT=10 to 90% 450 μs
10mA RTC LDO
Default output voltage VRTC LDO IOUT=10mA, power on state 3.104 3.2 3.296 V
Ground current IQ RTC No load 6.5 μA
Dropout voltage(8) VDROP1 VOUT=3V, IOUT=10mA 100 mV
VIN=3.3V, VOUT drops 33%,
Current limit ILIM_RTC 25 55 85 mA
TJ=+25°C
Soft-start slew rate τSS_RTC VOUT=10% to 90%, COUT=1µF 35 mV/μs

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 MP5416 – 5V, DIGITAL PMIC WITH 9 OUTPUTS

ELECTRICAL CHARACTERISTICS (continued)

(5)
VIN1 = VIN2 = VIN3 = VIN4 =VIN5 =AVIN =5V, TJ = -40°C to 125°C , unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Low Dropout (LDO) Regulator: LDO2 to LDO5
VLDO2 3.2340 3.30 3.3660 V
VLDO3 3.2634 3.33 3.3966 V
Output voltage
VLDO4 1.0780 1.10 1.1220 V
VLDO5 1.7730 1.80 1.8270 V
PSRR 1k F=1kHz, 100mA, VOUT=1.8V 47 dB
PSRR(8)
PSRR10k F=10kHz, 100mA, VOUT=1.8V 51 dB
Dropout voltage VDROP1 VOUT=3V, IOUT=300mA 100 mV
Current limit ILIMIT LDO VIN=3.3V, VOUT drops 33% 320 430 640 mA
Output discharge resistance RO DIS2 7 Ω
Soft-start time tSS_B2 VOUT=10% to 90%, COUT=2.2µF 70 μs
Line regulation VIN2=VIN5=2.8V to 5.5V 0.3 %/V
VIN2=VIN5=3.3V, IOUTfrom
Load regulation 0.5 %
10mA to 100mA
Logic Pins
nPBIN pull-up current IPBIN Internal pull-up to AVIN 5 9 13 μA
Push-button detect threshold VPB 500 700 900 mV
Manual reset threshold VMS Npbin pulls low, TJ=+25°C 50 mV
RSTO rising threshold VRSTO R Monitor Buck4’s output 90% VFB4
RSTO falling threshold VRSTO F 80% VFB4
RSTO rising delay TRSTO Adjustable through I2C/OTP 10 ms
I2C Interface Specifications(9)
Input logic high VIH 1.4 V
Input logic low VIL 0.4 V
Output voltage logic low VOUT L RSTO pin sink 4mA 0.4 V
SCL clock frequency fSCL 3.4 MHz
SCL high time tHIGH 60 ns
SCL low time tLOW 160 ns
Data setup time tSU.DAT 10 ns
Data hold time tHD.DAT 70 ns
Setup time for repeated start tSU.STA 160 ns
Hold time for repeated start tHD.STA 160 ns
Bus free time between a start
tBUF 160 ns
and a stop condition
Setup time for stop condition TSU.STO 160 ns
Rise time of SCL and SDA tR 10 300 ns

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 MP5416 – 5V, DIGITAL PMIC WITH 9 OUTPUTS

ELECTRICAL CHARACTERISTICS (continued)

(5)
VIN1 = VIN2 = VIN3 = VIN4 =VIN5 =AVIN =5V, TJ = -40°C to 125°C , unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Fall time of SCL and SDA tF 10 300 ns
Pulse width of suppressed
tSP 0 50 ns
spike
Capacitance bus for each bus
CB 400 pF
line
SCL low time tLOW 160 ns
NOTES:
5) Not tested in production, guaranteed by over-temperature correlation.
6) Guaranteed by design.
7) VIN2 and VIN4 share the same UVLO. It is recommended to connect VIN2 and VIN4 together in practical application.
8) Guaranteed by engineering sample characterization.
2 2
9) Refer to below I C timing chart when reading the I C interface specifications.
2
It is recommended to begin operating the I C function after the power-on sequence is finished or RSTO switches high.

TIMING DIAGRAM

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 MP5416 – 5V, DIGITAL PMIC WITH 9 OUTPUTS

TYPICAL CHARACTERISTICS
Performance waveforms are tested on the evaluation board.
VIN = 5V, TA = 25°C, test using default spec parts, unless otherwise noted.

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 MP5416 – 5V, DIGITAL PMIC WITH 9 OUTPUTS

TYPICAL PERFORMANCE CHARACTERISTICS

Performance waveforms are tested on the evaluation board.
VIN = 5V, TA = 25°C, test using default spec parts, unless otherwise noted.

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 MP5416 – 5V, DIGITAL PMIC WITH 9 OUTPUTS

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Performance waveforms are tested on the evaluation board.
VIN = 5V,TA= 25°C,test using default spec parts, unless otherwise noted.

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 MP5416 – 5V, DIGITAL PMIC WITH 9 OUTPUTS

PIN FUNCTIONS
Package
Name Description
Pin #
Supply voltage input of Buck1. The MP5416 operates from a 2.8Vto5.5V input rail. A
1 VIN1 ceramic capacitor is required to decouple the input rail. Connect VIN1 using a wide PCB
trace. VIN1, VIN2, VIN3, VIN4, and AVIN must be connected to the same bus voltage.
2 SW1 Buck 1 switch output. Connect SW1 using a wide PCB trace.
Power ground of Buck1.GND1 requires special consideration during PCB layout.
3 GND1
Connect GND1 to GND with copper traces and vias.
Power ground of Buck3.GND3 requires special consideration during PCB layout.
4 GND3
Connect GND3 to GND with copper traces and vias.
5 SW3 Buck 3 switch output. Connect SW3 using a wide PCB trace.
Supply voltage input of Buck3. The MP5416 operates from a 2.8Vto5.5V input rail. A
6 VIN3 ceramic capacitor is required to decouple the input rail. Connect VIN3 using a wide PCB
trace.
7 FB3 Feedback of Buck3.Connect the output of Buck3 to FB3 directly.
Reset output from the PMIC to the CPU. The 3.3V (Buck4) output is ready after the
8 RSTO RSTODELAY timer on RSTO goes high. RSTO is an open-drain output and needs an
external pull-up resistor.
I2C clock signal input. SCL needs an external resistor pulled up to AVIN if the I2C function
9 SCL
is unused.
10 SDA I2C data.SDA needs an external resistor pulled up to AVIN if the I2C function is unused.
11 OUT4 LDO4 output. LDO4is powered by VIN5.
12 OUT5 LDO5 output. LDO5is powered by VIN5.
13 VIN5 Power input of LDO4 and LDO5.
14 FB4 Feedback of Buck4.Connect the output of Buck 4to FB4 directly.
Supply voltage input of Buck4. The MP5416 operates from a 2.8Vto5.5V input rail. A
15 VIN4 ceramic capacitor is required to decouple the input rail. Connect VIN4 using a wide PCB
trace.
16 SW4 Buck 4 switch output. Connect SW4 using a wide PCB trace.
Power ground of Buck4.GND4 requires special consideration during PCB layout.
17 GND4
Connect GND4 to GND with copper traces and vias.
Power ground of Buck2.GND2 requires special consideration during PCB layout.
18 GND2
Connect GND2 to GND with copper traces and vias.
19 SW2 Buck 2 switch output. Connect SW2 using a wide PCB trace.
Supply voltage input of Buck2, LDORTC, LDO2, and LDO3.The MP5416 operates from
20 VIN2 a 2.8Vto5.5V input rail. A ceramic capacitor is required to decouple the input rail. Connect
VIN2 using a wide PCB trace.
21 FB2 Feedback of Buck2.Connect the output of Buck 2 to FB2 directly.
22 OUT3 LDO3 output. LDO3is powered by VIN2.
23 OUT2 LDO2 output. LDO2is powered by VIN2.
RTC LDO output. This LDO is powered by VIN2. Set a high enough output voltage to
24 OUTRTC
achieve a lower voltage gap between VIN2 to OUTRTC.
25 AGND Analog ground. Connect AGND to power ground.

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 MP5416 – 5V, DIGITAL PMIC WITH 9 OUTPUTS

PIN FUNCTIONS(continued)
Package
Name Description
Pin #
Power supply input for logic circuitry. Bypass AVIN with a 0.1μF-1μF ceramic capacitor
26 AVIN
to AGND. Connect AVIN to the system input.
27 FB1 Feedback of Buck1.Connect the output of Buck 1 to FB1 directly.
Push-button input. nPBIN is a logic input pin to start up or shut down the device. A logic
28 nPBIN low over a pre-set deglitch time must be applied to nPBIN. nPBIN has a weak internal pull-
up current.

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 MP5416 – 5V, DIGITAL PMIC WITH 9 OUTPUTS

BLOCK DIAGRAM

Figure 1: Functional Block Diagram

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 MP5416 – 5V, DIGITAL PMIC WITH 9 OUTPUTS

OPERATION allowing for greater flexibility of the system

design.
The MP5416 provides a complete power
management solution for many 5V systems, The I2C and one-time programmable (OTP)
such as televisions, SSD, STB, and so on. The interface provide adjustable default output
MP5416integrates 4-channel, high-frequency, voltage and dynamic voltage scaling. In order to
synchronous, rectified, step-down, switch-mode determine the most optimal output voltage
converters and 5-channel, low-dropout configurations supported by this device, refer to
regulators. The MP5416reduces component application note AN139. The I2C also provides
count and PC board space greatly. The powerful logic functions. See the Register Map
MP5416can manage the power system either on page 28for more detail.
for a 1-cell Li+ or a 5V regulated input voltage,
1. Power Control
1.1 State Machine Diagram

Figure 2: Power Control State Machine Diagram

State Machine Description voltage (AVIN) is lower than the UVLO rising
The state machine (shown in Figure 2) has the threshold, the PMIC’s functions are disabled.
following features. Power Off
No Supply If the AUTOON bit=0, when AVIN is higher than
The PMIC’s input pin has an under-voltage its rising UVLO threshold, PMIC first enters a
lockout (UVLO) detection circuit. If the input power-off state. In this state, the PMIC is
always monitoring the power-on factor. Once

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 MP5416 – 5V, DIGITAL PMIC WITH 9 OUTPUTS

the power-on factor is detected, it changes to nPBIN_ON

the power-on sequence state. nPBIN_ON includes two kinds of push button
Power-On Sequence events. If nPBIN is pulled to logic low (but is not
pulled to ground) and asserts low for longer
DC/DC converters and LDO regulators turn on
than two seconds, the PMIC treats this as a
sequentially according to the pre-programmed
power-on factor. In the power-off state, if nPBIN
order by the OTP eFuse.
is pulled to ground (below the manual reset
Power-On threshold) and asserts more than 30ms of max
DC/DC converters and LDO regulators are debounce time, the PMIC also treats this as a
turned on. The RSTO output switches high. In power-on factor. The SYSEN bit is set high
this state, the PMIC always monitors the power- when any of above nPBIN-initiated power-on
off or repower-on factors. events are detected.
Power-Off Sequence Thermal Recovery
The PMIC enters the power-off sequence when If the MP5416is in a power-off state due to the
it detects the power-off or repower-on factors in die temperature exceeding the thermal
the power-on state. RSTO is first switched low, protection threshold, the PMIC enters a power-
and then the DC/DC converters and LDO on sequence when the die’s temperature
regulators turn off sequentially in the reverse decreases.
order of the power-on sequence. For repower- 1.3 Power-On Sequence
on condition(software control), after the power-
There are eight slots of power-on sequence
off sequence is completed, the PMIC enters the
timing (see Figure 3). All the DC/DC converters
power-on sequence automatically after a delay
and LDO regulators (except RTCLDO) can be
timer.
programmed to time slots 0 to 7 by the OTP
Shutdown Event eFuse. The delay time between each time slot
If the PMIC detects that the input voltage is is related with the default switching frequency of
lower than the UVLO falling threshold (enter no MP5416 (see Table 1).
supply state) or over-temperature protection is Table1: Slot Time Interval vs. Default Switching
triggered (enter power off state), the PMIC Frequency
switches to no supply state or power-off state, Default Switching Time Delay between
regardless of the current state. Frequency Each Slot
NOTE: If PMIC enters power-off state due to over-temperature 1.0MHz 3ms
protection triggering, LDORTC is off.
1.5MHz 2ms
1.2 Power-On Factor
2.0MHz 1.5ms
The PMIC has following power-on factors.
2.5MHz 1.2ms
SYSEN
SYSEN is one data bit in the I2C register. If the
SYSEN bit is set to 1, the system changes from
a power-off state to a power-on sequence.
SYSEN can be set from 0 to 1by two different
methods: first by setting the AUTOON bit to1 by
the OTP, and the system auto-loads the
AUTOON bit into SYSEN when the input
voltage crosses the UVLO threshold, and
second by the push button initiating a power on.

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Figure 3: Power-On Sequence(Auto-On Bit Is Setto 1)

1.3.1 OUTRTC ON nPBIN_Short_Press
OUTRTC LDO is always on if both VIN2 and If nPBINis pulled to GND(below the manual
AVIN are higher than their respective UVLO reset threshold) and lasts longer than 30ms of
rising thresholds, regardless of any other pin’s maximum debounce time, the PMIC enters the
status. OUTRTC turns off if either VIN2 or AVIN power-off sequence after 8msof delay time (see
falls below their respective UVLO falling Figure 6).
thresholds or thermal shutdown is triggered.
SYSEN(Software-Initiated Power-Off)
1.3.2 Other Buck Regulators and LDOs On The MP5416 supports a software-controlled
The MP5416 provides a programmable power- power-off through the I2C interface. SYSEN is
on sequence. Once the power-on sequence is one data bit in the I2C register. If the SYSEN bit
fixed, the power-off sequence is reversed. The is set to 0, the system enters a power-off
OTP configuration table on page 25 shows the sequence. The nPBIN function or toggle input
bits to set the time slot number for each power supply method are needed to make the
channel. PMIC restart again.
1.4 Power-Off Factor
nPBIN_Long_Press
If nPBIN is pulled to logic low (but not pulled to
ground) and asserts longer than eight seconds,
the PMIC enters the power-off sequence.

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1.4.1 Power-Off Sequence

Figure 4: Power off Sequence by nPBIN Key Press

RSTO is pulled low before the DC/DC converter 1.6 Repower-On Sequence (Software-
or LDO regulator turns off (see Figure 4). The Initiated Power Cycle)
DC/DC converter and LDO regulator power-off The MP5416 supports a software-controlled
sequence is in the reverse order of the power- power reset through the I2C interface or a
on sequence. manual reset push button.
1.5 Repower-On Factor When using the software-controlled method, the
Manual_Reset SFRST bit is set high. TheMP5416 waits for
nPBIN is pulled to ground (below the Manual 8ms and powers off the system, and powers on
Reset Threshold) for longer than 30ms of the all the power rails again after a 60ms delay.
maximum debounce time and is released after The SFRST bit is reset to 0automatically by the
a while (see Figure 6). RSTO rising edge. After the SFRST bit is reset
to 0, the software can control power cycle again.
SFRST There power-on factor detection is blocked
Software reset. If the SFRST bit is set to1 during the repower-on period (t1 to t2) (see
through the I2C interface, the system detects Figure 5).
this as a repower-on factor.

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Figure 5:Repower-On Sequence(Software Control)

When using the manual reset control method, if 1.7 Shutdown Sequence
the PMIC is working in a power-on state, once When the input voltage is lower than the UVLO
the manual reset button is pressed down, the falling threshold or the IC is over-temperature,
PMIC enters a power-off sequence after 30ms the PMIC enters the shutdown sequence
of maximum debounce time and 8ms of delay, directly. All DC/DC converters and LDO
and remains in the power-off state until the regulators turn off at the same time (see Figure
manual reset button is released. After 30ms of 7).
debounce time, the PMIC enters the power-on
sequence again, and the manual reset function
is also completed (see Figure 6).

Figure 6: Repower-On Sequence (Manual Reset Control)

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Figure 7: Shutdown Sequence

2. High Efficiency Buck Regulator from 0V. The soft-start period lasts until the
Buck1 to Buck4 are synchronous, step-down, voltage on the soft-start capacitor exceeds the
DC/DC converters with built-in UVLO, soft-start, reference voltage. At this point, the reference
compensation, and hiccup current limit voltage takes over. For four channel buck
protection. Fixed-frequency constant-on-time outputs, their soft-start times are fixed internally
(COT) control provides fast transient response. at 450µs.For the LDO2-LDO5 outputs, their
The switching clock is phase-shifted from soft-start times are fixed at 70µsinternally.For
Buck1 to Buck4 during continuous conduction LDORTC, the soft-start slew rate is consistent
mode (CCM) operation. Buck2 and Buck4 at 35mV/µs.
support 100% duty cycle mode. Output Discharge
Power Supply and UVLO To discharge the energy of the output capacitor
VIN1 is the power supply of Buck1. VIN2 is the during a power-off sequence, there is an active
power supply of Buck2, LDORTC, LDO2, and discharge path from the DC/DC converters and
LDO3. VIN3 is the power supply of Buck3. VIN4 LDO regulators output to ground. The discharge
is the supply of Buck4. VIN5 is the power path is turned on when the corresponding
supply of LDO4 to LDO5.AVIN is power input to channel is disabled. The typical discharge
the bias internal logic blocks. resistance is 7Ω. The discharge function can be
enabled or disabled through the I2C interface.
VIN1, VIN3, VIN5, and AVIN have their own
UVLO threshold with a proper hysteresis.VIN2 3. System Control Signals
and VIN4 share the same UVLO threshold. 3.1 nPBIN Functions
Once AVIN ramps up and exceeds the UVLO nPBIN is a multi-function pin that supports
rising threshold, the nPBIN logic is enabled and push-button detection and manual reset
ready to accept start-up and shutdown functions. There is an internal pull-up current to
commands. LDORTC is active once VIN2 pull up nPBIN’s voltage to AVIN.
exceeds the rising threshold. Before the power TheMP5416distinguishesbetweenthe push-
key turn-on, the input shutdown current is button and manual reset functions by the
typically 15µA. different pull-low resistances. Connect nPBIN to
Internal Soft Start (SS) ground for a manual reset function. Connect
nPBIN to ground through a 49.9kΩ resistor to
The soft-start (SS) function is implemented to
generate a push-button signal.
prevent the PMIC output voltage from
overshooting during start-up. When the PMIC A push-button event and manual reset event
starts up, the internal circuitry of each power rail can both generate an interrupt signal and set
generates a soft-start voltage that ramps up

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PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGEMP5416
the corresponding interrupt bit high. See the Status2 register on page 31 for details.

Figure 8: nPBIN Functional Block Diagram

3.1.1 Push Button Control seconds, the power-on sequence begins. The
Long Press1/Start-Up power-on sequence must be completed before
the backside CPU can take over control. The
When PMIC is in the power-off state, if AVIN is
power-on sequence complete signal is RSTO
higher than the UVLO threshold, and the push
switching high (see Figure 9).
button is asserted low for more than two

Figure 9: nPBIN Push Button Long Press1: Start-Up

Long Press2/Shutdown (excluding OUTRTC). The power-off sequence
During the power-on state, once the push is the reverse of start-up.
button is asserted low for more than eight If nPBIN is pulled low through a 49.9kΩ resistor
seconds, the power-off sequence begins. The constantly, the MP5416remains in the power-off
MP5416 turns off all regulators and LDOs state (see Figure 10).

Figure 10: nPBIN Push Button Long Press2: Shutdown

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3.1.2 Manual Reset Control MP5416begins the power-on sequence. When

the MP5416is turned on, a short press makes
Short Press and Release/Manual Reset
the nPBIN voltage lower than the manual reset
If theMP5416 is in a power-off state, a short threshold with 30ms of maximum debounce
press on nPBIN pulls the nPBIN voltage below time and triggers the manual reset function (see
the manual reset threshold with 30msof Figure 11).
maximum debounce time, and the

Figure 11: nPBIN Push Button Short Press to Ground

When the manual reset function is detected, the or the system detects a power-off factor,
PMIC enters and remains in power-off mode shutdown factor, or repower-on factor.
until the manual reset button is released. The
3.4Thermal Warning and Shutdown
PMIC enters the power-on state again after
30ms of maximum debounce time. Thermal warning and shutdown prevent the part
from operating at exceedingly high
3.2 Auto Turn-On temperatures. When the silicon die temperature
If the AUTOON bit in the OTP configuration exceeds 120°C, MP5416 sets the
table is set high, the system changes the OTWARNING bit to 1.
default value of SYSEN to 1. The PMIC enters
If the die temperature exceeds 153°C, the
the power-on sequence automatically once the
MP5416sets the OTEMPP bit to 1.Meanwhile,
input voltage AVIN exceeds its UVLO threshold.
the system enters the shutdown sequence.
The system can startup automatically without
When the temperature recovers to 130°C, the
pressing the push button. After power-up, the
regulator enters the power-on sequence again.
push button can still support the manual power-
on/-off control, and SYSEN can be read or 3.5 I2C Timing Graph
written by the I2C. The I2C interface of the PMIC is powered by an
3.3 RSTO (Reset Output) internal, fixed, 2V power supply. During VIN
power-up, when VIN exceeds its UVLO
When Buck4’s output voltage is ready (VFB>90%
threshold, this 2V power supply is ready after a
VREF), RSTO outputs high to enable the
0.5ms delay. After another 5ms of delay time,
processer after an RSTO delay time. RSTO is
the I2C is available (see Figure 12).
an open-drain structure with an external pull-up
resistor. RSTO is pulled low when Buck4’s
output is lower than 80% of the nominal value

Figure 12: I2C Timing Graph

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I2C INTERFACE
I2CSerial Interface Description
I2C is a 2-wire, bidirectional, serial interface
consisting of a data line (SDA) and a clock line
(SCL). The lines are pulled to a bus voltage
externally when they are idle. A master device Figure 13: Start and Stop Conditions
connected to the line generates the SCL signal
and device address and arranges the The master then generates the SCL clocks and
communication sequence. The MP5416 transmits the device address and the read/write
interface is an I2C slave, which supports both direction bit (r/w) on the SDA line.
fast mode (400kHz) and high-speed mode Transfer Data
(3.4MHz). The I2C interface adds flexibility to
the power supply solution. The output voltage, Data is transferred in 8-bit bytes by the SDA
transition slew rate, or other parameters can be line. Each byte of data is to be followed by an
controlled by the I2C interface instantaneously. acknowledge bit.
When the master sends the address as an 8-bit I2C Update Sequence
value, the 7-bit address should be followed by a The MP5416 requires a start condition, a valid
0 or 1 to indicate a write or read operation. I2C address, a register address byte, and a data
Start and Stop Conditions byte for a single data update. The MP5416
Start and stop are signaled by the master acknowledges the receipt of each byte by
device, which signifies the beginning and end of pulling the SDA line low during the high period
the I2C transfer. The start condition is defined of a single clock pulse. A valid I2C address
as the SDA signal transitioning from high to low selects the MP5416. The MP5416 performs an
while the SCL is high. The stop condition is update on the falling edge of the LSB byte.
defined as the SDA signal transitioning from low Examples of an I2C write and read sequence
to high while the SCL is high (see Figure 13). are shown below.

I2C Write Example – Write Single Register

I2C Write Example – Write Multi Register

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I2C Read Example – Read Single Register

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 MP5416 – 5V, DIGITAL PMIC WITH 9 OUTPUTS

REGISTER DESCRIPTION
OTP eFuse Configuration Table
# NAME D7 D6 D5 D4 D3 D2 D1 D0
00 CTL1 AUTOON FREQUENCY PUSHBUTTONTIMER RSTODELAY
01 CTL2 ILIMBUCK1 ILIMBUCK3 N/A PWRONDELAYBUCK1
02 CTL3 MODEBUCK1 NOT NEED PWRONDELAYBUCK2 PWRONDELAYBUCK3
03 CTL4 MODEBUCK2 NOT NEED PWRONDELAYBUCK4 PWRONDELAYLDO2
04 CTL5 MODEBUCK3 NOT NEED PWRONDELAYLDO3 PWRONDELAYLDO4
05 CTL6 MODEBUCK4 NOT NEED PWRONDELAYLDO5 N/A
06 VSET1 ENBUCK1 BUCK 1 VOUT SET: 0.6V-2.1V/100mV STEP(10) I2C SLAVE ADDRESS A3, A2, A1
BUCK 2 OUTPUT VOLTAGE SET: 0.8V-3.9V/100mV
07 VSET2 ENBUCK2 N/A
STEP(10)
(10)
08 VSET3 ENBUCK3 BUCK 3 VOUT SET: 0.6V-2.1V/100mV STEP N/A
BUCK 4 OUTPUT VOLTAGE SET: 0.8V-3.9V/100mV
09 VSET4 ENBUCK4 N/A
STEP(10)
10 VSET5 Reserved LDORTC OUTPUT VOLTAGE SET: 0.8V-3.9V/100mV STEP N/A
11 VSET6 ENLDO2 LDO2 OUTPUT VOLTAGE SET: 0.8V-3.9V/100mV STEP N/A
12 VSET7 ENLDO3 LDO3 OUTPUT VOLTAGE SET: 0.8V-3.9V/100mV STEP N/A
13 VSET8 ENLDO4 LDO4 OUTPUT VOLTAGE SET: 0.8V-3.9V/100mV STEP OTP VERSION D1, D0
14 VSET9 ENLDO5 LDO5 OUTPUT VOLTAGE SET: 0.8V-3.9V/100mV STEP OTP VERSION D3, D2

OTP eFuse Selected Table by Default

OTP Items Buck1 Buck2 Buck3 Buck4 LDORTC LDO2 LDO3 LDO4 LDO5

Output Voltage 1.2V 1.5V 1.8V 3.3V 3.2V 3.3V 3.3V 1.1V 1.8V
Initial On/Off On On On On On On Off On On
Mode FPWM PFM FPWM FPWM N/A
Power-On Delay/Time Slot # 2ms/1 4ms/2 4ms/2 0ms/0 Always on 4ms/2 6ms/3 2ms/1 4ms/2
Automatic Turn-On Yes
Switching Frequency 1.5MHz
Push-Button Timer 2 seconds
RSTO Delay 10ms
Buck 1 Peak Current Limit 6.8A
Buck 3 Peak Current Limit 5.6A
2
I C Slave Address 0x69
OTP Version 0000
NOTES:
10) In order to determine the most optimal output voltage configurations supported by this device, refer to application note AN139
.

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Descriptions
NAME BITS DEFAULT DESCRIPTION
System automatic turn-on bit. If AUTOON is set high, the system enters the power-on
sequence once AVIN exceeds the UVLO rising threshold. There is no need to press
AUTOON D[7] 1 the push button (nPBIN).
The AUTOON bit information is loaded into the SYSEN register after AVIN reaches the
UVLO rising threshold.
Switching frequency set bit.
00: fs=1MHz
FREQUENCY D[6:5] 01 01: fs=1.5MHz
10: fs= 2MHz
11: fs=2.5MHz
Set the push button long press1 power-on deglitch timer.
Fsw=1MHz Fsw=1.5MHz Fsw=2MHz Fsw=2.5MHz
000 0.75s 0.5s 0.375s 0.3s
001 1.5s 1s 0.75s 0.6s
010 2.25s 1.5s 1.225s 0.9s
PUSHBUTTON
D[4:2] 011 011 3s 2s 1.5s 1.2s
TIMER
100 3.75s 2.5s 1.875s 1.5s
101 4.5s 3s 2.25s 1.8s
110 5.25s 3.5s 2.625s 2.1s
111 6s 4s 3s 2.4s
There is no corresponding data in the I2C register table for the three bits.
Reset output delay.
Fsw=1MHz Fsw=1.5MHz Fsw=2MHz Fsw=2.5MHz
00 210ms 140ms 105ms 84ms
RSTODELAY D[1:0] 11 01 150ms 100ms 75ms 60ms
10 75ms 50ms 37.5ms 30ms
11 15ms 10ms 7.5ms 6ms
There is no corresponding data in the I2C register table for the three bits.
Delay time from SYSEN=high to Buckx/LDOx beginning to switch.
000: 0ms – time slot 0
001:2ms– time slot 1
010:4ms– time slot 2
011:6ms– time slot 3
PWRONDELAY 100: 8ms– time slot 4
BUCK1-4, 3 bit --- 101: 10ms– time slot 5
LDO2-6 110: 12ms– time slot 6
111: 14ms– time slot 7
Delay time between neighbor slots are related with the PMIC default switching
frequency. Refer to the Operation section on page 16for details.
There is no corresponding data in the I2C register table for the three bits.
Select the mode (auto PFM/PWM mode or forced PWM mode).
0: auto PFM/PWM mode (Buck2 default mode)
MODEBUCKX 1 bit --- 1: forced PWM mode (Buck1, Buck3, and Buck4 default mode)
2
These bits are loaded into the I C register MODE BUCKx during VIN1 exceeding
UVLO.

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Descriptions(continued)
NAME BITS DEFAULT DESCRIPTION
Program the current limit threshold of the buck regulator:
00: 3.8A typical high-side peak current limit
ILIMBUCK1/3 2 bit 10 01: 4.6A typical high-side peak current limit
10: 5.6A typical high-side peak current limit
11: 6.8A typical high-side peak current limit
I2C SLAVE
Set the A3 to A1 bit of the slave I2C address. Refer to the I2C bus slave address on
ADDRESS A3, 3 bit 001
page 28.
A2, A1

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I2C Register Map

ADD
NAME R/W D7 D6 D5 D4 D3 D2 D1 D0
(HEX)
00 CTL0 r/w SYSEN SFRST Reserved Reserved Reserved
MODEBU MODEBU MODEBUC MODEBUC DISCHGB DISCHGBUC DISCHGBU
01 CTL1 r/w Reserved
CK1 CK2 K3 K4 UCK3 K2 CK1

DISCHGB DISCHGLD DISCHGLD DISCHGL DISCHGLDO

02 CTL2 r/w DVS SLEW RATE Reserved
UCK4 O2 O3 DO4 5
03 ILIMIT r/w ILIMBUCK1 ILIMBUCK3 ILIMBUCK2 ILIMBUCK4
(10)
04 VSET1 r/w ENBUCK1 BUCK1 OUTPUT VOLTAGE SET: 0.6V-2.1875V/12.5mV STEP
(10)
05 VSET2 r/w ENBUCK2 BUCK2 OUTPUT VOLTAGE SET: 0.8V-3.975V/25mV STEP
(10)
06 VSET3 r/w ENBUCK3 BUCK3 OUTPUT VOLTAGE SET: 0.6V-2.1875V/12.5mV STEP
(10)
07 VSET4 r/w ENBUCK4 BUCK4 OUTPUT VOLTAGE SET: 0.8V-3.975V/25mV STEP
08 VSET5 r/w ENLDO2 LDO2 OUTPUT VOLTAGE SET: 0.8V-3.975V/25mV STEP
09 VSET6 r/w ENLDO3 LDO3 OUTPUT VOLTAGE SET: 0.8V-3.975V/25mV STEP
0A VSET7 r/w ENLDO4 LDO4 OUTPUT VOLTAGE SET: 0.8V-3.975V/25mV STEP
0B VSET8 r/w ENLDO5 LDO5 OUTPUT VOLTAGE SET: 0.8V-3.975V/25mV STEP
0C RESERVED
0D Status1 r PGLDO4 PGLDO3 PGLDO2 PGRTC PG4 PG3 PG2 PG1
SHORTKEY
0E Status2 r KEYON KEYOFF MREST SFRST_ON Reserved Reserved PGLDO5
ON
0F Status3 r OTWARNING OTEMPP Reserved Reserved Reserved Reserved Reserved Reserved
10 Reserved
11 ID2 r VENDOR ID OTP VERSION

Register Description
I2C Bus Slave Address(11)
The slave address is seven bits followed by an eights data direction bit (read or write). The A3, A2, and A1
bits are programmable by the OTP eFuse.

A7 A6 A5 A4 A3 A2 A1

Setting Value 1 1 0 1 0(12) 0(12) 1(12)

NOTES:
11) By default, the slave address is 0x69, A[7:1]=1101 001.
12) This bit is programmable by the OTP eFuse.

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1. Reg00 CTL0
NAME BITS DEFAULT DESCRIPTION RESET CONDITION
System enable on/off bit. When the MP5416 detects a
power-on event, this bit is set to 1. Then the power-on
sequence starts. The DC/DC converters and LDO
regulators turn on sequentially according to its enable bit
(e.g.: ENBUCK1=1) and power-on delay
BY OTP (POWERONDELAYBUCK1) setting.
SYSEN D[7] AVIN<UVLO
AUTOON
Set this bit from 1 to 0 to trigger a power-off sequence.
Other I2C registers are not reset when the I2C sets SYSEN
from 1 to 0. The MP5416is enabled again until the push
button is pressed for a long time or a manual reset is
asserted for more than 30ms of maximum debounce time.
Software reset. Once the SFRST bit is set high, the AVIN<UVLO or
MP5416 waits for 8ms and restarts all power rails. When RSTO from low to
SFRST D[6] 0
the RSTO signal switches from low to high, the MP5416 high
resets SFRST=0.

2. Reg01CTL1
NAME BITS DEFAULT DESCRIPTION RESET CONDITION
PFM/PWM mode or forced PWM mode.
MODEBUCKx D[6:3] BY OTP 0: auto PFM/PWM AVIN<UVLO or
1: forced PWM mode SFRST or manual
reset or long press2
Regulator Output discharge enable bit. The output discharge function
D[2:0] 1
Discharge is active during the power-off sequence.

3. Reg02CTL2
NAME BITS DEFAULT DESCRIPTION RESET CONDITION
Voltage scaling slew rate for the Buck1 to Buck4
converters.
DVS SLEW 00: 32mV/µs
D[7:6] 01
RATE 01: 16mV/µs AVIN<UVLO or
10: 8mV/µs SFRST or manual
11: 4mV/µs reset or long press2
Output discharge enable bit. The output discharge function
Regulator
D[5:0] 1 is active during the power-off sequence and active after
Discharge
shutdown.

4. Reg03 ILIMIT
NAME BITS DEFAULT DESCRIPTION RESET CONDITION
Program the current-limit threshold of the buck regulator.

ILIMBUCK1 00: 3.8A typical high-side peak current limit

D[X:X] BY OTP 01: 4.6A typical high-side peak current limit
ILIMBUCK3
10: 5.6A typical high-side peak current limit
11: 6.8A typical high-side peak current limit AVIN<UVLO
Or SFRST
Program the current-limit threshold of the buck regulator. Or manual reset
00: 2.2A typical high-side peak current limit. or long press2
ILIMBUCK2
D[X:X] 10 01: 3.2A typical high-side peak current limit.
ILIMBUCK4
10: 4.2A typical high-side peak current limit.
11: 5.2A typical high-side peak current limit.

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5. Reg04 to Reg0B VSET & EN

NAME BITS DEFAULT DESCRIPTION RESET CONDITION
Enable bit of Buckx and LDOx. The default value is 1, but
ENX D[7] BY OTP the default SYSEN is 0. Regulators are enabled when both AVIN<UVLO
ENx=1 and SYSEN=1. Or SFRST
Or manual reset
BUCK1/3 Set the output voltage (10)from 0.6V to 2.1875V with or long press2
D[6:0] BY OTP
VOUT SET 12.5mV step(see Table 2).

Table 2: Output Voltage Chart of Buck1 and Buck3

D[6:0] VOUT(V) D[6:0] VOUT(V) D[6:0] VOUT(V) D[6:0] VOUT(V)
0000000 0.6000 0100000 1.0000 1000000 1.4000 1100000 1.8000
0000001 0.6125 0100001 1.0125 1000001 1.4125 1100001 1.8125
0000010 0.6250 0100010 1.0250 1000010 1.4250 1100010 1.8250
0000011 0.6375 0100011 1.0375 1000011 1.4375 1100011 1.8375
0000100 0.6500 0100100 1.0500 1000100 1.4500 1100100 1.8500
0000101 0.6625 0100101 1.0625 1000101 1.4625 1100101 1.8625
0000110 0.6750 0100110 1.0750 1000110 1.4750 1100110 1.8750
0000111 0.6875 0100111 1.0875 1000111 1.4875 1100111 1.8875
0001000 0.7000 0101000 1.1000 1001000 1.5000 1101000 1.9000
0001001 0.7125 0101001 1.1125 1001001 1.5125 1101001 1.9125
0001010 0.7250 0101010 1.1250 1001010 1.5250 1101010 1.9250
0001011 0.7375 0101011 1.1375 1001011 1.5375 1101011 1.9375
0001100 0.7500 0101100 1.1500 1001100 1.5500 1101100 1.9500
0001101 0.7625 0101101 1.1625 1001101 1.5625 1101101 1.9625
0001110 0.7750 0101110 1.1750 1001110 1.5750 1101110 1.9750
0001111 0.7875 0101111 1.1875 1001111 1.5875 1101111 1.9875
0010000 0.8000 0110000 1.2000 1010000 1.6000 1110000 2.0000
0010001 0.8125 0110001 1.2125 1010001 1.6125 1110001 2.0125
0010010 0.8250 0110010 1.2250 1010010 1.6250 1110010 2.0250
0010011 0.8375 0110011 1.2375 1010011 1.6375 1110011 2.0375
0010100 0.8500 0110100 1.2500 1010100 1.6500 1110100 2.0500
0010101 0.8625 0110101 1.2625 1010101 1.6625 1110101 2.0625
0010110 0.8750 0110110 1.2750 1010110 1.6750 1110110 2.0750
0010111 0.8875 0110111 1.2875 1010111 1.6875 1110111 2.0875
0011000 0.9000 0111000 1.3000 1011000 1.7000 1111000 2.1000
0011001 0.9125 0111001 1.3125 1011001 1.7125 1111001 2.1125
0011010 0.9250 0111010 1.3250 1011010 1.7250 1111010 2.1250
0011011 0.9375 0111011 1.3375 1011011 1.7375 1111011 2.1375
0011100 0.9500 0111100 1.3500 1011100 1.7500 1111100 2.1500
0011101 0.9625 0111101 1.3625 1011101 1.7625 1111101 2.1625
0011110 0.9750 0111110 1.3750 1011110 1.7750 1111110 2.1750
0011111 0.9875 0111111 1.3875 1011111 1.7875 1111111 2.1875

6. Buck 2, Buck4, and LDO Regulator Output Voltage Set

NAME BITS DEFAULT DESCRIPTION RESET CONDITION
BUCK2/4, (10) AVIN<UVLO
Set the output voltage from 0.8V to 3.975V with 25mV
LDO VOUT D[6:0] BY OTP or SFRST or manual
step(see Table 3).
SET reset or long press2

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Table 3: Output Voltage Chart of Buck2, Buck4, and all LDOs

D[6:0] VOUT(V) D[6:0] VOUT(V) D[6:0] VOUT(V) D[6:0] VOUT(V)
0000000 0.800 0100000 1.600 1000000 2.400 1100000 3.200
0000001 0.825 0100001 1.625 1000001 2.425 1100001 3.225
0000010 0.850 0100010 1.650 1000010 2.450 1100010 3.250
0000011 0.875 0100011 1.675 1000011 2.475 1100011 3.275
0000100 0.900 0100100 1.700 1000100 2.500 1100100 3.300
0000101 0.925 0100101 1.725 1000101 2.525 1100101 3.325
0000110 0.950 0100110 1.750 1000110 2.550 1100110 3.350
0000111 0.975 0100111 1.775 1000111 2.575 1100111 3.375
0001000 1.000 0101000 1.800 1001000 2.600 1101000 3.400
0001001 1.025 0101001 1.825 1001001 2.625 1101001 3.425
0001010 1.050 0101010 1.850 1001010 2.650 1101010 3.450
0001011 1.075 0101011 1.875 1001011 2.675 1101011 3.475
0001100 1.100 0101100 1.900 1001100 2.700 1101100 3.500
0001101 1.125 0101101 1.925 1001101 2.725 1101101 3.525
0001110 1.150 0101110 1.950 1001110 2.750 1101110 3.550
0001111 1.175 0101111 1.975 1001111 2.775 1101111 3.575
0010000 1.200 0110000 2.000 1010000 2.800 1110000 3.600
0010001 1.225 0110001 2.025 1010001 2.825 1110001 3.625
0010010 1.250 0110010 2.050 1010010 2.850 1110010 3.650
0010011 1.275 0110011 2.075 1010011 2.875 1110011 3.675
0010100 1.300 0110100 2.100 1010100 2.900 1110100 3.700
0010101 1.325 0110101 2.125 1010101 2.925 1110101 3.725
0010110 1.350 0110110 2.150 1010110 2.950 1110110 3.750
0010111 1.375 0110111 2.175 1010111 2.975 1110111 3.775
0011000 1.400 0111000 2.200 1011000 3.000 1111000 3.800
0011001 1.425 0111001 2.225 1011001 3.025 1111001 3.825
0011010 1.450 0111010 2.250 1011010 3.050 1111010 3.850
0011011 1.475 0111011 2.275 1011011 3.075 1111011 3.875
0011100 1.500 0111100 2.300 1011100 3.100 1111100 3.900
0011101 1.525 0111101 2.325 1011101 3.125 1111101 3.925
0011110 1.550 0111110 2.350 1011110 3.150 1111110 3.950
0011111 1.575 0111111 2.375 1011111 3.175 1111111 3.975

7. Reg0D Status1
Status registers are non-latch type. It automatically updates according to its real-time status.
NAME BITS DESCRIPTION RESET CONDITION
Power good indicator for the buck and LDO. PG=1 when the output
voltage is higher than 90% of the reference voltage. PG=0 when the AVIN<UVLO
output voltage is lower than 80% of the reference voltage. Or SFRST or
PGx D[7:0]
manual reset or long
During the I2C-controlled dynamic voltage scaling, the PG deglitch timer press2
blanks the possible PG glitch.

8. Reg0E Status2
NAME BITS DESCRIPTION RESET CONDITION
KEYON D[7] Push button power-on event (long press1) is detected.
KEYOFF D[6] Push button power-off event (long press2) is detected. This bit is
latched
MREST D[5] Manual reset event is detected. once it’s
triggered
If the MP5416 is in a power-off state, nPBIN is pulled to and cleared AVIN<UVLO
SHORTKEYO
D[4] ground and lasts longer than the 30ms maximum by a read
N
debounce time. Then the SHORTKEYON bit is set high. action to
A software reset event is detected. When the SFRST bit is the status
SFRST_ON D[3] set high, the SFRST_ON bit goes high, and the high state register.
is latched.
AVIN<UVLO or
PGx D[0] Power good indicator for LDO5. Non-latch type bits. SFRST or manual
reset or long press2

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9. Reg0F Status3

NAME BITS DESCRIPTION RESET CONDITION

This bit is
Die temperature early warning bit. When the bit is high, latched
OTWARNING D[7]
the die temperature is higher than 120˚C. once it’s
triggered
and cleared AVIN<UVLO
by a read
Over-temperature indication. When the bit is high, the IC action to
OTEMPP D[6]
is in thermal shutdown. the status
register.

10. Reg11 ID2

NAME BITS DESCRIPTION
Vendor ID D[7:4] 1000
OTP version D[3:0] 0000

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APPLICATION INFORMATION For simplification, choose an input capacitor

with an RMS current rating greater than half of
Selecting the Inductor
the maximum load current.
For most applications, use a 0.47µHto2.2µH
inductor with a DC current rating at least 25% The input capacitor can be electrolytic, tantalum,
higher than the maximum load current. For the or ceramic. When using electrolytic or tantalum
highest efficiency, use an inductor with a DC capacitors, add a small, high-quality, ceramic
resistance less than 15mΩ. For most designs, capacitor (e.g.: 0.1μF) placed as close to the IC
the inductance value can be derived from as possible. When using ceramic capacitors,
Equation (1): ensure that they have enough capacitance to
provide sufficient charge to prevent excessive
VOUT  (VIN  VOUT ) voltage ripple at the input. The input voltage
L1 
VIN  IL  fOSC (1) ripple caused by the capacitance can be
estimated with Equation (5):
Where ∆IL is the inductor ripple current.
ILOAD V  V 
Choose the inductor ripple current to be VIN   OUT   1  OUT 
fS  C1 VIN  VIN 
approximately 30% of the maximum load (5)
current. The maximum inductor peak current Selecting the Step-Down Converter Output
can be calculated with Equation (2): Capacitor
IL The output capacitor for the step-down
IL(MAX )  ILOAD  regulator maintains the DC output voltage. Use
2 (2) ceramic, tantalum, or low ESR electrolytic
Use a larger inductor for improved efficiency capacitors. For best results, use low ESR
under light-load conditions(<100mA). capacitors to keep the output voltage ripple low.
The output voltage ripple can be estimated with
Selecting the Step-Down Converter Input Equation (6):
Capacitor
The input current to the step-down converter is VOUT  V   1 
VOUT    1  OUT    RESR  
discontinuous and therefore requires a fS  L1  VIN   8  fS  C2 
(6)
capacitor to supply AC current to the step-down
converter while maintaining the DC input Where L1 is the inductor value, and RESR is the
voltage. Use low ESR capacitors for the best equivalent series resistance (ESR) value of the
performance. Ceramic capacitors with X5R or output capacitor.
X7R dielectrics are recommended because of For ceramic capacitors, the capacitance
their low ESR and small temperature dominates the impedance at the switching
coefficients. For most applications, use a 22µF frequency and causes the majority of the output
capacitor. voltage ripple. For simplification, the output
Since C1 absorbs the input switching current, it voltage ripple can be estimated with Equation
requires an adequate ripple current rating. The (7):
RMS current in the input capacitor can be VOUT  V 
∆VOUT    1  OUT 
estimated with Equation (3): 8  fS2  L1  C2  VIN 
(7)

I C1  ILOAD 
VOUT  VOUT
 1

 For tantalum or electrolytic capacitors, the ESR
VIN  VIN 
 dominates the impedance at the switching
(3)
frequency. For simplification, the output ripple
The worst-case condition occurs at VIN = 2VOUT, can be approximated with Equation (8):
shown in Equation (4):
VOUT  VOUT 
∆VOUT   1   RESR
I
IC1  LOAD fS  L1  VIN  (8)
2 (4)
The characteristics of the output capacitor also
affect the stability of the regulation.

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Recommended External Components for PCB Layout Guidelines (13)

DC/DC and LDO Converters Efficient PCB layout is critical for stable
Table 4 lists recommended external operation. A four-layer layout is recommended
components for the DC/DC converters and LDO for the best performance. For best results, refer
regulators. to Figure 14 and follow the guidelines below.
Table 4: Recommended External Components 1. Connect the input ground to GND using the
Value Notes shortest and widest trace possible.
Cin of VIN1 22µF 0805 size/10V ceramic capacitor 2. Connect the input capacitor to VIN using the
Cin of VIN2 22µF 0805 size/10V ceramic capacitor shortest and widest trace possible.
Cin of VIN3 22µF 0805 size/10V ceramic capacitor 3. Ensure that FB1-FB4 are Kelvin connected
Cin of VIN4 22µF 0805 size/10V ceramic capacitor to the Buck1-Buck4 output capacitor. DO
Cin of VIN5 10µF 0805 size/10V ceramic capacitor NOT directly connect FB to the inductor’s
Cin of AVIN 1µF 0603 size/10V ceramic capacitor output node.
Cout of Buck1 22µFx2 0805 size/10V ceramic capacitor 4. Route SW away from sensitive analog
L of Buck1 1µH ISAT> current limit areas, such as FB1 to FB4.
Cout of Buck2 22µF 0805 size/10V ceramic capacitor
NOTE:
L of Buck2 1.5µH ISAT> current limit 13) The recommended layout is based on Figure 15 on page 36.
Cout of Buck3 22µFx2 0805 size/10V ceramic capacitor
L of Buck3 1µH ISAT> current limit
Cout of Buck4 22µF 0805 size/10V ceramic capacitor
L of Buck4 1.5µH ISAT> current limit
Cout of
1µF 0603 size/6.3V ceramic capacitor
RTCLDO
Cout of LDO2 2.2µF 0603 size/6.3V ceramic capacitor
Cout of LDO3 2.2µF 0603 size/6.3V ceramic capacitor
Cout of LDO4 2.2µF 0603 size/6.3V ceramic capacitor
Cout of LDO5 2.2µF 0603 size/6.3V ceramic capacitor
RSTO pull-up
100kΩ 0603 or 0402 size film resistor
resistor
nPBIN pull-low Push button function. 0603 or
49.9kΩ
resistor 0402 size film resistor
AVIN series
10Ω 0603 or 0402 size film resistor
resistor to VIN1

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Buck1 VIN1 PGND VIN2 Buck2

C6A C6B C7A C7B

L1 SW1 SW2 L2
C5 C10 C11 C12
R2

C1 C2

PGND PGND Top layer

C3 C4
Inner layer1

Bottom layer
R1 C13 C14 C15
L3 SW3 SW4 L4

C8A C8B C9A C9B

Buck3 VIN3 PGND VIN5 VIN4

Buck4

Figure 14: Recommended Layout(14)

NOTE:
14) It is recommended to separate Buck1/3 and Buck2/4’s PGND on the top layer.

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TYPICAL APPLICATION CIRCUIT

Figure 15: Typical Application Circuit(15)

NOTE:
15) The minimum input voltage of VIN5 is equal to the maximum nominal output voltage of LDO4 and LDO5.

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PACKAGE INFORMATION
QFN-28 (4mmx4mm)

NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.

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