Design of Combinational

Logic Circuits

Slide 1
BITS Pilani, Dubai Campus Analog & Digital VLSI Design
Dr. Vilas
Static CMOS Circuits

• The CMOS circuits falls under the category of static Circuits in which every point of
time each gate output either connected to Vdd or Vss via low resistance path.
•In dynamic circuit class, the circuits relies on the temporarily storage of signal values
on the capacitance of high impedance circuits nodes.
This simpler and faster but fails due to sensitivity to noise.

•A static CMOS gate is combination of

1 . Pull-Up Network (PUN): Provide connection between Vdd and Output
2 . Pull Down Network (PDN) : Provide Connection between output and ground

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Slide 2
BITS Pilani, Dubai Campus Analog & Digital VLSI Design
Dr. Vilas
Static CMOS Circuits

• 1. Two Input NAND Gate

•2. Two Input NOR Gate
F = BC + A ( D + E )
•3. F = D + A(B + C )
F = (B + C) + ( A+ D + E)
•VTC Curve for Two input NAND Gate
• Conditions : 1. A=B=0 to 1
2. A= 1, B= 0 to 1
3. B= 1, A = 0 to 1

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Slide 3
BITS Pilani, Dubai Campus Analog & Digital VLSI Design
Dr. Vilas
Propagation Delay of CMOS Gates

•For delay analysis each transistor is modeled as a resistor in series with a ideal Switch
•The value of resistance is depend on the Vdd and equivalent large signal scaled by the
ratio of device W and L
•The logic is transferred into an equivalent RC network that includes the effect of
internal node capacitances.
•The propagation delay is depend upon the input pattern
•For the case B=1 and A= 1 to 0 PMOS only has to charge up the output node
•For A=1 and B= 1 to 0 PMOS has to charge up output node and the internal node.
•The propagation delay can be calculated by using the Elmore delay model. (Four
input NAND gate )

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Slide 4
BITS Pilani, Dubai Campus Analog & Digital VLSI Design
Dr. Vilas
 Input Pattern Effects on Delay

 Delay is dependent on the pattern of inputs

 High to Low transition

Rp Rp
⚫ both inputs go low
A B
− delay is 0.69 Rp/2 CL
Rn CL ⚫ one input goes low
A − delay is 0.69 Rp CL

Rn  Low to High transition

Cint
B ⚫ both inputs go high

− delay is 0.69 2Rn CL

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Slide 5
BITS Pilani, Dubai Campus Analog & Digital VLSI Design
Dr. Vilas
 Propagation Delay of CMOS Gates

3
Input Data Delay
2.5 A=B=1→0 Pattern (psec)
2
A=B=0→1 69
Voltage [V]

1.5
B=1, A=1 →0, A=1, B=0→1 62
1

0.5
A=1, B=1→0 A= 0→1, B=1 50
0
A=B=1→0 35
0 100 200 300 400
-0.5
A=1, B=1→0 76
time [ps]
A= 1→0, B=1 57

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Slide 6
BITS Pilani, Dubai Campus Analog & Digital VLSI Design
Dr. Vilas
 Fan-In Considerations

A B C D

A CL
B C3
➢ Distributed RC model
C (Elmore delay)
C2
D C1 ➢tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

➢Propagation delay deteriorates rapidly

as a function of fan-in

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Slide 7
BITS Pilani, Dubai Campus Analog & Digital VLSI Design
Dr. Vilas
 Full Adder Circuit using CMOS
➢ The transistor level design of the CMOS full adder circuit needs 14 pMOS and
14nPOS Transistor with two CMOS inverter are used to generate the output.

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Slide 8
BITS Pilani, Dubai Campus Analog & Digital VLSI Design
Dr. Vilas
 Full Adder Circuit using CMOS

Sum = A  B  C
= ABC+ABC+ABC+ABC
Carry_out = AB+BC+AC

➢For minimum number of MOSFETs we have to use the above circuit

Carry_out = AB+C ( A+B )

Sum =  AB+C ( A+B )   ( A + B + C ) + ABC

 

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Slide 9
BITS Pilani, Dubai Campus Analog & Digital VLSI Design
Dr. Vilas
 Full Adder Circuit using CMOS

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Slide 10
BITS Pilani, Dubai Campus Analog & Digital VLSI Design
Dr. Vilas
 Pass Gate or CMOS Transmission gate

➢ A simple switch circuit called pass gate or CMOS Transmission gate (TG)
➢ It consist of one nMOS and one pMOS transistor connected in parallel
➢The gate voltage applied to these two transistors are also set to be complementary
signal.

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Slide 11
BITS Pilani, Dubai Campus Analog & Digital VLSI Design
Dr. Vilas
 Pass Gate or CMOS Transmission gate
For pMOS
➢The nMOS transistor will be
Vout  VDD − VT ,n VDS , p = Vout − VDD
turned off for
➢The nMOS transistor will
operate in Saturation for Vout  VDD − VT ,n

➢The pMOS transistor operates

in saturation for Vout  VT , p
➢The pMOS transistor operates
For nMOS
in linear region for V  V
out T ,p VDS ,n = VDD − Vout

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Slide 12
BITS Pilani, Dubai Campus Analog & Digital VLSI Design
Dr. Vilas
 Pass Gate or CMOS Transmission gate
➢Two-input multiplexor circuit implemented using two CMOS TGs.

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Slide 13
BITS Pilani, Dubai Campus Analog & Digital VLSI Design
Dr. Vilas
 Pass Gate or CMOS Transmission gate

➢EX-OR gate using two CMOS TGs.

F = AB + AB

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Slide 14
BITS Pilani, Dubai Campus Analog & Digital VLSI Design
Dr. Vilas
Pass Gate or CMOS Transmission gate

➢Implement the Boolean function using Pass gate or TG

F = AB + AC + ABC

F = AB + AC + ABC

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Slide 15
BITS Pilani, Dubai Campus Analog & Digital VLSI Design
Dr. Vilas