RANIPPETTAIENGINEERINGCOLLEGE

T.K.THANGAL
WALAJAH TALUK,VELLORE DISTRICT-632 513

PX4211 Power Electronics and Drives Laboratory

DEPARTMENT
OF
ELECTRICAL&ELECTRONICSENGINEERING
 RANIPPETTAIENGINEERINGCOLLEGE
T.K.THANGAL
WALAJAHTALUK,VELLOREDISTRICT-632513

CERTIFICATE

This is certified to be the Bonafide Record of work done by

With REG.NO of First
Year/ II Semester in PX 4211 Power Electronics Drives Laboratory during the
academic year 2023-2024.

HEADOFTHEDEPARTMENT SIGNATUREOFLAB-IN-CHARGE

Submitted for the Anna University Practical Examination held on for

PX 4211 Power Electronics Drives Laboratory

INTERNALEXAMINER EXTERNALEXAMINER
 INDEX

PAGE
S.NO DATE EXPERIMENTS SIGN
NO.
PINDIAGRAMOFIC7408:

PINDIAGRAMOFIC7432:

PINDIAGRAMOFIC7404:

PINDIAGRAMOFIC7486:
Ex.No.1
IMPLEMENTATIONOFBOOLEANFUNCTIONS,ADDER/SUBTRACTORCIRCUITS

AIM:
(a) TominimizeBooleanfunctionsusingK-map andtoimplementthesameinPOS and
SOP forms using basic gates.
(b) Todesign and verifythetruth table oftheAdder &Subtractor circuits.

APPARATUSREQUIRED:

Sl.No Component Specification Quantity

1 ANDGATE IC 7408 1
2 X-ORGATE IC 7486 1
3 NOTGATE IC7404 1
4 OR GATE IC7432 1
5 ICTRAINERKIT - 1
6 PATCHCORDS - As required

PROCEDURE:

1. Connectionsaregivenasperthecircuitdiagrams.
2. Forallthe IC’s7thpinisgroundedand 14thpinis connectedto+5Vsupply(VCC).
3. Applythe inputs andverifythe truth tablefortherespectivelogic circuits.
INTRODUCTION:

HALFADDER:
Acombinationalcircuitwhichperformstheaddition oftwobitsiscalledhalf adder.
Theinputvariablesdesignatetheaugendandtheaddendbit,whereastheoutputvariables
producethesum andcarrybits.

FULLADDER:
Acombinationalcircuitwhichperformsthearithmeticsumofthreeinputbitsiscalled full
adder.The three input bits include two significant bits and a previous carry bit.A full adder
circuit can be implemented with two half adders and one OR gate.

HALFSUBTRACTOR:
Acombinationalcircuitwhichperformsthesubtractionoftwobitsiscalledhalfsubtractor.Thei
nputvariables designatetheminuendandthesubtrahendbit,whereas the output variables produce
the difference and borrow bits.
FULLSUBTRACTOR:
Acombinationalcircuitwhichperformsthesubtractionofthreeinputbitsiscalled
fullsubtractor.Thethree inputbitsincludetwosignificantbitsandapreviousborrowbit.A full
subtractor circuit can be implemented with two half subtractors and one OR gate.
i. MINIMIZATIONOFBOOLEANFUNCTIONINSOP
TRUTH TABLE – SOP:
Input Output
A B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

SUMOF PRODUCTS:
F=∑m(2, 3,5, 7, 9,11,12, 13, 14)

CD
00 01 11 10
AB

00 1 1

01 1 1

11 1 1 1

10 1 1

F ABC ABD ABD ABC ABD

LOGICDIAGRAM–SOP:

A B C D

ii. PRODUCTOFSUMS:

TRUTH TABLE – POS:

Inputs Outputs
A B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
 CD
00 01 11 10
AB

0 0
00

01 0 0

11 0

10 0 0

F A B C . A B D . A B C D . A B

LOGICDIAGRAM–POS:
IMPLEMENTATIONOFHALFADDER,FULLADDER,HALFSUBTRACTOR AND
FULL SUBTRACTOR CIRCUITS:

HALFADDER:

TRUTHTABLE:

Inputs Output
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

DESIGN:

Fromthetruthtabletheexpressionforsumandcarrybitsoftheoutputcan beobtainedas, Sum, S =

A B
Carry,C=A.B

SUM:
CARRY:

Sum=(A.B AB) A Carry=A.B

B
LOGICDIAGRAMOFHALFADDER:

FULLADDER:
TRUTHTABLE:
Inputs Output
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

DESIGN:

Fromthetruthtabletheexpressionforsumandcarrybitsoftheoutputcan beobtainedas, SUM =

A’B’C + A’BC’ + AB’C’ + ABC
CARRY=A’BC+ AB’C+ABC’ +ABC
UsingKarnaughmaps thereducedexpression for the outputbitscan beobtained as,
SUM

BC
00 01 11 10
A

1 1
0

1 1 1

Sum (A.B.C A.B.C A.B.C A.B.C)

A B C
CARRY

BC
00 01 11 10
A

0 1

1 1 1 1

CARRY= AB+ AC+BC

LOGICDIAGRAMOFFULLADDER:
HALFSUBTRACTOR:

TRUTHTABLE:

Inputs Output
A B Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

DESIGN:
Fromthetruthtabletheexpressionfordifferenceandborrowbitsoftheoutputcanbe obtained as,
Difference,DIFF=A B Borrow,
BORR = A’. B

LOGICDIAGRAMOFHALFSUBTRACTOR:

FULLSUBTRACTOR:

TRUTHTABLE:

Inputs Output
A B C Difference Borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

DESIGN:

Fromthetruthtabletheexpressionfordifferenceandborrowbitsoftheoutputcanbe obtained as,

 Difference=A’B’C+A’BC’+AB’C’+ABC
Borrow = A’BC + AB’C + ABC’ +ABC
UsingKarnaughmaps thereducedexpression for the outputbitscan beobtained as,

DIFFERENCE

BC
00 01 11 10
A

1 1
0

1 1 1

DIFFERENCE (A.B.C A.B.C A.B.C A.B.C)

A B C
BORROW

BC
00 01 11 10
A

1 1
0

1 1 1

BORROW B.C A(B C)

LOGICDIAGRAMOFFULLSUBTRACTOR:
RESULT:
(a) TheminimizationofBooleanfunctionsusingK-mapisperformedandsameis
implementedin POSand SOPforms usingbasicgates.
(b) ThedesignoftheAdderandSubtractorcircuitswasdoneandthecorresponding truth
tables were verified.
LOGICDIAGRAMOFEXCESS– 3TOBCDCONVERSION

A B C D
Ex.No.2
CODECONVERTERS
Date:

AIM:

To construct logicdiagram and to verifythe truthtablefor,

(a) Excess-3to BCDcodeconverter
(b) BCDto Excess-3codeconverter
(c) BinarytoGraycodeConverter
(d) GraytoBinarycodeconverter

INTRODUCTION:
Code converter is a circuit that makes two systems compatible even though each uses
differentbinarycodes.Thereisawidevarietyof binarycodesusedindigitalsystems.Some of these
codes are Binary Coded Decimal, Gray code, Excess- 3 code , ASCII code, etc.

APPARATUSREQUIRED:

Sl.No Component Specification Quantity

1 ANDGATE IC7408 1
2 X-ORGATE IC7486 1
3 NOTGATE IC7404 1
4 ORGATE IC7432 1
5 ICTRAINERKIT - 1
6 PATCHCORDS - As required

PROCEDURE:
Thelogiccircuitis designedusingK map.

Gatesaredecided forthelogic circuit.

Connectionsaremadeasperthelogicdiagrams. Truth
tables are verified.
EXCESS-3TOBCDCONVERTER:

TRUTH TABLE:

Excess–3 input BCDoutput

A B C D B3 B2 B1 B0

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1
K-MAP:EXCESS – 3TO BCD

B3:

CD
00 01 11 10
AB

00 0

01 0 0 0 0

11 1 x x x

10 0 0 1 0

B3=AB+ABC=A(B+BC)
B2:

CD
00 01 11 10
AB

00 x x 0 x

01 0 0 1 0

11 0 x x x

10 1 1 0 1

B2=BD BC BCD

B2=B(C D) C D
=B
BCD
B1:

CD
00 01 11 10
AB

00 x x 0 x

01 0 1 x 1

11 0 x x x

10 x 1 0 1

B1=CD CD C D

B0:

CD
00 01 11 10
AB

00 x x 0 x

01 1 0 0 1

11 1 x x x

10 1 0 0 1

B0=D
BCDTOEXCESS-3CONVERTER:

TRUTH TABLE:

BCDinput Excess–3 output

A B C D X1 X2 X3 X4

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 x x x x

1 0 1 1 x x x x

1 1 0 0 x x x x

1 1 0 1 x x x x

1 1 1 0 x x x x

1 1 1 1 x x x x
X4:

CD
00 01 11 10
AB

00 1 1

01 1 1

11 x x x x

10 1 x x

X4 =D

X3:

CD
00 01 11 10
AB

00 1 1

01 1 1

11 x x x x

10 1 x x

X3=CD CD
=
C D
X2:

CD
00 01 11 10
AB
00 1 1 1

01 1

11 x x x x

10 1 x x

X2=BCD BCD =B C D
BC

X1:

CD
00 01 11 10
AB

00

01 1 1 1

11 x x x x

10 1 1 x x

X1=A BD =A+ B(C+D)

BC
LOGIC DIAGRAM:

A B C D

BINARYTOGRAYCODECONVERTER TRUTH

TABLE:

BINARYCODE GRAY CODE

A B C D G1 G2 G3 G4

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0
 1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

K-MAP:BINARYTO GRAY

G1:
CD
00 01 11 10
AB

00

01

11 1 1 1 1

10 1 1 1 1

G1=A
G2:

CD
00 01 11 10
AB

00

01 1 1 1 1

11

10 1 1 1 1

G2 A.B A.B A B
G3:

G3 B.C B.C B C
G4:

CD
00 01 11 10
AB

00 1 1

01 1 1

11 1 1

10 1 1

G4 C.D C.D C D
LOGIC DIAGRAM:
GRAYTOBINARYCODECONVERTER: TRUTH

TABLE:

GRAYCODE BINARYCODE

A B C D B1 B2 B3 B4

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 1 0

1 0 0 1 1 1 1 1

1 0 1 0 1 1 0 1

1 0 1 1 1 1 0 0

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 0 1 0 1 1

1 1 1 1 1 0 1 0
K-MAP:
B1:

CD
00 01 11 10
AB

00

01

11 1 1 1 1

10 1 1 1 1

B1=A

B2:

CD
00 01 11 10
AB

00

01 1 1 1 1

11

10 1 1 1 1

B2=AB AB A B
B3:

CD
00 01 11 10
AB

00 1 1

01 1 1

11 1 1

10 1 1

B3=ABC ABC ABC =A B C

ABC

B4:

CD
00 01 11 10
AB

00 1 1

01 1 1

11 1 1

10 1 1

B4=A B C D
LOGIC DIAGRAM:
RESULT:

Thusthelogicdiagramsareconstructed andtruthtablesareverifiedfor,

(a) Excess-3toBCD
(b) BCDtoExcess-3
(c) BinarytoGraycodeConverter
(d) GraytoBinarycodeconverter
Ex.No.3
PARITYGENERATORANDPARITYCHECKER
Date:

AIM:
Toconstructlogiccircuitand toverifythe truthtable for:
(a) Odd ParityGenerator
(b) OddParityChecker
(c) Even Parity Generator
(d) Even ParityChecker

INTRODUCTION:
A parity bitis used for the purpose of detecting errors during transmission of binary
information.Aparitybitisanextrabitincludedwithabinarymessagetomakethenumberof
1’seitheroddoreven.Themessageincludingtheparitybitistransmittedandthen checked at the
receiving end for errors.An error is detected if the checked parity does not correspond with the
one transmitted.The circuit that generates the parity bit in thetransmitter is called a parity
generator and the circuit that checks the parity in the receiver is called a parity checker.

APPARATUSREQUIRED:

Sl.No Component Specification Quantity

1 X-ORGATE IC 7486 1
2 NOTGATE IC 7404 1
3 ICTRAINERKIT - 1
4 PATCHCORDS - As required

PROCEDURE:

Thelogic circuitis designedusingK map.

Gatesaredecidedforthelogic circuit.

Connectionsaremadeasperthelogic diagrams.
Applythe inputs andverifythe truth tablefortheParitygenerator andchecker.
 ODDPARITYGENERATOR:

TRUTHTABLE:

INPUT OUTPUT

A B C P
0 0 0 1

0 0 1 0
0 1 0 0

0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1

1 1 1 0

K-MAP:ODDPARITYGENERATOR:

BC
00 01 11 10
A

0 1 1

1 1 1

P= A B C+ A BC +A BC +AB C

P= A B C

LOGIC DIAGRAM:
ODDPARITYCHECKER:
TRUTH TABLE:

INPUT OUTPUT
A B C D(P) P
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

K-MAP:ODDPARITYCHECKER

CD
00 01 11 10
AB

00 1 1

01 1

11 1 1

10 1 1

X= A B C P
 ODDPARITYCHECKER

EVENPARITYGENERATOR:

TRUTH TABLE:

INPUT OUTPUT
A B C P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

K-MAP:EVENPARITYGENERATOR

BC
00 01 11 10
A

0 1 1

1 1 1

P =A B C
LOGIC DIAGRAM:

EVENPARITYCHECKER:
TRUTH TABLE:

INPUT OUTPUT
A B C D(P) P
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
K-MAP:EVENPARITYCHECKER

CD
00 01 11 10
AB

00 1 1

01 1 1

11 1 1

10 1 1

P =A B C D

LOGIC DIAGRAM
RESULT:
Thusthelogiccircuitsareconstructedandtruthtablesareverifiedfor:
(a) Odd ParityGenerator
(b) OddParityChecker
(c) Even Parity Generator
(d) Even ParityChecker
Ex.No.4
ENCODERSANDDECODERS
Date:

AIM:
a) Todesignand implementencoder usingIC 74148(8-3 encoder)
b) Todesignand implementdecoder usingIC 74155(3-8 decoder)

INTRODUCTION:
ENCODER:
An encoder is digital circuit that has 2n input lines and n output lines. Theoutput lines
generateabinarycodecorrespondingtotheinputvalues8 -3encodercircuithas8inputs,one
foreachoftheoctaldigitsandthreeoutputsthatgeneratethecorrespondingbinary
number.EnableinputsE1shouldbeconnectedtogroundandEoshouldbeconnected to VCC.
DECODER:
A decoder is a combinational circuit that converts binary information fromn input
linesto 2nunique output lines. In3-8 line decoder the three inputsare decoded into right outputs
in which each output representing one of the minterm of 3 input variables.

APPARATUSREQUIRED:

S.No Components Specification Quantity

1 Encoder IC74148 1
2 Decoder IC74155 1
3 ORgate IC7432 3
4 ANDgate IC7408 5
5 NOTgate IC7404 1
6 DigitalICTrainerKit - 1
7 Patchchords - As required

PROCEDURE:

Connectionsaregivenasperthelogicdiagram.
Thetruth table is verified byvaryingthe inputs.
TRUTHTABLE-ENCODERS

INPUTS OUTPUTS
A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1

PINDIAGRAM:ENCODER

A3 1 16
+5 volt
A2 2 15
INPUT
A1 3 14 G3NOCONNECT

A0 4 13 A7

E1 5
IC74148 12 A6
INPUT
D2 6 11 A5
OUTPUT
D1 7 10 A4

GND 8 9 D0 OUTPUT
 BLOCKDIAGRAMOF8-3ENCODER:

A0 A1

A2 D0

A3 D1
8-3 ENCODER
A4 D2

A5
A6

A7

CIRCUITDIAGRAM OF8-3ENCODER:

A7 A6 A5 A4 A3 A2 A1 A0

D0

D1

D2
TRUTHTABLE– DECODERS:

INPUTS OUTPUTS
D0 D1 D2 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0

PINDIAGRAM:DECODER

C1 9 2Y0
1

C C2 10 2Y1
15
11 2Y2
B 3
12 2Y3
A 13

G1
IC74155 7 1Y0

2 6 1Y1

5 1Y2
G G2 14
4 1Y3

8 16 +VCC
GND
BLOCKDIAGRAMOF3-8DECODER

A0
A1
A2
D0
A3
D1 3-8DECODER
A4
D2
A5
A6
A7

CIRCUITDIAGRAM OF3-8DECODER
A2 A1 A0

A0

A1

A2

A3

A4

A5

A6

A7
RESULT:
Thusthelogicdiagramswereconstructedandthetruthtablesareverifiedfor8to3 line
Encoder and 3 to 8 line Decoder.
Ex.No.5
COUNTERS
Date: CTION:

AIM:
Toimplementandverifythetruthtableofsynchronousandasynchronouscounter.

APPARATUSREQUIRED:

S. No Components Range Quantity

1. DigitalICtrainerkit 1
2. JK FlipFlop IC7473 2

4. NANDgate IC7400 1

5. ANDgate IC7408 1
6. Connecting wires As required

PROCEDURE:

Connectionsaregivenasperthelogicdiagram.

Thetruth table is verified byvaryingthe inputs.

CIRCUITDIAGRAM (ASYNCHRONOUSCOUNTER):
CIRCUITDIAGRAM (ASYNCHRONOUSCOUNTER):
+VCC
14
1 3

2
7
VCC GND VCC GND
4 11 4 11

14 12 7 14 12 7
J Q J Q 9 J Q J Q 9

1 CLK 5 CLK 1 CLK 5 CLK

7473 7473 7473 7473

3 10 3 10
K K K K

2 6 2 6

A B C D
LSB MSB
TRUTHTABLE:
Clock Output Decimal

Count QD QC QB QA Value

1 0 0 0 0 0
2 0 0 0 1 1
3 0 0 1 0 2
4 0 0 1 1 3
5 0 1 0 0 4
6 0 1 0 1 5
7 0 1 1 0 6
8 0 1 1 1 7
9 1 0 0 0 8
10 1 0 0 1 9
11 CounterResetsits outputbackto zero
 PINDIAGRAMOFIC7473:

Acounterisaregistercapableofcountingnumberofclockpulsearrivingatits
clockinput.Counterrepresentsthenumberofclockpulsesarrived.Anup/down
counterisonethatiscapableofprogressinginincreasingorder ordecreasingorder through a certain
sequence. An up/down counter is also called bidirectional counter.Usually up/down operation
of the counter is controlled by up/down signal. When this signal is high counter goes through
up sequence and when up/down signal is low counter follows reverse sequence.
TRUTHTABLE:
Clock Output Decimal
Count QD QC QB QA Value

1 0 0 0 0 0
2 0 0 0 1 1
3 0 0 1 0 2
4 0 0 1 1 3
5 0 1 0 0 4
6 0 1 0 1 5
7 0 1 1 0 6
8 0 1 1 1 7
9 1 0 0 0 8
10 1 0 0 1 9
11 1 0 1 0 10
12 1 0 1 1 11
13 1 1 0 0 12
14 1 1 0 1 13
15 1 1 1 0 14
16 1 1 1 1 15
17 CounterResetsits outputbackto zero
RESULT:
ThetruthtableofAsynchronouscounterand Synchronouscounterwas verified.
Ex.No.6
SHIFTREGISTERS
Date:
INTRODUCTION:

The Shift Register is another type of sequential logic circuit that can be used for the
storage or the transfer of data in the form of binary numbers. This sequential device loads the
data present on its inputs and then moves or “shifts” it to its output once every clock cycle,
hence the name “shift register”. A register capable of shifting its binary information either to
the left or to the right is called a shift register.The logical configuration of a shift register
consists of a chain of flip flops connected in cascade with the output of one flip flopconnected
to the input of the next flip flop.All the flip flops receive a common clock pulse which causes
the shift from one stage to the next.

ANNAUNIVERSITY QUESTIONS
1.Designandconstructa4-bitshiftregisterinSISO,SIPO,PISOandPIPO
modesusingsuitableICs.
(100)
2. Design &constructa 4bit Serial inserialout shiftregister. (100)
3. Design &constructa4bitSerialinparalleloutshiftregister. (100)
4. Design &constructa4bitParallelinserialoutshiftregister. (100)
5. Design &constructa 4bitParallelinparalleloutshiftregister. (100)

AIM:
Toimplement thefollowingshift register usingflip flop

(i) SIPO (ii) SISO (iii) PISO (iv) PIPO

PINDIAGRAM IC7474:
+VCCCLR2 D2CLKPR2 Q2

14 13 12 11 10 9 8

IC 7474
1 2 3 4 5 6 7

CLR 1 D1 CLK PR1 Q1 GND

SIPO-LEFTSHIFT:

+5 VCC
Q2 Q1 Q0

10 4 10 4 DIN
12 5 2 9 12 5 2

9IC 7474 IC 7474 IC 7474 IC 7474

11 3 11 3
13 1 13 1

+5 VCC
CLK

APPARATUSREQUIRED:

S. No Component Specification Quantity

1. IC 7474 1
2. DigitalICTrainerKit 1
3. Patchchords -

PROCEDURE:

Givetheconnectionsasperthecircuit.

Setor Resetat pinno:2which istheMSBofserial data

Applyasingle clock Setor Resetseconddigital inputatpin no:2.

Repeatstep2 untilall4-bitdata aretaken away.

VERIFICATION TABLE:
No of clock Serialinput Din Paralleloutput
pulse Q3 Q2 Q1 Q0
0 0 0 0 0 0
1 1 0 0 0 1
2 1 0 0 1 1
 3 0 0 1 1 0
4 1 1 1 0 1
5 0 1 0 1 0
6 0 0 1 0 0
7 0 1 0 0 0
8 0 0 0 0 0
SIPO-RIGHT SHIFT:
Q3 Q2 Q1 Q0
+5 VCC

10 DIN 4 10 4
12 5 2 9 12 5 2

9IC7474 IC7474 IC7474 IC7474

11 3 11 3
13 1 13 1

+5 VCC
CLK

VERIFICATION TABLE:

Noof clock pulse SerialinputDin Paralleloutput

Q3 Q2 Q1 Q0
0 0 0 0 0 0
1 1 1 0 0 0
2 1 0 1 0 0
3 0 1 0 1 0
4 1 1 1 0 1
5 0 0 1 1 0
6 0 0 0 1 1
7 0 0 0 0 1
8 0 0 0 0 0
SISO:

DOUT

+5VCC

10 4 10 4 DIN
12 5 2 9 12 5 2

9IC7474 IC7474 IC7474 IC7474

11 3 11 3
13 1 13 1

+5VCC

CLK

VERIFICATION TABLE:

Datainput= 1100

Clock Serial input Serial output

0 0 0
4 1 1
8 1 1
12 0 0
16 0 0

PIPO:

Q3 Q2 Q1 Q0
+5VCC

10 4 10 4
12 5 2 9 12 5 2

9IC7474 IC7474 IC 7474 IC7474

11 3 11 3
13 1 13 1

+5VCC
CLK

A B C D
VERIFICATION TABLE:

Clock Parallelinput Paralleloutput

A B C D QA QB QC QD
0 0 0 0 0 0 0 0 0

1 1 1 0 1 1 1 0 1

PISO:
RESULT:
ThustheSISO,SIPO,PISO,PIPOshiftregisters weredesignedandimplemented.
 a) 2:1 MULTIPLEXER:

S0 O/P
S0
I0 0

0 I0
O/P
1 I1
I1 1

LOGIC DIAGRAM:

IC7408

IC7432

O/P

IC7408

b) 1:2 DE MULTIPLEXER:

S0 I/Pat
S0

0 O0
0 O0
I/P

1 O1
1 O1
Ex.No.7
MULTIPLEXERANDDEMULTIPLEXER
Date:

AIM:
Toconstruct thelogic diagram andverifythe truthtable for:

(a) 2:1 Multiplexer

(b) 1: 2 Demultiplexer
(c) 4:1 Multiplexer.
(d) 1: 4 Demultiplexer.

APPARATUSREQUIRED:

Sl.No Component Specification Quantity

1 X-ORGate IC7486 1
2 NOTGate IC7404 1
3 ANDGate IC7408 1
4 OR Gate IC7432 1
5 ICTRAINERKIT - 1
6 PATCHCORDS - As required

INTRODUCTION:

Multiplexerisadigitalswitchwhichallowsdigitalinformationfromseveralsourcesto be
routed onto a single output line.The basic multiplexer has several data input lines and a single
output line.The selection of a particular input line is controlled by a set of selection
lines.Normally, there are 2n input lines and n selector lines whose bit combinations determine
which input is selected.Therefore, multiplexer is ‘many into one’ and it provides the digital
equivalent of an analog selector switch.

ADemultiplexerisacircuitthatreceivesinformationonasinglelineandtransmitsthis
information on one of 2n possible output lines.The selection of specific output line is
controlled by the values of n selection lines.
LOGIC DIAGRAM:

IC7408

I/P

IC7408

a) 4:1 MULTIPLEXER:

S0 S1 O/P

S0S1
0 0 I0
I0I 00 0 1 I1

1 01 1 0 I2
O/P
1 1 I3
I2I 10

3 11

PROCEDURE:
1. Connectionsaremadeas perthelogicdiagram.
2. Thetruth tablesareverified.
LOGIC DIAGRAM:

S0 S1

IC7404
IC7408

I0 IC7486

I1

IC7432

O/P

I2

I3

b) 1:4 DE MULTIPLEXER:

S0S1

O0 I/P S0 S1 O0 O1 O2 O3
1 X 0 0 0 0 0
01_______O1
I/P 0 0 0 0 0 0 0
10 _______O2
0 0 1 0 1 0 0
11 _______O3
0 1 0 0 0 1 0
0 1 1 0 0 0 1
LOGIC DIAGRAM:

S0 S1 I/P

IC7404
IC7408

O0

O1

O2

O3
RESULT:
Thuslogicdiagramsare constructedandtruthtablesareverifiedfor
(a) 2:1 Multiplexer
(b) 1: 2 Demultiplexer
(c) 4:1 Multiplexer.
(d) 1: 4 Demultiplexer.
PINDIAGRAM:

Ground 1 8 VCC

Trigger 2 7 Discharge
IC LM555
Output 3 6 Threshold

Control
Reset 4 5 voltage
Ex.No.8
TIMERIC(555)APPLICATION
Date:

AIM:
(a) TodesignandobtaintheMonostablemultivibratorusingIC555timerfor the given
time period.
(b) TodesignandobtaintheAstablemultivibratorusingIC555timerforthe given time
period.
Todesignandtestanastablemultivibratorforgeneratingsymmetricaland
unsymmetricalsquarewaveform forthe given frequencyand dutycycle.

APPARATUSREQUIRED:
S.No. Components Range Quantity
1 ICLM555Timer 1
2 Resistor 10KΩ 1
3 Capacitor 0.01µF, 1
4 Capacitor 0.1µF 1
5 RPS (0-30)V 1
6 CRO 1
7 FunctionGenerator 1
8 BreadBoard 1
9 ConnectingWires

THEORY:
The555timerisconnected asan astablemultivibratoras shownin figure.

In this mode of operation the timing capacitorcharges up towards Vcc(assuming

Voishighinitially)through(Ra+Rb)untilthevoltageacrossthecapacitorreaches the
threshold level (2/3) Vcc. At this pointthe internal upper comparator switches
statecausingtheinternalflip-flopoutputtogohigh.Thisturns onthe discharge transistor
and the timing capacitor C then discharges through Rb and the discharging
transistor. The discharging continues until the capacitor voltage drops to (1/3) V cc at
which point the internal lower comparator switches states causing the internal flip-
flopoutputtogolow,turningoff thedischargetransistor.Atthispointthe capacitor starts to
charge again, thus completing the cycle.
a) MONOSTABLEMULTIVIBRATOR:

CIRCUIT DIAGRAM:

Model Graph:
INTRODUCTION:
ASTABLE MULTIVIBRATOR:
Anastablemultivibrator,oftencalledafree-runningmultivibrator,isarectangular-wave-
generating circuit.This circuit does not require an external trigger to change the state of the
output.The time during which the output is either high or low is determined by two resistors
and a capacitor, which are connected externally to the 555 timer.The time during which the
capacitor charges from 1/3 Vcc to 2/3 Vccis equal to the time the output is high and is givenby,
tc=0.69(R1+R2)C
Similarlythetimeduringwhichthecapacitordischargesfrom2/3V ccto1/3Vccisequaltothe time the
output is low and is given by,
td=0.69(R2)C
Thusthe total timeperiod oftheoutput waveform is,
T=tc +td =0.69(R1 +2R2)C
%dutycycle =[(R1 +R2) /(R1 +2 R2)] x100

MONOSTABLE MULTIVIBRATOR:
A monostable multivibrator often called a one-shot multivibrator is a pulse generating circuit
inwhichthedurationofthepulseisdeterminedbytheRCnetworkconnectedexternallytothe 555
timer.In a stable or stand-by state the output of the circuit is approximately zero or at logic
low level.When an external trigger pulse is applied, the output is forced to go high (approx.
Vcc).The time during which the output remains high is given by,

tp=1.1R1C

DESIGN:
i. ForUnsymmetricalwaveform:
f =1/T=1.44/(Ra+2Rb)C;
DutyCycle=D=tlow/(tlow +thigh)=> D= R b/
(Ra +2Rb) ;
Wherethigh=0.693(Ra+Rb)C;tlow =0.69;
Specifications:frequency = 1kHz;
Dutycycle =25%Design:
tlow=0.25ms=0.693R bC;
LetC=0.1µF=>Rb =0.25/(0.693X0.1X10-6) =
thigh =0.693(Ra+Rb)C= 0.75ms=>Ra=
ii. ForSymmetricalWaveform:
thigh =0.693RaC;tlow=0.693RbC
f=1/T =1.44 /(Ra+Rb)C =>D=Rb/(Ra+Rb);

Specifications:frequency=1 kHz; Dutycycle

=50%.Design:tlow =0.5ms=0.693RbC; Let
C= 0.1 µF; R b=
thigh =0.693RaC=0.5ms;Ra=
DESIGN:
ConsiderVCC=5V,forgiventpOutputpulsewidthtp=1.1RAC Assume
C in the order of microfarads & Find RA
Typicalvalues:
IfC=0.1μF,RA=10kthentp=1.1mSec,TriggerVoltage=4 V

TABULAR COLUMN:

VOLTAGE CHARGINGTIME
S.NO. DISCHARGING TIME
(VOLTS) TC(SEC)
TD(SEC)

PROCEDURE:
1.Connectionsaregivenasperthecircuitdiagram.
2.+5Vsupplyisgiventothe+VccterminalofthetimerIC.
3. Anegativetriggerpulseoflessthan(1/3VCC)i.eGroundtopin2ofthe555IC
4. Atpin3theoutputtimeperiodisobservedwiththehelpofaLEDorCRO
5. Atpin6thecapacitorvoltageisobtainedintheCROandtheV0andVcvoltagewaveforms are
plotted in a graph sheet.
b) ASTABLE MULTIVIBRATOR:

Model Graph:

VCC
V0
0V t

VC
t

DESIGN:
Givenf=4 KHz,
Therefore,Totaltimeperiod,T=1/f= We
know, duty cycle = tc /T
Therefore,tc= and td =
Wealsoknowforanastablemultivibrator,td=0.69(R2)C Therefore,
R2 = -------------
tc=0.69(R1+R2)C
Therefore,R1=--------------
TABULAR COLUMNS:

VOLTAGE TON( TOFF

S.No.
(VOLTS) mS) (mS)

V1(V V2(V TC( TD(

S.No.
OLTS) OLTS) mS) mS)
RESULT:
Thusthemonostablemultivibratorandastablemultivibratorusing555timerforthe given time
period was designed and waveforms are obtained.
CIRCUIT DIAGRAM:

PINDIAGRAM:
Ex.No.9
APPLICATIONSOFOP-AMP
Date:

AIM:
(a) Todesignandtestthe operationofinvertingamplifier.
(b) Todesign andtesttheoperationofNon-invertingamplifier.
(c) Todesignandtestthe operationofsummingamplifier.
(d) Todesignandtestthe operationofIntegrator.
(e) Todesign andtestthe operationofDifferentiator.
(f) Todesign andtestthe operationofComparator.

APPARATUSREQUIRED:

S.No. Nameof the Item Range Qty

1 IC741 1
2 Resistors 1M ,1k ,10K ,100 ,2.5K ,5.2K
2
3 Capacitors 0.01 F,0.005 F
4 DualPowerSupply 2 1
5 RPS 1
6 FunctionGenerator 1
7 CRO 1
8 BreadBoard 1
MODELGRAPH:

Vin(
volts)

V0
(volts)

t
INTRODUCTION:
Inverting Amplifier:
The fundamental component of any analog computer is the operationalamplifier or op-
ampandthefrequencyconfigurationinwhichitisusedasaninvertingamplifier.
AninputvoltageVinisappliedtotheinputvoltage.Itreceivesandinvertsitspolarityproducing
anoutputvoltage.ThissameoutputvoltageisalsoappliedtoafeedbackresistorR f,whichis
connectedtotheamplifierinputanalogwithR1.Theamplifieritselfhasaveryhigh voltage gain.
Non-InvertingAmplifier:
Although the standard op-amp configuration is as an inverting amplifier,there are
some applications where such inversion is not wanted. However, we cannot justswitch the
inverting and non-inverting inputs to the amplifier itself.
SummingAmplifier
The Summing Amplifieris a very flexible circuitbased upon the standard Inverting
OperationalAmplifierconfiguration.Wesawpreviouslythattheinvertingamplifierhasa
singleinput signal applied to the inverting input terminal.
Differentiator:
Op-ampsallowustomakenearlyperfectintegratorssuchasthepractical integrator the
circuit incorporates a large resistor in parallel with the feedback
capacitor.Thisisnecessarybecauserealop-amps haveasmallcurrentflowingattheirinput
terminals called the "bias current".The feedback resistor gives a path for the biascurrent
to flow.The effectoftheresistorontheresponseisnegligibleatallbutthelowestfrequencies.
Integrator:
One of the simplest of the operational amplifier that contains capacitor isdifferential
amplifier. Asthesuggests,thecircuitperformsthemathematicaloperationof differentiation. The
output is the derivative of the given input signal voltage. The minus sign indicates a 1800phase
shift of the output waveform Vo with respect to the input signal.

PROCEDURE:
1. Theconnections aremadeas perthecircuit diagram.
2. Theinputsaregivenandtheoutputs areobservedfrom CRO.
3. Incaseofslewratetheinputsinewavesignalisadjustedsothattheoutputisinpeak
timewaveof1KHz,thefrequencyoftheinputisthenincreaseduntiltheoutput is diminished.
4. Incaseofcomparator,thereferencevoltageVrefisvariedandthecorrespondingchange in the
waveforms are observed.
DESIGN:

Vo/Rf=-(Vin/R1)

Then,V0=-
(Rf/R1)*VINRcomp Rf
RinRf/ Rin

LetRin=1kΩ,Rf=1MΩ Rcomp=

1kΩ

TABULARCOLUMN:
DC INPUT:
Vin THEORETICALOUTPUT PRACTICALOUTPUT
(VOLTS) (VOLTS) (VOLTS)

ACINPUT:
Vin Tin V0 T0
(VOLTS) (ms) (VOLTS) (ms)
CIRCUIT DIAGRAM:
Rf=5.6kΩ

+15V
Rin=1kΩ
2 7
+
6
IC741
-
3 4 CRO

Signal -15V
Generator

MODELGRAPH:

Vin(
volts)

V0
(volts)

t
b) NONINVERTINGAMPLIFIER:

DESIGN

V0=(1+Rf/R1)*VIN
Rcomp RinRf/Rin Rf

LetRin=1kΩ,Rf=5.6 kΩ

TABULAR COLUMN:

DCINPUT:

Vin THEORETICALOUTPUT PRACTICALOUTPUT

(VOLTS) (VOLTS) (VOLTS)

ACINPUT:
Vin Tin V0 T0
(VOLTS) (ms) (VOLTS) (ms)
ADDER-CIRCUITDIAGRAM:
Rf=10kΩ

V1 Rin=1kΩ
+15V

V2 Rin=1kΩ 2 7
+
6 V0
R=1kΩ
in IC741
V3
-
3 4

-15V
Rcomp=2.5kΩ

MODELGRAPH

Vm
t

Vm
t

Vm
t

3Vm

V0
t
c) ADDER:

DESIGN:

Vo/Rf=-[V1/R1+V2/R2+V3/R3]

IfR1 = R2= R3 =Rf

ThenVo=-[V1+V2+V3]and

Rcomp=R1||R2||R3|| Rf

IfR1=R2=R3=Rf=10K ,thenR comp =2.5K

TABULAR COLUMN:

Waveform Amplitude(v) Time (mS)

Sine I/P

O/P
INTEGRATOR-CIRCUIT DIAGRAM:

MODELGRAPH:

Vi Vi
(volts) (volts)

V0 V0
(volts) (volts)
t
t
d) INTEGRATOR:

DESIGN:
Inanintegratorcircuit,Fa=Fb/10whereFaisthefrequencyoftheperiodicsignaland Fbis the

break frequency, assuming the values Fa= 1khz, Rf=10K , Fb= 10Khz, R1= 1 K

From which

Fa=1/(2 RfCf)=Cf=1/(2 R1Fa)=>Cf=0.015 f

Fb=1(2 R1Cf)=R1=1(2 Fb Cf)=>R1=1.06K

TABULAR COLUMN:

Waveform Amplitude(v) Time (mS)

Sine I/P

O/P

SquareI/P

O/P
DIFFERENTIATOR-CIRCUIT DIAGRAM:

Cf=0.005µf

Rf=1 .5kΩ

V+
Cf=0.01µf
R1=1 kΩ 2 7

6 V0
IC741

Signal 3 4
Generator
V-

MODELGRAPH:

Vi(v Vi(v
olts) olts)

t t

V0 V0
(volts) (volts)

t t
e) DIFFERENTIATOR:

DESIGN:

Fb=20 Fa, selecting C1=0.1 F(C<1 F) and Fa=1KHZthenFb=20KHZ

From which

Fa =1/(2 Rf C1)=Rf=1/(2 FaC1)=Rf=1.5 K

Fb =1(2 RfCf)=Cf=1/(2 FbRf)=Cf=0.005 F

TABULAR COLUMN:

Waveform
Amplitude(v) Time (mS)

Sine I/P

O/P

SquareI/P

O/P
COMPARATOR-CIRCUITDIAGRAM:

+15V
Rin=1 kΩ
2 7
+
6 V0
IC741
Vi -
3 4
RL=10kΩ
-15V
R1=1kΩ

Vref

MODELGRAPH:

Vpeak

Vref
0V
t

0V
t
f) COMPARATOR:

TABULAR COLUMN:

Waveform Amplitude(v) Time (mS)

Sine I/P

O/P
RESULT:

ThusthecharacteristicsandapplicationsofOp-Amp IC741wereverified.
PINDIAGRAM:

Ground 1 8 +Vcc

NC 2 7 CT
NE/SE566
VCO
Square wave
3 6 RT
output

Trianular Modulated
4 5
waveoutput input

CIRCUIT DIAGRAM:
+VCC

R1

6 8

Rf
4
Modulating
input
5 566
VC
3
R2

7 1

CT

100
Ex.No.10
STUDYOFVCOANDPLLICs
Date:
ODUCTION:

AIM:
(a) Tostudyaboutvoltagecontrolled oscillator.
(b) Tostudyabout Phaselocked loop.

APPARATUSREQUIRED:

S.NO COMPONENT RANGE QUANTITY

1 DigitalICtrainer 1
2 PLL NE565 1
3 VCO NE566 1
4 DecadeCounter IC7490 1
5 Resistor 2K, 4.7K,10K 3
6 Capacitor 0.001μF,0.01μF, 3
10μF
7 SignalGenerator 1
8 POT 20K 1
9 RPS (0-30V) 1
10 Connectingwiresandprobes As required

VOLTAGECONTROLLEDOSCILLATOR:
A common type of VCO available in IC form as NE/SE 566.It consists of a timing
capacitor CT linearly charged or discharged by a constant current source/sink. The amount of
currentcanbecontrolled bychangingthevoltageVcappliedatthemodulatinginput(Pin5)or by
changing the timing resistor Rrexternal to the IC chip. The voltage at Pin 6 is held at the
samevoltageasPin5.Thus,ifthemodulatingvoltageatPin5ismeasured,thevoltageatPin6
alsoincreases,resultinginlessvoltageacross R andthereby decreasingthechanging current.
MONOLITHICPHASELOCKED LOOP:
All the different building blocks of the PLL are available as independent IC packages
and can be externally interconnected tomake a PLL. Moreover a number of manufacturers
have introduced monolithic PLL’s too.
SomeoftheimportantmonolithicPLL’sareSE/NE560seriesintroducedby
signeticsandLM560 seriesbyrational semiconductor.TheSE/NE 560,561,562,564,565 and
567mainlydifferinoperatingfrequencyrange,powersupplyrequirement,frequency and
bandwidth adjustment ranges. SE/NE 565 is the most commonly used PLL.
PINDIAGRAM:
-VCC 1 14 NC

Input 13 NC
2

Input 3 12 NC

VCO 4 NE/SE565 11 NC

VCO 5 10 +VCC

Reference 6 Externalcapacitor
9
for VCO

Demodulate 7 Externalresistor
8
for VCO

CIRCUIT DIAGRAM:
Thesourceandsinkcurrentsareequal,capacitorchargesanddischargesfor,thesame amount of
the time.

Thus∆v= 0.25Vcc
ΔV i
t CT
0.25VCC i
t CT
0.25VCCC T
t
i
Thefrequencyofoscillatorf0 is

f0 =1/t

=1/2∆t
i
0.5VCCCT

VCC VC
i
Rt

b)PHASELOCKED LOOP:

TousePLLasamultipliermakeconnectionsasshowninfigthecircuitusesandbit binary
counter 7490 used as a divide by 5 circuit. Set the lip signal at 1 Vpp square wave at 500 HZ
vary the VCO frequency by adjusting the by adjusting the 20k potentiometer till the PLL is
locked Measure the output frequency it should be 5 times the input frequency repeat steps for
input frequency of 1 KHZ
Fo=1.2/4R1C1

It may be seen that phase locked loop is internally broken between the VCO output and the
phase comparator input. A short circuit between pins 4 and 5 connects the VCO output to the
phase comparator, so as to compare f0with input signal fs. A capacitor C is connectedbetween
Pin 7 and Pin 10 to make a low pass filter with internal resistance of 3.6KΩ.
WAVEFORMS:
RESULT:

Thusthe voltagecontrolledoscillatorand the phaselocked loop were studied.