TEST SCENERIO OF MEMORY CONTROLLER(UVM)

module mem_8bit #(parameter WIDTH=8,DEPTH=16) (input clock,reset,wr_en,[3:0] addr,[7:0] wdata,

integer i;

reg [WIDTH-1:0]mem[DEPTH-1:0];

always@(posedge clock) begin

if(reset)

for(i=0;i<=16;i=i+1) begin

mem[i] <= 0;

rdata <= 0;

end

else begin

if(wr_en)

mem[addr] <= wdata;

else

rdata <= mem[addr];

end

end

endmodule

1.MULTIPLE WRITE AND READ

task body();

repeat(2) begin

repeat(15) begin

`uvm_do_with(pkt,{pkt.wr_en==1;});

end

repeat(15) begin

`uvm_do_with(pkt,{pkt.wr_en==0;});

end
 end

endtask22

2. consecutive write_read

sequence

task body();

repeat(5) begin

`uvm_do_with(pkt,{pkt.wr_en == 1;});

req=pkt;

`uvm_do_with(pkt,{pkt.wr_en == 0; req.addr==pkt.addr;});

end

endtask

3.write and read to particular address

sequence

task body();
 repeat(5) begin

`uvm_do_with(pkt,{pkt.wr_en == 1; pkt.addr==5;});

`uvm_do_with(pkt,{pkt.wr_en == 0; pkt.addr==5;});

end

endtask

4.verify clk&reset

driver

task reset();

vif_h.reset=1;

#10 vif_h.reset=0;

endtask

task drive();

reset();

endtask

5.write into even locator and read from even from even locator

even locator

task body();

int address=0;
 repeat(5) begin

`uvm_do_with(pkt,{pkt.wr_en==1;pkt.addr==(2*address);});

req=pkt;

`uvm_do_with(pkt,{pkt.wr_en==0;req.addr==pkt.addr;});

address++;

end

endtask

odd locator

task body();

int address=0;

repeat(5) begin

`uvm_do_with(pkt,{pkt.wr_en==1;pkt.addr==(2*address+1);});

req=pkt;

`uvm_do_with(pkt,{pkt.wr_en==0;req.addr==pkt.addr;});

address++;

end

endtask

6.check the default read for all the location

repeat(15) begin

`uvm_do_with(pkt,{pkt.wr_en == 0;});

end

endtask

7.constant value for all the location

sequence

task body();

repeat(5) begin

`uvm_do_with(pkt,{pkt.wr_en == 1;pkt.wdata == 5;});

req=pkt;

`uvm_do_with(pkt,{pkt.wr_en == 0;req.addr==pkt.addr;});

end

endtask

8.verify using backdoor access

task body();

int address=4;

repeat(2) begin

repeat(2**address) begin

`uvm_do_with(pkt,{pkt.wr_en==0;});

end

repeat(2**address) begin

`uvm_do_with(pkt,{pkt.wr_en==1;});

end

end

endtask

TEST SCENERIO OF MEMORY CONTROLLER(verilog)

1. Multiple read and write

initial begin

reset=1;

#10 reset=0;

for(i=0;i<16;i=i+1) begin

address=I;

wdata={$random}%200;

end

for(j=0;j<16;j=j+1) begin

address=j;

end
 end

2. consecutive write_read

task automatic wr_task(input a,[7:0]b,[3:0]c);

@(posedge clock) begin

integer i;

for(i=20;i<=400;i=i+1) begin

wr_en=a;

wdata=b;

addr=c;

end

end

endtask

task automatic rd_task(input b);

@(posedge clock) begin

integer i;

for(i=20;i<=400;i=i+1) begin

wr_en=b;

end

end

endtask

initial begin

repeat(15) begin
 wr_task(1,$random%20,$random%15);

#10 rd_task(0);

end

end

3.write and read at a particular address;

initial begin

repeat(5) begin

@(posedge clock)

wr_en=1;

addr={$random}%5;

array=addr;

wdata={$random}%400;

@(posedge clock)

@(posedge clock)

wr_en=0;

addr=array;

end

end
4.multiple writing in randomized address and reading at particular address

initial begin

repeat(5) begin

@(posedge clock)

wr_en=1;

addr={$random}%32;

wdata={$random}%400;

@(posedge clock);

end

begin

@(posedge clock);

wr_en=0;

addr=5;

end

end
4.verify clock and reset

initial begin

clock=0;reset=1;

#50 reset=0;

end

5. write into even locator and read from even from even locator

Even locator

initial begin

for(i=0;i<=15;i=i+1) begin;

if(i%2==0)

begin

@(posedge clock);

wr_en=1;

addr=i;

wdata={$random}%400;

@(posedge clock);

@(posedge clock);

wr_en=0;

addr=i;

end

end

end
Odd locator

initial begin

for(i=0;i<=15;i=i+1) begin;

if(i%2==1)

begin

@(posedge clock);

wr_en=1;

addr=i;

wdata={$random}%400;

@(posedge clock);

@(posedge clock);

wr_en=0;

addr=i;

end

end

end
6.check the default read for all the location

initial begin

for(i=0;i<=15;i=i+1) begin

@(posedge clock);

wr_en=0;

addr=i;

end

end

7.constant value for all the location

Consecutive

initial begin

repeat(5) begin

@(posedge clock);

wr_en=1;

addr={$random}%32;

str=addr;

wdata=5;

@(posedge clock);

wr_en=0;

addr=str;

end

end
Multiple writes and read

initial begin

for(i=0;i<=10;i=i+1) begin

@(posedge clock);

wr_en=1;

wdata=5;

addr=($random)%32;

ary[i]=addr;

end

for(i=0;i<=10;i=i+1) begin

@(posedge clock);

wr_en=0;

addr=ary[i];

end

end
8. rd_wr(rand)_rd(rand) for until 15 clock cycles

task wr_task(input a);

for(i=0;i<=15;i=i+1) begin

@(posedge clock);

wr_en=a;

wdata=i*2;

addr=i;

end

endtask

task rd_task(input b);

for(i=0;i<=15;i=i+1) begin

@(posedge clock);

wr_en=b;

addr=i;

end

endtask

initial begin

repeat(2)begin

rd_task(0);

wr_task(1);

end

end