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Mediatek Interview

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Tejal Adake
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59 views4 pages

Mediatek Interview

Uploaded by

Tejal Adake
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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1.

find the minimal expression for the given logic diagram

((A'+A'B')(B'+B'C'))'
(A'+A'B')'+(B'+B'C')'
A.(A'B')'+B.(B'C')'
A.(A+B)+B(B+C)
A+AB+B+BC
A(1+B)+B(1+C)
A+B

2.what will be the output of the given circuit

1001 0010
1101 1011
219

3.find the highest number in the given array using verilog code

module test;
integer array[9:0];
integer i,j;
integer result;
initial begin
for(i=0;i<10;i=i+1)begin
array[i]=$random%20;
end
for(j=0;j<10;j=j+1) begin
if(j=0)
result=array[0];
else if(array[j]>array[j-1])
result=array[j];
end
end
endmodule

2,8,3,9,12,17,28,19,10,5

4. write verilog code for mod-6 counter

module counter(input clk,rst,output count);


reg [2:0] count;
always @(posedge clk or posedge rst) begin
if(rst)
count <= 3'b0;
else
count <= (count<5)? count+1 :3'b0;
end
endmodule

5. write verilog code for 3:1 mux using conditional operator

module mux(input [2:0]in,input [1:0]sel,output out);


assign out = (sel<3) ? ((~sel[1])&(~sel[0])&in[0]|(~sel[1])&sel[0]&in[1]|
sel[1]&(~sel[0])&in[2]) : 1'bx;
endmodule

6.freq divider 50MHz to 1MHz

module freq_divied(input clk_in,output clk_out);


integer out=0;

always@(posedge clk_in) begin


out=out+1;
if(out==25) out=0;
end

assign clk_out = (out==25)?(~clk_out):clk_out;


endmodule

7.write verilog code for given circuit

module d_ff(input clk,rst,d,output reg q);


always@(posedge clk or posedge rst) begin
if(rst) q<=1'b0;
else q<= d;
end
endmodule

module test(input clk,rst,inout d, output out);


wire q0,q1,q2,q3,x1;
d_ff d_ff0(.clk(clk),.rst(rst),.d(d),.q(q0));
d_ff d_ff1(.clk(clk),.rst(rst),.d(q0),.q(q1));
d_ff d_ff2(.clk(clk),.rst(rst),.d(q1),.q(q2));
d_ff d_dd3(.clk(clk),.rst(rst),.d(q2),.q(q3));
d_ff d_ff4(.clk(clk),.rst(rst),.d(q3),.q(out));
xor xor1(x1,out,q1);
assign d=x1;
endmodule

8.find the duty cycle of y2

q3 q2 q1 q0 y2
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1

duty cycle of y2 is 33.33%

9.what is the output of given circuit

(a'b'i+a'bi)+(ab'i+abi)
(a'i+ai)
i

(c'i')+(c'i) = c'

10. using array locator method find the elements greater than 4

module dyn_array;
int dyn_arr[]='{2,4,6,2,7,82,22,23,14,56,73,84,21};
int result[$];
initial begin
result=dyn_arr.find with (item>4);
$display("the elements greater than 4 are %p",result);
end
endmodule

11. generate some 4bit data reverse it and then send the data to the DUT at every
posedge of clock sequentially

module test;
reg clk,rst;
reg in;
reg [3:0]tmp;
DUT inst(.in(in),.clk(clk),.rst(rst));
initial begin
clk = 1'b0;
forever #2 clk = ~clk;
end
initial begin
rst = 1'b0;
#5 rst = 1'b1;
#100 $finish;
end

initial begin
tmp = {$random};
#1 tmp[0] <= tmp[3];
tmp[1] <= tmp[2];
tmp[2] <= tmp[1];
tmp[3] <= tmp[0];

@(posedge clk) in = tmp[0];


@(posedge clk) in = tmp[1];
@(posedge clk) in = tmp[2];
@(posedge clk) in = tmp[3];
end
endmodule

12. write a verilog code to send 8bit of data to the DUT in which MSB should be
parity

module parity;
reg [6:0]data;
reg [7:0]out;
wire parity;
reg clk;

initial begin
clk = 1'b0;
forever #2 clk = ~clk;
end

initial begin
data ={$random};
#20 $finish;
end
assign parity = ^data;
always@(posedge clk) out = {parity,data};
endmodule
13. what will be the output at f in the given circuit

output at 5->0
output at 7->1
output at 8->a'
output at f is a

14. find the output freq if the input freq is 10KHz

when both q1 and q3 are high then all the flipflops are cleard.So the modulus of
the given counter is 10.hence the frequency is divided by 10

10KHz/10 = 1KHz.

15. find whether the given number is even or odd without using modulus operator

module even_odd(input [7:0]Byte_in,output even,odd);


assign odd=Byte_in[0];
assign even = ~odd;
endmodule

16. write a verilog tb for driving bit data at every posedge of clock when ever
data_fifo_full is low and send_data is high

the data format should be 4bit frame_end,8bit video_data,4bit frame_start


frame_end is 1100
frame_start is 0011
video_data is any random data

module test;
reg [3:0]in;
reg clk;
wire send_data,data_fifo_full;
reg [7:0]video_data;
reg [3:0]frame_end,frame_start;
reg [15:0]tmp;
integer i=0;

initial begin
clk = 1'b0;
forever #2 clk = ~clk;
end
DUT
inst(.in(in),.clk(clk),.send_data(send_data),.data_fifo_full(data_fifo_full));
initial begin
frame_end = 4'b1100;
frame_start = 4'b0011;
video_data = {$random};
tmp = {frame_end,video_data,frame_start};
end

alwaya@(posedge clk) begin


if(send_data==1 && data_fifo_full==0) begin
in <= tmp[i+3:i];
if(i<12) i= i+4;
end
end
endmodule

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