UNIT-III

CPU control unit design: hardwired and micro-programmed design

approaches.
The function of the control unit in a digital computer is to initiate sequences of micro operations.
 Two major types of Control Unit.
i. Hardwired Control Unit: The control logic is implemented with gates, Flip-flops,
decoders, and other digital circuits, then that control unit is said to be Hardwired Control
Unit.
ii. Microprogrammed Control Unit: The control information is stored in a control memory,
and the control memory is programmed to initiate the required sequence of
microoperations is referred as Microprogrammed Control Unit.
 Control Word: The control variables at any given time can be represented by a string of 1’s and
0’s called a control word.
 Microinstruction: The microinstruction specifies one or more microoperations.
 Microprogram: A sequence of microinstruction constitutes a microprogram.
i. Static microprogramming: Here Control Memory = ROM
o The content of the words in ROM are fixed and cannot be altered by simple
programming, since no writing capability is available in the ROM.
o Control words in ROM are made permanent during the hardware production of the
unit.
ii. Dynamic microprogramming: Here Control Memory = RAM
o Microprogram is loaded initially from an auxiliary memory such as a magnetic disk.
o Control units that use dynamic microprogramming employ a writable control
memory. This type of memory can be used for writing (to change the microprogram)
but is used mostly for reading.
 A memory that is part of a control unit is referred to as a control memory.
 A computer that employs a microprogrammed control unit will have two separate memories: a
main memory and a control memory.
 The main memory is available to the user for storing the programs. The contents of main memory
may alter when the data are manipulated and every time that the program is changed. The user's
program in main memory consists of machine instructions and data.
 The control memory holds a fixed microprogram that cannot be altered by the occasional user.
 The general configuration of a microprogrammed control unit is demonstrated in the block
diagram of the following figure 4.
 The control memory is assumed to be a ROM, within which all control information is
permanently stored.

Figure 4: Microprogrammed control organization

 Control address register: The control address register specifies the address of the
microinstruction.
 Control data register: The control data register holds the microinstruction read from memory.
 The microinstruction contains a control word that specifies one or more microoperations for the
data processor. Once these operations are executed, the control must determine the next address.
 The location of the next microinstruction may be the one next in sequence, or it may be located
somewhere else in the control memory. For this reason it is necessary to use some bits of the
present microinstruction to control the generation of the address of the next microinstruction.
 The next address may also be a function of external input conditions. While the microoperations
are being executed, the next address is computed in the next address generator circuit and then
transferred into the control address register to read the next microinstruction.
 The next address generator is sometimes called a microprogram sequencer, as it determines the
address sequence that is read from control memory.
 The address of the next microinstruction can be specified in several ways, depending on the
sequencer inputs.
 Typical functions of a microprogram sequencer are incrementing the control address register by
one, loading into the control address register an address from control memory, transferring an
external address, or loading an initial address to start the control operations.
 The control data register holds the present microinstruction while the next address is computed
and read from memory.
 The data register is sometimes called a pipeline register. It allows the execution of the
microoperations specified by the control word simultaneously with the generation of the next
 microinstruction. This configuration requires a two-phase clock, with one clock applied to the
address register and the other to the data register.
 The other two components: the sequencer and the control memory are combinational circuits and
do not need a clock.
 The main advantage of the microprogrammed control is the fact that once the hardware
configuration is established, there should be no need for further hardware or wiring changes. If
we want to establish a different control sequence for the system, all we need to do is specify a
different set of microinstructions for control memory.
 The hardware configuration should not be changed for different operations, the only thing that
must be changed is the microprogram residing in control memory.

Address Sequencing
 Microinstructions are stored in control memory in groups, with each group specifying a routine.
 Each computer instruction has its own microprogram routine in control memory to generate the
microoperations that execute the instruction.
 An initial address is loaded into the control address register when power is turned on in the
computer. This address is usually the address of the first microinstruction that activates the
instruction fetch routine.
 The control memory next must go through the routine that determines the effective address of the
operand.
 The effective address computation routine in control memory can be reached through a branch
microinstruction, which is conditioned on the status of the mode bits of the instruction.
 The next step is to generate the microoperations that execute the instruction fetched from
memory.
 The transformation from the instruction code bits to an address in control memory where the
routine is located is referred to as a mapping process.
 Once the required routine is reached, the microinstructions that execute the instruction may be
sequenced by incrementing the control address register.
 When the execution of the instruction is completed, control must return to the fetch routine. This
is accomplished by executing an unconditional branch microinstruction to the first address of the
fetch routine.
 The address sequencing capabilities required in a control memory are:
1. Incrementing of the control address register.
2. Unconditional branch or conditional branch, depending on status bit conditions.
 3. A mapping process from the bits of the instruction to an address for control memory.
4. A facility for subroutine call and return.
 The following figure 5 shows a block diagram of a control memory and the associated hardware
needed for selecting the next microinstruction address.

Figure : Selection of address for control memory

 The microinstruction in control memory contains a set of bits to initiate microoperations in
computer registers and other bits to specify the method by which the next address is obtained.
 The above diagram shows four different paths from which the control address register (CAR)
receives the address.
1. Incrementer
2. Branch address from control memory
3. Mapping Logic
4. SBR : Subroutine Register
 In the above diagram Multiplexer receives 4 inputs as follows.
 1. CAR Increment
2. JMP/CALL
3. Mapping
4. Subroutine Return
 Subroutine Register (SBR): Return Address cannot be stored in ROM. So return Address for a
subroutine is stored in SBR.
Conditional Branching
 The branch logic of figure 5 provides decision-making capabilities in the control unit.
 The status conditions are special bits in the system that provide parameter information such as the
carry-out of an adder, the sign bit of a number, the mode bits of an instruction, and input or
output status conditions.
 Information in these bits can be tested and actions initiated based on their condition: whether their
value is 1 or 0.
 The Status Bits Control the conditional branch decisions generated in the Branch Logic.
 The Branch LogicTest the specified condition and Branch (jump) to the indicated address if the
condition is met; otherwise, the control address register is just incremented.
 An unconditional branch microinstruction can be implemented by loading the branch address
from control memory into the control address register. This can be accomplished by fixing the
value of one status bit at the input of the multiplexer, so it is always equal to 1.
Mapping of Instruction
 A special type of branch exists when a microinstruction specifies a branch to the first word in
control memory where a microprogram routine for an instruction is located. The status bits for
this type of branch are the bits in the operation code part of the instruction.
 For example, a computer with a simple instruction format as shown in figure 6 has an operation
code of four bits which can specify up to 16 distinct instructions.
 Assume further that the control memory has 128 words, requiring an address of seven bits. For
each operation code there exists a microprogram routine in control memory that executes the
instruction.
 One simple mapping process that converts the 4-bit operation code to a 7-bit address for control
memory is shown in figure 6.
 This mapping consists of placing a 0 in the most significant bit of the address, transferring the
four operation code bits, and clearing the two least significant bits of the control address register.
 This provides for each computer instruction a microprogram routine with a capacity of four
microinstructions.
 Figure : Mapping from instruction code to microinstruction address
Subroutines
 Subroutines are programs that are used by other routines to accomplish a particular task. A
subroutine can be called from any point within the main body of the microprogram.
 Microprograms that use subroutines must have a provision for storing the return address during a
subroutine call and restoring the address during a subroutine return. This may be accomplished by
placing the incremented output from the control address register into a subroutine register and
branching to the beginning of the subroutine.
 The subroutine register can then become the source for transferring the address for the return to
the main routine.

Microinstruction Format
 The microinstruction format for the control memory is shown in following figure 8. The 20 bits
of the microinstruction are divided into four functional parts.
 The three fields F1, F2, and F3 specify microoperations for the computer.
 The CD field selects status bit conditions.
 The BR field specifies the type of branch to be used.
 The AD field contains a branch address.
 The address field is seven bits wide, since the control memory has 128 = 2 7 words.

Figure : Instruction format

 Table 2: Four computer instructions

Figure : Microinstruction code format (20 bits)

 The microoperations are subdivided into three fields of three bits each.
 The three bits in each field are encoded to specify seven distinct microoperations as listed in
Table 2. This gives a total of 21 microoperations.
 No more than three microoperations can be chosen for a microinstruction, one from each field. If
fewer than three microoperations are used, one or more of the fields will use the binary code 000
for no operation.
 Each microoperation in Table 3 is defined with a register transfer statement and is assigned a
symbol for use in a symbolic microprogram.
 All transfer-type microoperations symbols use five letters. The first two letters designate the
source register, the third letter is always a T, and the last two letters designate the destination
register.
 Table : Symbols and Binary Code for Microinstruction Fields

 For example, the microoperation that specifies the transfer AC DR (F1 = 100) has the symbol
DRTAC, which stands for a transfer from DR to AC.
 The CD (condition) field consists of two bits which are encoded to specify four status bit
conditions as listed in Table 4.

Table : Symbols and Binary Code for CD field

  The first condition is always a 1, so that a reference to CD = 00 (or the symbol U) will always
find the condition to be true. When this condition is used in conjunction with the BR (branch)
field, it provides an unconditional branch operation.
 The indirect bit I is available from bit 15 of DR after an instruction is read from memory.
 The sign bit of AC provides the next status bit.
 The zero value, symbolized by Z, is a binary variable whose value is equal to 1 if all the bits in
AC are equal to zero.
 We will use the symbols U, I, S, and Z for the four status bits when we write microprograms in
symbolic form.
Table 5: Symbols and Binary Code for BR field

 The BR (branch) field consists of two bits. It is used, in conjunction with the address field AD, to
choose the address of the next microinstruction.
 As shown in Table 5, when BR = 00, the control performs a jump (JMP) operation (which is
similar to a branch), and when BR = 01, it performs a call to subroutine (CALL) operation. The
two operations are identical except that a call microinstruction stores the return address in the
subroutine register SBR.
 The jump and call operations depend on the value of the CD field. If the status bit condition
specified in the CD field is equal to 1, the next address in the AD field is transferred to the control
address register CAR. Otherwise, CAR is incremented by 1.
 The return from subroutine is accomplished with a BR field equal to 10. This causes the transfer
of the return address from SBR to CAR.
 The mapping from the operation code bits of the instruction to an address for CAR is
accomplished when the BR field is equal to 11. This mapping is as depicted in figure 6.
 The bits of the operation code are in DR(ll-14) after an instruction is read from memory. Note
that the last two conditions in the BR field are independent of the values in the CD and AD fields.

Design of Control Unit

 The various fields encountered in instruction formats provide control bits to initiate
microoperations in the system, special bits to specify the way that the next address is to be
evaluated, and an address field for branching.
 Each field requires a decoder to produce the corresponding control signals.
 The control memory output of each subfield must be decoded to provide the distinct
microoperations. The outputs of the decoders are connected to the appropriate inputs in the
processor unit.
 The following figure 9 shows the three decoders and some of the connections that must be made
from their outputs.

Figure : Decoding of microoperation fields

 Each of the three fields of the microinstruction presently available in the output of control
memory are decoded with a 3 x 8 decoder to provide eight outputs.
 Each of these outputs must be connected to the proper circuit to initiate the corresponding
microoperation as specified in Table 3.
  For example, when F1 = 101 (binary 5), the next clock pulse transition transfers the content of
DR(0-10) to AR (symbolized by DRTAR in Table 3). Similarly, when F1 = 110 (binary 6) there
is a transfer from PC toAR (symbolized by PCTAR).
 As shown in figure 9, outputs 5 and 6 of decoder F1 are connected to the load input of AR so that
when either one of these outputs is active, information from the multiplexers is transferred to AR.
 The multiplexers select the information from DR when output 5 is active and from PC when
output 5 is inactive. The transfer into AR occurs with a clock pulse transition only when output 5
or output 6 of the decoder is active.
 The other outputs of the decoders that initiate transfers between registers must be connected in a
similar fashion.
 In arithmetic logic shift unit designing, Instead of using gates to generate the control signals
marked by the symbols AND, ADD, and DR, these inputs will now come from the outputs of the
decoders associated with the symbols AND, ADD, and DRTAC, respectively, as shown in figure
9.
 The other outputs of the decoders that are associated with an AC operation must also be
connected to the arithmetic logic shift unit in a similar fashion.

Microprogram Sequencer
 The basic components of a microprogrammed control unit are the control memory and the
circuits that select the next address. The address selection part is called a microprogram
sequencer.
 A microprogram sequencer can be constructed with digital functions to suit a particular
application. However, just as there are large ROM units available in integrated circuit packages,
so are general-purpose sequencers suited for the construction of microprogram control units.
 The purpose of a microprogram sequencer is to present an address to the control memory so that a
microinstruction may be read and executed.
 The next-address logic of the sequencer determines the specific address source to be loaded into
the control address register. The choice of the address source is guided by the next-address
information bits that the sequencer receives from the present microinstruction.
 The block diagram of the microprogram sequencer is shown in figure 10. The control memory is
included in the diagram to show the interaction between the sequencer and the memory attached
to it.
 Figure : Microprogram sequencer for a control memory.
 There are two multiplexers in the circuit. The first multiplexer selects an address from one of four
sources and routes it into a control address register CAR. The second multiplexer tests the value
of a selected status bit and the result of the test is applied to an input logic circuit.
 The output from CAR provides the address for the control memory. The content of CAR is
incremented and applied to one of the multiplexer inputs and to the subroutine register SBR.
 The other three inputs to multiplexer number 1 come from the address field of the present
microinstruction, from the output of SBR, and from an external source that maps the instruction.
 The CD (condition) field of the microinstruction selects one of the status bits in the second
multiplexer. If the bit selected is equal to 1, the T (test) variable is equal to 1, otherwise it is equal
to 0.
 The T value together with the two bits from the BR (branch) field go to an input logic circuit. The
input logic in a particular sequencer will determine the type of operations that are available in the
unit.
 The input logic circuit in figure 10 has three inputs, I0, I1, and T, and three outputs, S0, S1, and L.
  Variables S0 and S1, select one of the source addresses for CAR.
 Variable L enables the load input in SBR.
 The binary values of the two selection variables determine the path in the multiplexer. For
example, with S1 S0 = 10, multiplexer input number 2 is selected and establishes a transfer path
from SBR to CAR.
 The truth table for the input logic circuit is shown in Table 6. Inputs I1 and I0 are Identical to the
bit values in the BR field.
 The function listed in each entry was defined in Table 3. The bit values for S 1 and S0 are
determined from the stated function and the path in the multiplexer that establishes the required
transfer.
 The subroutine register is loaded with the incremented value of CAR during a call
microinstruction (BR = 01) provided that the status bit condition is satisfied (T = 1).
 The truth table can be used to obtain the simplified Boolean functions for the input logic circuit:
S1 = I1
'
S0 = I1I0 + I 1 T
'
L = I 1I0T
Table : Input logic Truth Table for MicroProgram Sequence

Hardwired control unit

 In the hardwired organization, the control logic is implemented with gates, flip-flops, decoders,
and other digital circuits. It has the advantage that it can be optimized to produce a fast mode of
operation.
 A hardwired control, as the name implies, requires changes in the wiring among the various
components if the design has to be modified or changed. In the microprogrammed control, any
required changes or modifications can be done by updating the microprogram in control memory.
 A hardwired control for the basic computer is as follows. The block diagram of the control unit is
shown in following figure 11.

Figure : Control unit of basic computer

 It consists of two decoders, a sequence counter, and a number of control logic gates. An
instruction read from memory is placed in the instruction register (IR).
 The instruction register is shown in figure 11, where it is divided into three parts: the I bit, the
operation code, and bits 0 through 11.
 The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder. The eight outputs of
the decoder are designated by the symbols D0 through D7.
 Bit 15 of the instruction is transferred to a flip-flop designated by the symbol I.
 Bits 0 through 11 are applied to the control logic gates. The 4-bit sequence counter can count in
binary from 0 through 15. The outputs of the counter are decoded into 16 timing signals T 0
through T15.
 The sequence counter SC can be incremented or cleared synchronously. Most of the time, the
counter is incremented to provide the sequence of timing signals out of the 4 x 16 decoder.
 Once in awhile, the counter is cleared to 0, causing the next active timing signal to be T 0. As an
example, consider the case where SC is incremented to provide timing signals T 0, T1 T2, T3, and
T4 in sequence. At time T4, SC is cleared to 0 if decoder output D3 is active.
 Hardwired control unit Micro-programmed Control Unit
1. It uses flags, decoder, logic gates and other 1. It uses sequence of micro-instruction in micro
digital circuits. programming language.
2. As name implies it is a hardware control unit. 2. It is mid-way between Hardware and Software.
3.It generates a set of control signal on the basis of
3. On the basis of input Signal output is generated.
control line.
4. Difficult to design, test and implement. 4. Easy to design, test and implement.
5. Inflexible to modify. 5. Flexible to modify.
6. Faster mode of operation. 6. Slower mode of operation.
7. Expensive and high error. 7. Cheaper and less error.
8. Used in RISC processor 8. Used in CISC processor.