AsIc

BasIcs
An Introduction to Developing
Application Specific Integrated Circuits
 AsIc
BasIcs
An Introduction to Developing
Application Specific Integrated Circuits
About the cover: An array of IC die on a silicon wafer is in the foreground. In the
background, a machine is attaching bonding wires from an IC die to package pins.
Picture Credits:
Silicon wafer on cover and page 8, <http://josef.org/pictures/Miscellaneous/silicon_wafer.jpg>, accessed on 19Feb05
ASIC die microphotograph, on page 8, <http://www.semicon.toshiba.co.jp/eng/prd/asic/doc/pdf/bce0032a.pdf>, accessed
on 19Feb05
14-pin DIP, on page 8 & page 43, <http://www.acad.humberc.on.ca/~ceng103/package.gif>, accessed on 19Feb05
44-pin PLCC, on page 8, <http://www.cpu-world.com/CPUs/8085/MANUF-OKI.html>, accessed on 24Feb05
100-pin QFP, on page 8, <http://www.topline.tv/qfp.html>, accessed on 24Feb05
144-pin BGA, on page 8, <http://www.tessera.com/technologies/applications/wireless/dsp_asic.htm>, accessed on
24Feb05
Line drawing of hen, page 13 & page 15, <http://www.coloring.ws/birds9.htm>, accessed on 19Feb05
Cadence SimVision and Encounter screenshots, page 27 & page 30,
<http://www.demosondemand.com/clients/cadence/014/dod_page/previews.asp#2>,
Reel of tape, page 29, <http://www.dataconversionresource.com/
9-track_magnetic_reel_tape_1600%20BPI_6250%20BPI.htm>, accessed on 24Feb05
Wire bonding machine, cover & page 33, <http://www.netmotion.com/htm_files/ot_ruby.htm ruby_main.jpg>, accessed
on 19Feb05
Testing a prototype, page 34, <http://www.pft.com.hk/PFT/testing.aspx>, accessed on 19Feb05
All drawings were prepared by the author except as credited above.

This guide was produced on a Windows PC using Adobe Framemaker.

Illustrations and photographs were prepared using Adobe Illustrator and Adobe Photoshop.
Fonts used in the guide are Goudy Old Style, Lucinda Sans, and Curlz MT.
ASIC BASICS: AN INTRODUCTION TO DEVELOPING APPLICATION SPECIFIC INTEGRATED
CIRCUITS. Copyright © 2005 by Elaine Rhodes. All rights reserved. No part of this publication can be
reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical,
photocopying, recording or otherwise, without the prior permission of the author. While every precaution
has been taken in the preparation of this book, the author assumes no responsibilities for errors or omissions,
or for damages resulting from the use of information contained herein.
Contents
Introduction 3
Getting Started 5
„ How are ASICs made? 6
„ Are ASICs right for my project? 9
Full custom ICs 9
ASICs 10
FPGAs 11
Selecting an IC class 11
„ What does an ASIC engineer do? 13
Designing logic 13
Using hardware description languages 17
Turning HDL into silicon 18
„ How do I choose an ASIC vendor? 20
„ What tools and equipment do I need? 21

Developing an ASIC 23
„ Designing the logic 24
„ Synthesizing the gates 26
„ Laying out the chip 29
„ Signing off the design 32
„ Fabricating the prototypes 33
„ Verifying the prototypes 34
„ Iterating the design 35

Moving On 37
Troubleshooting 39
Glossary 43
Index 49

1
 Introduction
D id you ever wonder what magic engineers use to make cell
phones, music players, and a plethora of other products smaller
and less expensive every year, even while adding amazing new
features and capabilities? They use the magic of integrated circuits
(ICs), those tiny silicon chips that contain thousands of electronic
circuits. Every year, engineers pack more circuits into ICs by inventing
new ways to advance the optical imaging and etching technologies they
use create microscopic devices on the surfaces of silicon chips. Engineers at
Intel packed their latest Pentium chip with over one hundred million
transistors!
Companies like Intel dedicate teams of over a hundred engineers to develop
complex ICs like Pentium processors. Only a handful of giant corporations
around the world can afford to invest so heavily to develop ICs. These
companies see their investments pay off handsomely because they sell millions

3
4 | ASIC Basics

of chips annually, generating enough revenue to pay back the development

expenses and earn a good profit. How can thousands of other companies gain
the benefits of IC technology when their products do not generate such large
revenues? They need some way to develop ICs at a dramatically lower cost.
IC manufacturers satisfy the need for lower cost IC development with a
technology called application specific integrated circuits, or ASICs
(pronounced “Ay-six”). ASICs lower the cost of developing an IC for a specific
application by sharing a standard basic design among many applications. An
engineer develops an ASIC by building on top of a standard base chip, much
like a pizza is customized with pepperoni, mushrooms, and other toppings.
The ASIC engineer’s job is much less work than developing an entirely
customized or full custom IC, just like picking the toppings for a pizza is easier
than making the whole pie from scratch. But because ASIC engineers rely on
standard base designs, they cannot pack the circuits as efficiently as on a full
custom IC. Therefore, an ASIC part is larger and costs more than an equiv-
alent full custom IC. Nevertheless, ASICs deliver most of the benefits of IC
technology at a reasonable price, while being developed much more quickly
and cheaply than full custom ICs.
With ASIC technology, a single engineer can develop a complex IC with
hundreds of thousands of transistors in a reasonable amount of time, usually
about a year, at a cost and quality level suitable for mass production. ASICs
bring the magic of ICs to products like medical equipment, tape drives, profes-
sional video recorders, and satellites — just about any product shipping less
than a million units annually.
If you are an engineer embarking on your first ASIC project, or if you just
curious about ASICs, keep reading to learn what ASICs are and how they are
developed, a process most engineers find challenging, fun, and rewarding.
This guide is divided into the following sections:
„ Getting Started. Explains what ASICs are, how they are manufactured, and
what role you, as an engineer, play in developing them.
„ Developing an ASIC. Describes the process flow you follow to develop an
ASIC, including instructions for the procedures you execute.
„ Moving On. Suggests how you can learn more about developing ASICs.

„ Troubleshooting. Describes problems you are likely to encounter as you

develop ASICs, and suggests solutions.
So, grab a tasty piece of pizza and dive in!
 Appetizer

Getting Started
You already have an idea of what ASICs are, but before you start
developing your first ASIC, you should know the answers to these
questions, which are discussed in this section:
„ How are ASICs made? Explains how ASICs and other ICs are
manufactured so you can answer the next question.
„ Are ASICs right for my project? Describes several classes of ICs and
explains how you choose the best class to meet your needs.
„ What does an ASIC engineer do? Describes the engineer’s
responsibilities to design logic expressed in high-level description languages
or HDLs, and how they turn their HDL code into silicon chips.
„ How do I choose an ASIC vendor? Explains the criteria you use to select a
vendor to provide your ASICs.
„ What tools and equipment do I need? Describes the CAD (computer aided
design software) tools you use to develop ASICs.

5
6 | ASIC Basics

How are ASICs made?

ASICs and other ICs are made the same way, which is described below. What
distinguishes ASICs from other types of ICs is which parts of the manufac-
turing process are customized for a particular design and which parts are
standardized across many designs. To understand this concept better, you
need to know how ICs are manufactured.
Fabricating an IC is like making a pizza. To make a pizza, you start with a crust,
add a layer of sauce, a layer of cheese, and finally toppings like pepperoni and
green peppers. An IC is made in a similar fashion. The IC’s “crust” is a round,
flat silicon wafer. The wafers used in the latest IC fabrication facilities or fabs
(IC manufacturing plants) are 300 millimeters or 12 inches in diameter, the
size of a small pizza. On top of this wafer, circuits are built up in layers of
materials like polysilicon, aluminum, and silicon dioxide, as shown below:

Toppings Aluminum

Cheese Silicon Dioxide

Polysilicon
Sauce
Silicon Dioxide
Crust Polysilicon

Silicon wafer

Building pizzas and ICs in layers

An important difference between making a pizza and making an IC is a

process called etching. While a layer of cheese covering the entire pizza is great,
a layer of material covering the entire surface of a silicon wafer is not very
useful. Patterns must be etched into the material to create transistors and
interconnections (wires) on the surface of the wafer.
Etching creates microscopic patterns on the wafer’s surface, and is the true
magic of IC technology. Etching delineates fine geometries using an optical
process, forming features ten thousand times narrower than the period at the
end of this sentence.
 Getting Started | 7

The etching process is performed with the following steps:

1. The etching process starts with a new silicon wafer, or one that already has
some etched layers.
Silicon wafer

2. A layer of material is deposited over the entire surface of the wafer.

Material to be etched

3. The layer of material is coated with a photoresistive chemical or photoresist.

Photoresist

4. Light is focused on the photoresist through a mask, which is like a

photographic negative of the patterns to be etched into the material.

Mask

Photoresist hardens
where light hits

5. Because of its photoresistive properties, the photoresist hardens where the

light hits it, as shown above.
6. The photoresist that was not hardened is washed away leaving photoresist
in the desired pattern on the surface of the material.
Exposed, hardened photoresist remains
Unexposed photoresist washed away

7. The material is chemically etched using the photoresist as a stencil, forming

the mask’s pattern in the material.
Material etched using
photoresist as stencil
8 | ASIC Basics

Once the desired patterns have been etched into the material, the layer is
complete. The etching process is repeated with a new material and a new mask
to make the next layer. Advanced IC manufacturing processes use over twenty
masks to make a chip. That’s a lot of toppings on your pizza!
The last step in making a pizza is to slice it and put it in a box. The IC wafer
must be sliced up, too, into individual die, or little rectangular chips. (Die is
both singular and plural.) Each die is one IC, so a wafer yields more ICs if the
die is small. ICs with smaller die sizes cost less than those with larger die sizes
because processing a wafer costs the same amount regardless of how many die
are on it.

Single ASIC die

Makes one IC
(shown actual size)

Special test die

(visible in three places)

Grid of die on 300mm wafer

This wafer holds 200 die

IC die and wafer

The die are tested while the wafer is still intact. A robotic machine performs
the tests rapidly and leaves a drop of red ink on any die that fails the test. The
wafer is diced with a diamond-tipped circular saw or a hydraulic knife, which
is a thin, high pressure stream of water. The die with red ink dots are discarded
and the rest are put into appropriate chip packages, producing the familiar
little black plastic or ceramic “bugs” you see on electronic circuit boards.
Examples of IC packages are pictured below:

14-pin DIP “bug” 44-pin PLCC 100-pin QFP 144-pin BGA

Dual in-line package Plastic leadless chip carrier Quad flat pack Ball grid array

Some IC packages (shown actual size)

 Getting Started | 9

Are ASICs right for my project?

Now that you know how ICs are manufactured, you can decide whether
ASICs are the best kind of ICs to use for your project. ASICs are one of three
classes of ICs that manufacturers have invented to allow you to optimize for:
„ The cost of the parts themselves.
„ The NRE you have to pay. (NRE stands for non-recurring engineering
expense, the fixed cost of developing the IC.)
„ The amount of time it takes to develop the IC.
The three IC classes, full custom, ASIC, and FPGA, are distinguished by how
much of the manufacturing process is customized for your particular project,
and how much is standardized for many designs. These classes of ICs are
described below.

Full custom ICs

Full custom ICs are like pizzas made to order, where you pick the crust, the
sauce, the cheeses, and the toppings. With full custom ICs, engineers
customize all the mask layers.

Full custom: All layers customized

The objective of developing full custom ICs is to achieve a low part cost. The
engineering team uses creativity and as much time as they need to pack the die
as tightly as possible. Engineers design twenty or more masks, so the job takes
a long time and incurs a large NRE. The result is a small die size, so the cost
of manufacturing each part is low. Small full custom chips may cost twenty-five
cents or less, while large chips like Pentium processors cost tens or hundreds
of dollars.
10 | ASIC Basics

ASICs
ASICs are like pizzas where the bases are pre-made and all you pick are the
toppings. With ASICs, engineers customize only the last few mask layers.
These layers interconnect elements ASIC manufacturers predefine in
standard base wafers.

ASIC: Standard base, only “toppings” customized

Transistors on base wafer Transistors wired into a circuit

completing the ASIC

Customizing an ASIC, schematic view

An abstract representation of ASIC customization

The objective of developing ASICs is to reap the benefits of IC technology

without investing the time and expense required for full custom chips. ASICs
can be developed more quickly and with a lower NRE than full custom chips
because engineers only design a few masks. However, the ASIC base wafer has
a fixed set of configurable elements, so ASIC engineers do not have the flexi-
bility to pack the die as tightly as possible. Therefore, a design in an ASIC has
a larger die size and higher part cost than the same design in a full custom IC.
ASICs typically cost fifty cents to two dollars in mass production, but very large
ASICs can have over a million gates and cost hundreds of dollars. An ASIC
costing $900 may seem very expensive, but if it is used in a system that sells for
$50,000, it can still be cost effective.
 Getting Started | 11

FPGAs
FPGAs are like pizzas you take home and bake yourself. With FPGAs,
engineers do not customize anything on the chips physically. They simply use
software to program the FPGAs to interconnect their elements as desired.

Configure with Software

Bake in Oven

FPGA: No physical customization

FPGA is an acronym for field programmable gate array, which means:
„ Field. Customized in the field, meaning anywhere outside of the IC fab.
„ Programmable. Customized by software rather than by masks.
„ Gate. A logic element made of transistors.
„ Array. A large number of gates arranged in rows and columns.
The objective of developing FPGAs is to get projects done quickly and spend
very little NRE. FPGAs satisfy these objectives because they do not need any
customized masks at all. However, an FPGA’s logic elements are very flexible
and additional memory elements are needed to store configuration infor-
mation, so the die size is much larger and the cost much higher than for an
equivalent ASIC or full custom IC. FPGAs typically cost from one to five
dollars. The largest FPGAs have hundreds of thousands of logic gates and cost
several hundred dollars.

Selecting an IC class
The first table on the next page indicates how you can select the best class of
IC for your project. The second table summarizes the characteristics of the
classes that affect your selection. The main factor in choosing a class of IC is
the quantity of parts you will need in mass production, because selling a larger
volume of parts drives the need for a lower unit cost and provides profits to
pay back a large NRE. High volume ICs need a low unit price but can tolerate
a high NRE, so full custom ICs are the best fit. Low volume ICs can tolerate a
12 | ASIC Basics

high unit cost but need a low NRE, so FPGAs are the best choice. ASICs
provide a balance of reasonable unit cost and moderate NRE, so they fit in the
middle ground where production volumes are moderate.
Another important factor in choosing a class of IC is the time it takes to
develop the chip. As shown in the second table, development time may be a
few months for FPGAs, a year or so for ASICs, and several years for full
custom ICs. Some programs take advantage of the best features of all three
classes of ICs by prototyping with FPGAs, beginning low volume production
with ASICs, and converting the design to full custom if the product is
successful in the market and the volumes ramp up to millions.

Selecting an integrated circuit class

Annual production Example application Critical factors Best IC class

1,000,000 or more Cell phones Low unit cost Full custom

10,000 to 1,000,000 Medical equipment Reasonable unit cost & ASIC

NRE

1 to 10,000 Specialized scientific Low NRE & quick time FPGA

instruments to develop

Characteristics of integrated circuit classes

IC Class
Characteristic Full custom IC ASIC FPGA
Masks customized All A few None

NRE(1) $300,000 to $millions $50,000 to $150,000 Less than $5,000

(2)
Die size Small Medium Large

Time to develop 2 to 5 years About 1 year A week to a few months

(3)
Unit cost,10M/yr Small Medium Large

Unit cost,100k/yr(3) Not feasible(4) Medium Large

(3) (4) (4)
Unit cost,1k/yr Not feasible Not feasible Large

Notes:
(1) Non-recurring engineering expense, the fixed cost of developing a chip.
(2) For equivalent functionality.
(3) IC cost per unit is shown for several levels of mass production, 10,000,000 per year, 100,000 per year, and 1,000 per year.
(4) IC manufacturers do not produce this type of IC at this low of a volume.
 Getting Started | 13

What does an ASIC engineer do?

If you have decided that ASICs are right for your project, you probably want
to know what your role is in developing them. As an ASIC engineer, your job
involves the following activities:
„ Designing logic
„ Using hardware description languages
„ Turning HDL into silicon

Designing logic
The part of the job engineers enjoy the most is the area you probably studied
in college, designing logic. In case you did not study it in college, this section
introduces the basic concepts of designing logic.
Designing logic is the process of interconnecting logic elements so they
function in a specified manner. Logic functions range in complexity from very
simple, like deciding if either of two signals is true, to very complex, like
executing Windows software. However, even the most complex logic function
is built up from very simple ones, so you need to understand what simple logic
functions are.
An example of a simple logic function is this egg sorting machine:

Output1
Input Large eggs
Unsorted eggs Egg Sorting
Output2
Machine Medium eggs

Output3
Small eggs

The egg sorting machine

14 | ASIC Basics

The egg sorting machine accepts eggs of various sizes into its input, shown at
the machine’s upper left corner. (Italics indicate technical terms used by
engineers who design logic.) The machine sorts the eggs and routes them to
three separate outputs, shown on the right, one for large eggs, one for medium
eggs, and one for small eggs.
You begin designing logic by drawing block diagrams, like the picture of the egg
sorting machine. A high-level block diagram like this one uses a single block to
represent the entire machine, and shows all its inputs and outputs. Engineers
often call this block a black box (even though it is blue in this drawing), because
you cannot look inside to see how it works. The block diagram is accompanied
by a specification document that explains the functions, inputs, and outputs
of the machine. The preceding paragraph is a specification of the egg sorting
machine.
Once you understand the machine at a high level through your block diagram,
your next step is partitioning. Partitioning means breaking down the functions
inside the machine into smaller logic blocks, which you document in a more
detailed, lower level block diagram and specification. (The egg sorting
machine is so simple, it does not need to be partitioned.)
Partitioning also includes deciding whether to implement the entire machine
in a single IC, or to put some blocks in separate chips or circuit boards instead.
Engineers make decisions about partitioning by considering a number of
factors including:
„ Cost. How much the solution costs to manufacture in mass production.
„ Size. How big the chips (or boards, or boxes) are.
„ Power. How much power the solution consumes — how long it runs before
the battery needs recharging.
„ Pin counts. How many pins the chips need to carry all the input and output
signals; or how many pins are on the connectors of boards and boxes.
„ Capabilities of IC manufacturers. How many gates and how many pins IC
manufactures can put on an chip.
For example, perhaps you can build your machine in a single chip, but if you
split it into two smaller chips, the cost is lower. Based on cost, then, parti-
tioning in two chips is the better solution. But your product may be a small
cell phone that only has room for one chip; in that case, size is the most
important factor and partitioning into a single chip is the best solution, even
though the cost is higher.
 Getting Started | 15

After partitioning, the engineer’s challenge is to configure logic elements to

implement the functions required of each block. Looking inside the black box,
you can see how the egg sorting machine works:

Output1
Input Large eggs
Unsorted eggs

Large hole Output2

Medium eggs

Small hole Output3

Small eggs

Internal logic of the egg sorting machine

The egg sorting machine’s hardware consists of boards with holes in them.
The boards perform the following operations:
„ The top board. Eggs roll past the large hole if they are larger than the large
hole in the board. Thus eggs larger than the large hole roll to Output1, while
eggs that are smaller than the large hole drop to the middle board.
„ The middle board. Eggs roll past the small hole if they are larger than the
small hole in the board. Eggs larger than the small hole roll to Output2, and
since no large eggs reach the middle board, only medium eggs make it to
Output2. Meanwhile, eggs that are smaller than the small hole drop to the
bottom board.
„ The bottom board. Eggs roll to Output3; since no large or medium eggs
reach the bottom board, only small eggs make it to Output3.
A distinctive feature of the logic in the egg sorting machine is that each board’s
operation is a simple yes or no decision — is the egg larger than the hole, or
isn’t it? This is characteristic of binary logic, logic that uses only two states. The
states of binary logic may be called True and False (as logic states), 1 and 0 (as
mathematical quantities), or High and Low (as electrical voltage levels). Binary
logic is the basis of all conventional logic design; it is the language that
computers speak. They are called digital computers because they compute
using the digits 1 and 0.
16 | ASIC Basics

Another feature of the egg sorting machine is that it has two classes of behavior
the engineer must analyze. Functional behavior is how the outputs change in
response to changes in the inputs, irrespective of the time it takes to happen.
The timing behavior is the amount of time it takes for an egg to get from the
input to an output. This period is called the propagation delay through the
system. If the egg sorting machine were driven by a clock, another important
timing characteristic would be how fast the clock can run, like a Pentium
processor that can operate with a 3 gigahertz clock but not faster. Engineers
normally analyze functional and timing behavior separately, first getting the
functional behavior to operate correctly, then working on timing issues.
As an engineer, your job is to design logic to implement particular functions
like egg sorting, firing your engine’s spark plugs at just the right time, or letting
you play solitaire on your computer. Of course, you do not design ASICs using
wooden boards with holes in them; you use logic gates which are made from
transistors in ICs. Gates are very simple logic functions such as:

Logic gates: schematic symbols, equations, and functions

Name Symbol Equation Function Comment

AND A C=A&B The output is True

B C only if all of the
inputs are True.
OR C=A|B The output is True
A only if any of the
C
B inputs are True.
Inverter B = ~A The output is True Also called a
A B only if the single NOT gate
input is False.
NAND A
C = ~(A & B) The output is False NAND means
C only if all of the NOT AND
B inputs are True.
NOR A
C = ~(A | B) The output is False NOR means
B C only if any of the NOT OR
inputs is True.

You may think the egg sorting machine is a trivial example, but sorting and
routing are fundamental operations in computing. Cisco Systems built a huge
company sorting and routing data packets on the Internet!
 Getting Started | 17

Using hardware description languages

ASIC engineers specify logic with hardware description languages (HDLs),
which are very much like software programming languages. Two HDLs,
Verilog and VHDL, have been standardized and are used pervasively in the
ASIC industry. The C software programming language is also used as an HDL
to design ICs.
The egg sorting machine could be specified in an HDL as follows:

TopBoard: LargeEggs = Eggs > LargeHole;

MiddleBoard: MediumEggs = (Eggs < LargeHole) & (Eggs > SmallHole);
BottomBoard: SmallEggs = Eggs < SmallHole;

The elements in this HDL code are described in the following table:

Elements of sample HDL code

Element Description

TopBoard Labels for the statements after the colons

MiddleBoard
BottomBoard

Eggs Symbolic name for the input

LargeEggs Symbolic names for the outputs

MediumEggs
SmallEggs

LargeHole Symbolic names for the constants (fixed values) chosen

SmallHole to discriminate the sizes of the eggs

= Mathematical symbols for equals,

> greater than,
< less than,
& AND

The three statements in the sample HDL code read like plain English, or plain
algebra. You can easily see they describe the operations performed by the
boards and holes in the egg sorting machine.
18 | ASIC Basics

Turning HDL into silicon

When you finish designing your logic, you still have a lot of work to do. You
use these processes to turn your HDL description into an actual IC:
„ Simulation
„ Synthesis
„ Layout

Simulation
You simulate your design by using a CAD tool called a simulator to examine
the design’s functional and timing behavior. You define input stimulus for
your design as a set of functional test vectors; the simulator shows you how your
design responds. Every time you change the design, you simulate again to
verify the design still behaves correctly, or that improper behavior was
corrected if that was the reason for the change.
The simulator can work with a behavioral model, which is an abstract represen-
tation of the design, or a gate-level netlist, which contains actual gates and
timing information from the ASIC vendor’s library of predefined logic
elements. A gate-level netlist is produced by synthesis.

Synthesis
You use a CAD tool called a design compiler or synthesizer to create a version of
the design in gates that are available on the ASIC base wafer. The design
compiler accepts your HDL code and a library that describes the gates and
macros (predefined functions made from gates) available in a your ASIC
vendor’s product. It produces a gate-level netlist which is a text file that lists
the gates used to implement the design and the nets, or wires, that inter-
connect the gates. The design compiler reports the gate count, the number of
gates used in the netlist. Minimizing gate count is important because a design
with fewer gates can fit into a smaller ASIC. Also, a design with fewer gates is
easier to lay out in an ASIC of a given size because it does not need to be
packed as tightly as a design with more gates.

Layout
Your ASIC vendor uses CAD tools to turn the gate-level netlist into actual
geometries for the chip masks that define the transistors on the IC. This
process produces a more accurate timing model than the gate-level netlist
previously contained, so you use the simulator once again to verify that the
design’s function and timing are correct before fabricating the chip.
 Getting Started | 19

Once layout is complete, your vendor can tool (physically create) the masks
and fabricate the chips for you. When you receive the prototype chips, your
HDL has been turned into silicon.
The following chart shows how the design is refined to different levels of
abstraction as it moves from concept (top of chart) to implementation (bottom
of chart):

Levels of abstraction as an IC is developed

Level Example Created by Description

Specification The Geneva cell phone is Engineers Text description in plain English
only 2 millimeters thick...

Block diagram Blk1 Blk2 Engineers Partitioning the design into blocks that
implement the specification
C

HDL for (i=4’b0; (c = = 4’b1)) Engineers Hardware description language

begin describing detailed logic that
implements the block diagram and
inc[i] = val[i] ^ carry;
specification
c = val[i] & carry;
end

Gates CAD tools Logic gates synthesized to implement

the logic described by the HDL code

Transistors CAD tools Transistors that implement the logic

gates

Layout CAD tools Physical geometries that appear on the

masks and are etched into the silicon
surface to form and interconnect the
transistors
20 | ASIC Basics

How do I choose an ASIC vendor?

Your ASIC vendor is your partner as you turn your HDL code into silicon.
You need to choose an ASIC vendor that can meet your needs and help you
be successful. You should identify several ASIC vendors with product
offerings that meet your project’s requirements in these areas:

Factors in ASIC vendor selection

Factor Question to ask

Gate count How many gates do I need for my design?

IC package What type of package and how many pins do I need?

Price What does the vendor charge for the ASIC in mass
production?

Performance How fast does the chip need to run?

Power consumption How much power does the chip consume?

NRE What is the vendor’s price to do the project?

CAD tools Can the vendor work with my company’s CAD tools? Or,
does the vendor have a design center where I can use their
CAD tools?

Development time How quickly can the vendor do their part of the project?

Business relationship Are my company and the vendor willing to work together?

You begin your vendor screening process by looking at gate count and
packaging. Vendors have various product families that may offer ASICs in
sizes like 20,000, 50,000, 100,000, and 500,000 gates, and packages like 44-
pin PLCC, 100-pin QFP, and 144-pin BGA (see pictures on page 8).
Determine which vendors offer products with gate counts and packages that
meet your needs; then look at the rest of the factors listed in the table. Try to
identify several vendors who meet your requirements in all areas. The final
decision usually comes down to picking the vendor who bids the lowest price
for the ASIC in mass production.
You cannot choose your ASIC vendor on your own. Other people in your
company need to be involved because a large amount of money is at stake, and
because your company’s business depends upon your vendor delivering
product on time and at a good price. The final vendor decision is typically
made by an executive in the materials (purchasing) department, taking into
account your technical input.
 Getting Started | 21

You should select your ASIC vendor early in your development cycle if you
can. Your vendor provides a library of logic elements that the design compiler
tries to use efficiently as it synthesizes the gate-level netlist. However, you can
help the design compiler do a better job if you are familiar with the library
when you create your design. Therefore, select your ASIC vendor before you
start designing if you can. If you do not know your ASIC vendor while you are
designing the logic, you may need to go back and modify the design to achieve
a lower gate count while you are synthesizing the gates.

What tools and equipment do I need?

Besides choosing a vendor for your ASIC project, you also need to choose your
tools. You develop ASICs using expensive CAD tools running on powerful
engineering workstations. The CAD tools needed by a single engineer may
cost $50,000 to $100,000 or more. Most companies own or lease these tools
if they do substantial ASIC development. Smaller companies or individual
projects may use equipment at design centers owned by ASIC vendors.
The main CAD tools you need are a design compiler and a simulator. The
design compiler, sometimes called a synthesizer, generates a behavioral model
or a gate-level netlist from HDL code. The simulator allows you to examine the
functional and timing behavior of your design. Besides these two workhorses,
CAD vendors offer a wide variety of specialized tools to meet all kinds of
challenges engineers face while developing ICs.
Your CAD tools run on engineering workstations like Sun SPARCs or PCs
loaded up with a gigabyte or more of memory and ultra-fast disks and
processors. These workstations usually run on the UNIX operating system,
although Windows-based tools are becoming more powerful and popular.
Make sure you have a big nineteen inch monitor so you can see a great deal of
information on the screen at one time. If your project involves multiple
engineers and workstations, the workstations need to be networked together
and a fast, reliable server should be available to store your design data. Be sure
you have a backup strategy to keep your valuable data safe in case of disk
crashes, software viruses, or natural disasters.
A handful of vendors supply the CAD tools used by the majority of ASIC
developers. Among the most popular CAD tool vendors are Cadence, Mentor
Graphics, and Synopsys. All the vendors have Web sites where you can learn
more about their products, and their salespeople are happy to visit you and
explain why their tools are the best ones for doing your job.
 Entrée

Developing an ASIC
B y now you understand what ASICs are and generally how they
are developed. In this section you learn the specific process flow
and procedures for developing an ASIC.
You develop an ASIC by following this process flow:

Start

Designing Synthesizing Laying out Fabricating

the
the logic the gates the chip prototypes

Iterating the design Verifying the

Problems prototypes
Performed by engineer found
No problems
Performed by ASIC vendor found
Done

23
24 | ASIC Basics

You, as the engineer, perform the procedures of designing the logic, synthe-
sizing the gates, and verifying that the prototype chips meets their require-
ments.
Your ASIC vendor does the actual job of laying out the physical geometries of
the chip masks. You participate by verifying that their results correctly
implement your design. Your ASIC vendor fabricates the prototype chips.
If the prototype chips fail verification, you need iterate the design, that is, you
need to fix the design by repeating all the procedures. Iterating an ASIC is
expensive and time-consuming, so make every effort to keep the number of
iterations to a minimum. Most ASIC projects can be completed with only two
or three revisions of the chip, including Rev. A, the first version.
Each of the procedures you must perform is broken down into a set of specific
steps below.

Designing the logic

The objective of the design procedure is to produce a behavioral model of a
design that implements the ASIC’s functional requirements.
Before you can begin the design procedure, you need to develop a block level
functional specification. In this specification, partition the design into small
blocks. Each block should serve a single purpose and be simple enough to
implement in no more than four pages of HDL code. Explain the function of
each block in detail. Show all the inputs and outputs of all the logic blocks and
how the blocks connect to each other.
After you generate the block level functional specification, you should
approach the design procedure hierarchically. Treat each block as an
individual design and perform the design procedure on it. When the blocks
are working, combine them into higher level functions and perform the design
procedure on those functions. Keep building higher level functions until you
assemble all the blocks into a single chip and you can perform the design
procedure on the whole ASIC. The hierarchical approach is effective because
problems are easier to find and fix in smaller blocks than in a single large
block.
 Developing an ASIC | 25

12 parameter clk_cnt = 2;
13 function [7:0] increment;
14 input [7:0] a; reg [3:0] i; reg carry;
15 begin
16 increment = a; carry = 1’b1;
17 for (i = 4’b0; ((carry == 4’b1) && (i <=7)); i = i + 4’b1)
18 begin
19 inc[i] = a[i] ^ carry;
20 carry = a[i] & carry;
21 end
22 end
23 endfunction

A sample of Verilog HDL code

A complete ASIC has thousands of lines of code

Design the logic by performing these steps:

1 Create the design.

Write HDL code that describes logic which performs the specified function.

2 If you are aware of any problems in the design, fix them.

The first time you execute this step, you should not be aware of any problems.
You return to this step if you find any problems in step 6.

3 Compile the design using the design compiler.

A behavioral model of the design is produced.

NOTE Be sure to fix any errors the design compiler detects.

4 Do one of the following:

 If the functional test vectors do not exist yet, write them.
Functional test vectors are a set of input stimuli that thoroughly exercise
the design.
 If the functional test vectors already exist, adjust them as required for
problems you found in step 6.

5 Simulate the behavior of the design using the simulator.

The behavioral model responds to the test vectors with either correct or
incorrect behavior.
26 | ASIC Basics

6 Examine the simulation results carefully to see if the design behaved in the
manner you expect.
Any unexpected behavior indicates problems that must be fixed.

7 Repeat from step 2 until no problems are found in step 6.

When you finish the design procedure, the design exists in an abstract logical
form. It is complete and proven correct through behavioral simulation. The
design is ready to be synthesized into specific elements available in your ASIC
vendor’s library.

Synthesizing the gates

The objectives of the synthesis procedure are to:
„ Generate a gate-level netlist equivalent to the behavioral model you created
in the design procedure.
„ Minimize the gate count.
Synthesizing the gates means turning the abstract HDL description of your
design into a gate-level netlist using elements from the library supplied by your
ASIC vendor. Synthesis may be approached by working on individual
functional blocks or by giving the design compiler the entire design at once.
For some designs, you can achieve a lower gate count if you perform the
synthesis procedure on individual blocks. For other designs, the design
compiler does a better job working on the whole design. You should exper-
iment with both approaches. You may achieve the best result if you synthesize
some blocks separately and leave others to be synthesized with the entire
design.
After you have synthesized the gates and you are satisfied with the gate count,
you need to verify that the resulting gate-level netlist behaves correctly.
Problems may arise because the design compiler interprets your HDL code
differently than the simulator does, or simply because the design compiler fails
to generate some functions the way you want. In this procedure, you repeat
simulating, fixing the design, and synthesizing the gates again until you achieve
a result that behaves correctly.
 Developing an ASIC | 27

Simulating a design
Cadence SimVision simulation CAD tool

NOTE You must select your ASIC vendor before performing the synthesis procedure. Your
vendor supplies the logic element library you need for this procedure.

Synthesize the gates by performing these steps:

1 If you are aware of any problems in the design, fix them.

The first time you execute this step, you should not be aware of any problems.
You return to this step if you find gate count problems in step 2, functional
problems in step 5, or timing problems in step 8.

2 Synthesize the gate-level netlist from the design’s HDL description using
the design compiler.
A gate-level netlist is produced and the design compiler reports the gate count.

3 Repeat from step 1 until you are satisfied with the gate count in step 2.

NOTE Iterating synthesis several times while changing the design in ways that may help reduce
the gate count is usually a good idea.
28 | ASIC Basics

4 Simulate the design at a functional level using the simulator.

The gate-level netlist responds to the test vectors you prepared in the design
procedure with either correct or incorrect behavior. Simulate with relaxed
timing (short gate propagation delays and slow simulated clock speeds) so you
can focus on functional problems, not timing problems.

5 Examine the simulation results carefully to see if the design behaved in the
manner you expect.
Any unexpected behavior indicates problems that must be fixed.

6 Repeat from step 1 until no problems are found in step 5.

7 Verify the timing using the simulator.

The gate-level netlist responds to the test vectors you prepared in the design
procedure with either correct or incorrect timing. Simulate with worst-case
timing (long propagation delays and fast clocks) so you can detect timing
problems.

8 Examine the simulation results carefully to see if the design responded

with the timing you expect.
Any unexpected timing indicates problems that must be fixed.

9 Repeat from step 1 until no problems are found in step 8.

When you finish the synthesis procedure, the design exists in a form that
accurately models the characteristics of your ASIC vendor’s library elements.
However, it does not accurately reflect the timing of the final chip because the
CAD software had to estimate the lengths of the interconnect that will actually
hook up the gates on the chip when it is laid out. (See sidebar, Interconnect and
timing, on the next page.) To model the timing accurately, the physical geome-
tries of the chip must be known. Hence, the next step is laying out the chip.
 Developing an ASIC | 29

Interconnect and timing

Interconnect is wiring that hooks up timing. But the interconnect configuration
gates on a chip, and it makes a big is not known until the chip has been laid
difference in how fast signals change. At out. How can you examine the timing
the microscopic scale of an IC, signals do before laying out the chip?
not change abruptly like flipping a light
ASIC vendors solve this dilemma by
switch on and off. Rather, they change
statistically analyzing the interconnect
more slowly, like turning a dimmer switch
loads of many completed chips. For
gradually from off to dim, brighter, and
example, if a particular type of gate has an
full on — and an IC’s tiny transistors
interconnect length of less than
cannot move the dimmer switches very
10 microns in 90 percent of the cases they
quickly.
examined, you can assume your design is
The more interconnect a transistor likely to be the same. So the CAD tools use
has to drive, the slower the dimmer switch 10 microns as a conservative estimate for
turns, slowing the speed signals travel all the gates of that type in your design.
through the chip. Engineers say the These estimated characteristics are used
interconnect is loading down the transistor, for pre-layout timing analysis.
or the interconnect is a load on the
Because these estimates of
transistor.
interconnect loading come from empirical,
Because loading affects signal speeds statistical data, pre-layout timing analysis is
so heavily, interconnect must be modelled said to use empirical timing or statistical
precisely to accurately simulate a chip’s timing.

Laying out the chip

The objective of the layout procedure is to generate the actual geometries that
form the masks to build the chip.
In the design and synthesis procedures, you decided exactly what toppings you
want on your ASIC pizza. Laying out the chip is like putting the toppings on
the pizza. Your ASIC vendor uses powerful CAD tools to determine how to
actually arrange the gates on the ASIC die and interconnect them according
to your gate-level netlist. The layout process defines the actual patterns that are
created on the chip. When this task is completed, CAD software extracts the
exact interconnect loads for all the gates on the chip. You use the design
30 | ASIC Basics

compiler to back annotate these values into your gate-level netlist, that is, to add
that information into your design. Then you simulate the function and timing
again to verify the design still behaves correctly.

Laying out a chip

Cadence Encounter chip layout CAD tool

NOTE Your ASIC vendor must lay out the chip before you can start this procedure. You need
to give them a purchase order for 25 percent of the total NRE charges before they start.
(See sidebar, NRE payment schedule, on page 33.)

Participate in the layout process by following these steps:

1 If you are aware of any problems in the design, have your vendor fix them.
The first time you execute this step, you should not be aware of any problems.
You return to this step if you find functional problems in step 4 or timing
problems in step 7. You must determine how to fix the problems; your vendor
implements the fixes you specify.

NOTE During the layout procedure, your vendor can fix problems by optimizing certain parts
of the layout, using larger transistors to speed up signals, or inserting gates to slow down
signals. If you encounter problems which cannot be fixed with these techniques, you
must abort the layout procedure and go back to the beginning of the synthesis procedure.
 Developing an ASIC | 31

2 Generate the post-layout netlist.

Use the design compiler to back annotate the interconnect loading information
provided by your vendor into your gate-level netlist. If any fixes were made in
step 1, your vendor gives you a new set of values to back annotate.

3 Simulate the design at a functional level using the simulator.

The post-layout netlist responds to the test vectors you prepared in the design
procedure with either correct or incorrect behavior. Simulate with relaxed
timing (short gate propagation delays and slow simulated clock speeds) so you
can focus on functional problems, not timing problems.

4 Examine the simulation results carefully to see if the design behaved in the
manner you expect.
Any unexpected behavior indicates problems that must be fixed.

5 Repeat from step 1 until no problems are found in step 4.

6 Verify the timing.

The post-layout netlist responds to the test vectors you prepared in the design
procedure with either correct or incorrect timing. Simulate with worst-case
timing (long gate propagation delays and fast clocks) so you can detect timing
problems.

7 Examine the simulation results carefully to see if the design responded

with the timing you expect.
Any unexpected timing indicates problems that must be fixed.

8 Repeat from step 1 until no problems are found in step 7.

NOTE Your ASIC vendor may generate the post-layout netlist (step 2), simulate the design
(steps 3 & 4), and verify the timing (step 6 & 7) for you, and simply inform you of any
failures they find. This saves time because of the logistics involved in moving the design
data back and forth between you and your vendor.

When you finish the layout procedure, the design exists in its final form as it
is intended to be built on the actual chip, and it has been verified to work
correctly in both its functional and timing characteristics. You are ready to sign
off the design and send it to fab. Have a tapeout party! (See sidebar, Tapeout,
on the next page.)
32 | ASIC Basics

Signing off the design

The objective of the sign-off process is to approve the design and release it to
your ASIC vendor to authorize them to fabricate prototype ICs for you.
Signing off the design consists of preparing the documentation listed in the
table below. When the chip has been signed off and the sign-off documen-
tation has been transmitted to your ASIC vendor, they fabricate prototypes of
your chip.

Sign-off Documentation
Document Originates from Description

Final netlist Design compiler Defines the final configuration of the gates

Functional test Design procedure Used for testing the chip

vectors

Timing checks Timing verification in Used to establish timing goals for testing the chip
layout procedure

Package marking Engineer Artwork for the company logo, part number, and
specification other text you want printed on the IC package

Authorization ASIC vendor Various forms your vendor asks you to fill out
forms

Purchase order Your company Pay 25 percent of the NRE charges (see sidebar,
NRE payment schedule, on page 33)

Tapeout
When IC designers release a chip for internet. The chip data would be stored on
fabrication, they say they are taping out the a big reel of magnetic tape, and the tape
chip, or they have reached tapeout. This would be sent to the fab. The tape literally
term comes from the time before the went out the door!

A 9-track, 10.5” diameter, open reel tape

 Developing an ASIC | 33

Fabricating the prototypes

The objective of the fabrication process is to manufacture prototype ICs.
Vendors run prototypes on special lines for speed and quality control, and so
ongoing mass production is not disrupted. They run two or three wafers of
your chip so if something goes awry on one wafer, the other wafers may still
yield good parts. ASIC vendors include twenty-five samples of your chip in
your NRE charge, but you can negotiate for more if your program demands it.
Turn around time for prototypes is four to eight weeks. Two weeks of that time
is required just to package the completed die. You need to give your vendor a
purchase order the remaining 50 percent of the NRE when they deliver the
prototypes. (See sidebar, NRE payment schedule, below.)
Once the prototype chips have been fabricated and delivered to you, your next
task is to verify that they work.

Connecting die to package pins with wire bonds

NRE payment schedule

ASIC vendors require you to pay the These payments are non-refundable.
NRE charges in several installments as the If you cancel the program, you forfeit any
program progresses. 25 percent of the payments you have made, because these
NRE is due when they begin laying out payments compensate the vendor for the
your chip. 25 percent more is due when work they completed on your project.
the begin fabricating your prototypes. The
The timing of the NRE payments is shown
remaining 50 percent is due when they
deliver the prototype chips to you. below:

Vendor’s
library Synthesizing Laying out Fabricating Prototypes
Design the gates the chip prototypes delivered
complete
Pay 25% Pay 25% Pay 50%
of NRE of NRE of NRE
 34 | ASIC Basics

Verifying the prototypes

The objective of the verification process is to prove that the prototype ICs meet
all their functional, timing, and other (environmental, mechanical, etc.)
requirements, and that they meet the needs of the system they were designed
to be part of.
When your receive your prototype chips, you need to evaluate them quickly.
Many people are anxious to hear the verdict because a large amount of time
and money was invested, and because the program will be delayed if the part
has problems. In order to verify the chip rapidly and efficiently, you should
have a test system known as a test bed ready when the prototypes arrive. The test
bed should exercise the chip the same way as it is exercised in the final product.
Testing a prototype Sometimes the final product itself can be used as the test bed.
You need to verify that the chip behaves as designed, and also that it operates
correctly in the system for which it was designed. Exercise the chip in all the
conditions it is likely to encounter in all of its targeted uses. Vary external
conditions such as voltage and temperature to ascertain the chip’s quality and
design margins (how far the specifications can be extended without failures).
Verification is an important and complex task. Formulate your test strategy
early in the development process; you may want to design special features into
the chip to help you verify it. You may build the test bed hardware and write
any software you need during the weeks while your prototypes are being fabri-
cated. However, verification may be such a big job that preparations must be
started much earlier. Other hardware and software engineers may even be
assigned to this task.
If verification testing proves the chip meets all of its specifications and it
functions correctly in its target environment, the process of developing the
ASIC is complete. Release the design to manufacturing so they can order parts
for production. However, problems often show up during verification.
Sometimes they can be tolerated, patched, or worked around in software; if
not, you have to iterate the design to fix them.
 Developing an ASIC | 35

Iterating the design

The objective of iteration is to revise the design until you obtain prototype
chips that pass verification.
CAD tools and ASIC vendors are so good these days, first silicon (the first set
of prototypes) often yields good parts. However, when bugs do show up, you
need to eliminate them by revising the design and prototyping the chip again.
This process is known as iterating the chip, or stepping the chip. What it
means is that you return to the beginning of the design procedure and do it
all over again. Subsequent iterations can be accomplished much more quickly
than the first pass because you can focus on just the few problems you are
fixing. Nevertheless, each step of the development process must be repeated in
order for you to be successful. Short-cutting the process is a recipe for disaster!
Given the complexity you are dealing with when you develop an ASIC, at least
one bug has a substantial probability of showing up — no matter how well you
do your job. Therefore, you should always plan your program to allow you to
revise your chip one time. Another revision beyond even the one you planned
may be necessary, but if you do your job well, you should never have to revise
your chip more than twice. In any case, your first silicon should be good
enough to support most of the system testing required for your program.
 Dessert

Moving On
T he Appetizer section (Getting Started) reviewed what ASICs are,
how they are manufactured, and what the engineer’s role is in
developing them. The Entrée section (Developing an ASIC)
explained the process flow and procedures an engineer follows to
develop an ASIC. However, you need to know much more before you
actually start developing your first ASIC. So, for dessert, here are some
suggestions of how you can learn more about developing ASICs.

Hardware definition languages

Excellent books on the Verilog and VHDL hardware description languages
can be found at Amazon.com and other book stores. Some books come with
CD-ROMs containing software you can use to simulate your HDL code and
see how it actually behaves. Classes are also available from a variety of sources.

37
38 | ASIC Basics

CAD tool vendors

Visit the Cadence, Mentor Graphics, and Synopsys Web sites to learn about
the tools you use to develop ASICs. Plan to take training classes from your
CAD vendor so you can get the most benefit from these sophisticated tools.

ASIC vendors
Visit the Web sites of vendors like VLSI Technology and Toshiba to learn
about their ASIC products and training classes. Study the data books of their
ASIC products; these books are essential tools you need to be intimately
familiar with when you develop those ASICs. Invite some ASIC vendors to
visit you to explain their product offerings and drop off their data books.

FPGA vendors
Visit the Web sites of programmable logic vendors like Xilinx and Altera for
information about designing logic for FPGAs; most of it applies to designing
ASICs as well. You may want to experiment with FPGA development tools.
Getting set up for FPGA development is much less expensive than for ASICs.
You may be able to obtain or borrow tools for free. You may even want to
model some of your logic in FPGAs before completing your ASIC design.

Company resources
Think about training opportunities within your company, such as:
„ Attending design reviews of other ASIC projects.
„ Borrowing ASIC vendor or CAD tool data books or training manuals from
other engineers.
„ Studying the HDL code and simulation test benches from other ASIC
projects — or full custom IC or FPGA projects.
„ Offering to review HDL code or help with simulations on another project,
either on your own initiative or as a temporary work assignment.

The best way for you to become an excellent ASIC engineer is through real
world experience. However, if you are an independent consultant or the lone
ASIC engineer in a small company, you may not have access to these types of
company resources. Do not despair. The CAD tools and the support from the
ASIC and CAD vendors are so good that even inexperienced engineers can be
successful on their very first ASIC designs if they approach their projects with
intelligence, engineering discipline, and great attention to detail.
 Cleanup

Troubleshooting
J ust as cooking a three course meal or a pizza leaves a mess to
clean up, you are bound to run into some messes when you
develop ASICs. The table on the following page lists some common
problems you are likely to encounter as you develop ASICs, and
recommends solutions for them.

39
40 | ASIC Basics

Troubleshooting
Problem Description Solution

Failure to meet timing The logic you design may fail to Change the design and rerun
goals operate at the highest clock synthesis and layout until timing
speeds or with the slowest closure is achieved.
propagation delays required by
your product specification. Get help from other engineers.
Meeting your timing goals is
referred to as achieving timing If absolutely necessary, change the
closure. chip specifications to relax the
timing requirements or find a
faster ASIC technology.

Bugs in the CAD tools CAD tools are extremely complex Work with your CAD tool vendors
programs so they inevitably have to fix, patch, or work around the
bugs (problems) which affect your problems.
ability to do your job.

High cost of CAD tools The CAD tools used by a single Spread out the cost burden by
engineer may cost $50,000 to using floating licenses (see
$100,000 or more. A project’s sidebar, Floating licenses, on next
return on investment (ROI) may page) to share the software among
not justify such a large engineers working on multiple
expenditure. workstations and projects.

Confusion over CAD You cannot access the floating Be careful to request the correct
tool licenses licenses for resources you need licenses and to follow the exact
(see sidebar, Floating licenses, on procedures your IT people
the next page). prescribe.

Work with your IT people to

resolve problems.

Poor interoperability CAD tools from different vendors Ask in-house experts to write
between CAD tools may not be able to exchange scripts (small programs) to patch
design data because they: or work around the problems; or
• Use different data and file write such scripts yourself.
formats.
Work with your CAD tool vendors
• Interpret parts of standardized to solve these issues.
formats differently.
• Support different feature sets.
For example, a simulator from
Vendor A cannot load the netlist
generated by a design compiler
from Vendor B.
 Troubleshooting | 41

Floating licenses
CAD tool software can be shared by With licenses for different software
engineers working on multiple work- and different versions of software floating
stations by using a mechanism called around the network, confusion often
floating licenses. Floating licenses are arises. As a result, engineers may be unable
software licenses that are not tied to a to access critical resources.
particular user or workstation. They take
You can avoid most licensing
advantage of the network connecting the
confusion if you carefully identify which
workstations and servers to “float” around
licenses you need, and you meticulously
to where they are needed at any particular
follow the procedures your IT department
time.
has set up for checking licenses in and out.
Engineers check out floating licenses Also, be a good citizen and release your
from the network when they need to use licenses promptly, so others can use the
licensed resources. They check the licenses resources you no longer need. When you
back in to release the resources when they do have problems with licenses, ask your IT
done using them. people for help.
 Glossary
Application specific integrated Bug
circuit (ASIC) A problem in electronic hardware or
An integrated circuit that can be developed computer software; term comes from an
quickly and at a low cost; an ASIC usually actual dead moth that was discovered in a
serves a single, specialized purpose. failed computer in the early days of
computing; also can refer to an IC because
Back annotate the little black packages with leads sticking
out on two sides resemble insects, like this
To modify a design model to include a new DIP package:
set of characteristics; for example, to back
annotate the netlist with information about
interconnect loading extracted from the
chip layout.

BGA CAD
Ball grid array; a type of IC package that Computer aided design; software programs
packs a large number of pins in a small area; used as tools by engineers developing
the pins are actually tiny balls of solder. ASICs, and in other engineering disciplines
as well.
Binary logic
Logic that works on a set of only two values Chip
called True and False, 1 and 0, or High and Informal term for an IC or a die; term
Low; digital computers operate using binary comes from the tiny piece (like a chip of
logic. stone) of silicon that has a large number of
electronic circuits integrated on it.
Black box
An abstract representation of a logic Clock
function which specifies the inputs, A constant, repeating signal, like the tick of
outputs, and logical transformation, but not a timepiece, that drives computer logic at a
the internal structure that implements the fixed speed; for example, a 3.3 gigahertz
transformation. Pentium has a clock that runs at 3.3
gigahertz (a gigahertz is 1,000,000,000 or
Block diagram 109 cycles per second).
A drawing that indicates the inputs,
outputs, and interconnection of black box
logic functions.

43
44 | ASIC Basics

Design Functional behavior

The intellectual process of creating logic, The operation of a logic machine
circuits, or other implementations to meet a independent of its timing.
set of specifications; also can refer to the
end result of the process of designing; Gate
sometimes the entire development process
is referred to as design. Very simple logic functions like AND, OR,
NOT, NAND, and NOR, which are defined
as follows:
Design compiler
• The output of an AND gate is True only
A CAD tool that generates logic gates which if all of the gate’s inputs are True.
implement logic described in an HDL; also
called a synthesizer. • The output of an OR gate is True only if
any of its inputs is True.
Die • The output of a NOT gate (also called an
inverter) is True only if its single input is
A rectangular silicon chip; an IC without its False.
package. Die is used for both singular (“put
the die in the package”) and plural (“this • The output of a NAND gate is False only
wafer has 200 die on it”) forms. if all of its inputs are True; NAND
means NOT AND.
Digital • The output of a NOR gate is False only
if any of its inputs is True; NOR means
Working in a domain of discrete values, for NOT OR.
example, binary logic.
Gate count
DIP
The number of gates on a chip, normalized
Dual in-line package; a type of IC package to a 2-input NAND gate.
that has two rows of pins; called a through
hole technology because the pins stick A 2-input NAND gate is implemented with
through holes in the circuit board. (see illus- four transistors and is the fundamental unit
tration under Bug). used for counting gates on an ASIC. Here
are a few examples:
Empirical timing • An inverter counts as 0.5 gates because
it is made with two transistors.
See statistical timing.
• An AND gate counts as 1.5 gates
because it is made of a NAND gate
Fab
followed by an inverter.
Fabrication facility; a manufacturing plant
for building ICs; inside a fab are fab lines
• A 4-bit counter macro (it counts from
zero to fifteen) may have a gate count of
which are production lines for processing
80 gates.
silicon wafers into ICs; also, as a verb,
shorthand for fabricate, as in “to fab an IC.”
HDL
First silicon Hardware description language; an English-
like language for specifying logic; similar to
The first set of prototype chips received a software programming language.
when a new design is fabricated.
 Glossary | 45

High-level block diagram Load

A block diagram that shows only the overall The amount of interconnect a transistor or
inputs and outputs of a function; it has not a gate has to drive; long interconnect wires
been partitioned into smaller sub-blocks. are big loads that slow down how quickly
transistors or gates can change their output
Hydraulic knife states.
A thin, very high pressure stream of water
used to cut apart the die on a silicon wafer. M
Abbreviation for one million or 1,048,576
Input (2 raised to the 20th power).
A signal that goes into a logic function or
gate. Macro
A pre-designed, complex logic function like
Integrated circuit (IC) a multiplexer, counter, register, or memory;
ASIC vendors’ libraries have rich sets of
An electronic component which has a large macros for engineers to design with.
number of devices like transistors built onto
a tiny piece of silicon; also called a chip; IC
can refer to just the chip of silicon or to the Margins
chip in a package like a BGA, DIP, PLCC, or Safety factors built into designs; for
QFP. example, if a design is specified to operate
over the voltage range 4.5 volts to 5.5 volts,
Interconnect but testing proves that it works over 4.0
volts to 6.0 volts, the design margin for
Refers to the lines of metal (or other operating voltage is 0.5 volts.
material) that connect the devices on an IC;
essentially wires.
Mask
K An optical stencil used to define the fine
geometries of transistors and interconnect
Abbreviation for 1,000 or 1,024 (2 raised to on an IC.
the 10th power).
Netlist
Layout
A text file listing how a set of devices are
The physical geometries of the devices on a interconnected to form a particular
chip, as defined by the chip’s masks; laying electronic circuit; a net is all the points a
out the chip means designing these geome- particular signal is connected to.
tries.
NRE
Library
Non-recurring engineering expense; the
A computer data file containing descrip- amount invested in developing an IC; in
tions of the gates and macros available on an accounting terms, NRE is a fixed cost
ASIC; the descriptions include both because it does not vary with the number of
functional and timing characteristics of the units manufactured.
elements.
46 | ASIC Basics

Output Script
A signal that comes out of, or is generated A small program written in a scripting
by, a logic function or gate. language like Perl, often used to pre- or post-
process data moving between CAD tools;
Partitioning scripts have the advantage of being “quick
and dirty” compared to other types of
The process of breaking down a function software.
into smaller sub-blocks and deciding where
to implement each block; for example, a
desktop computer’s electronics are parti- Semiconductor
tioned into a motherboard and several add- A characteristic of silicon crystals
on cards. containing certain impurities; such crystals
conduct electricity only when a particular
Patch electric field is applied, and they can restrict
current to flow in only one direction;
To fix a problem temporarily, in a “quick generally refers to ICs made from such
and dirty” fashion. crystals.
PLCC Silicon
Plastic leadless chip carrier; a type of IC A chemical element that forms crystals
package with pins that do not stick through which can be processed into semiconductor
the circuit board (it is a surface mount devices.
component, i.e., mounted on the surface of
the circuit board).
Simulator
Propagation delay A CAD tool that shows how a logic design
responds to a set of input stimulus or test
The time it takes for the output of a gate or vectors; a behavioral simulator works with a
a series of gates to change after an input model of the design expressed in an HDL; a
changes; for example, a particular AND gate functional simulator works with a model
may have a propagation delay of 5 expressed in gates; a timing simulator models
nanoseconds (five thousandth of a micro- the speeds of signals as well as their
second or 5 x 10-9 seconds) when it is functional behavior.
driving a specified amount of interconnect.
Statistical timing
QFP
Timing estimates used for pre-layout timing
Quad flat pack, a type of IC package which analysis; the estimates are based on statis-
can have over 300 pins. tical analysis of the interconnect in previous
designs; also called empirical timing.
Schematic
An abstract drawing that shows how Synthesizer
electrical components like transistors or See design compiler.
logic gates are interconnected, using
symbols like this:
Tapeout
Releasing design data so prototype ICs can
be fabricated; at one time the data would be
transferred on magnetic tape and the tape
was literally sent out to the fab.
 Glossary | 47

Test bed Verilog

A lab fixture for testing prototype ICs; A popular HDL used to design ICs.
sometimes the product for which the IC was
designed can serve as the test bed. VHDL
VHSIC (very high speed integrated circuit)
Test vectors hardware description language; a popular
Input stimulus patterns for a logic HDL used to design ICs.
simulator; may also list the expected
(correct) states of the outputs; a vector is a Wafer
one dimensional array, so a single test vector
is a string of 1s and 0s that defines for a A thin, polished disc of crystallized silicon
particular moment in time the state of all of which is the starting material for manufac-
the inputs and outputs of the device under turing ICs; state-of-the-art fabs process
test. wafers which are 300 millimeters or
12 inches in diameter; the cover of this
guide has a picture of a silicon wafer with
Timing ICs fabricated on its surface.
The speed at which signals change and
propagate in an IC. Work around
A procedure to temporarily deal with a
Timing closure problem without fixing the root cause.
Satisfying the timing requirements of the
design; timing closure is achieved when the
design operates correctly at the highest
clock speeds and with the slowest propa-
gation delays required by the chip’s specifi-
cations.

Tooling
Creating a tool used to produce a unique
part; like creating the molds for a plastic
part or the masks for a semiconductor IC.

Transistor
A three terminal semiconductor device
which can be used as a switch or an
amplifier.

UNIX
The most popular operating system for
engineering workstations and network
servers; an alternative to Windows,
although Windows is becoming more
powerful and popular in the engineering
community.
 Index
A BGA, ball grid array, see integrated circuits,
packages
abstraction, levels of (table) 19
binary logic 15
AND gate 16
black box 14
annotation, back, see back annotation
block diagrams 14
Appetizer (Getting Started section, what
as level of abstraction (in table) 19
ASICs are and how to develop them) 5
black box 14
ASICs
high-level 14
class of ICs 10
bugs
customizing 10
in CAD tools (troubleshooting) 40
defined 6
see also integrated circuits, packages
Developing an ASIC (section),
Building pizzas and ICs in layers
procedures for 23
(illustration) 6
development resources in your
company 38
pronounced “Ay-six” 4
C
schematic (illustration) 10 C software programming language, as an
vendors 38 HDL 17
choosing 20 CAD tools
Toshiba, VLSI Technology 38 confusion over licenses
authorization, see sign-off (troubleshooting) 40
cost of 21
B defined 5
design compiler 21
back annotation
floating licenses, confusion over
defined 30
(troubleshooting) 40
in layout step 31
needed to develop ASICs 21
behavior
poor interoperability between
functional, see functional behavior
(troubleshooting) 40
timing, see timing, behavior
simulator 21
behavioral model
vendors, Cadence, Mentor Graphics,
created by design compiler 18, 25
Synopsys 38
gate-level netlist equivalent to 26
Cadence
objective of design procedure to
CAD tool vendor 38
produce 24
Encounter chip layout CAD tool
used for simulation 18, 25
(screenshot) 30

49
50 | ASIC Basics

SimVision simulation CAD tool Developing an ASIC (section),

(screenshot) 27 procedures for 23
capabilities of IC manufacturers as factor development resources in your
in partitioning 14 company 38
chip layout, see layout development time, see integrated circuits,
choosing an ASIC vendor 20 development time
Cisco Systems, a sorting and routing die size
company 16 for IC classes (in table) 12
Cleanup (Troubleshooting section) 39 larger for ASICs 10
clock largest for FPGAs 11
defined 16 small for full custom ICs 9
simulating with fast speeds 28, 31, die, see integrated circuits, die
40 digital computers 15
simulating with slow speeds 28, 31 DIP, dual in-line package, see integrated
company resources for ASIC circuits, packages
development 38
confusion over CAD tool licenses E
(troubleshooting) 40 egg sorting machine, see designing logic
cost empirical timing 29
factor in partitioning 14 Encounter, Cadence CAD tool (screen
of CAD tools 21, 40 shot) 30
per unit, for IC classes (in table) 12 Entrée (Developing an ASIC section) 23
counting gates, see gate count estimating interconnect during
customizing masks 9, 10, 11 synthesis 28
etching silicon
D creating transistors and
delays, see propagation delays interconnections 6
design compiler CAD tool 21 defined 6
back annotates interconnect steps (process) 7
loads 31 the true magic of ICs 6
creates gate-level netlist 18, 21, 26
design margins 34 F
designing logic fab, fabricating prototype chips, see
partitioning, see partitioning integrated circuits, manufacturing
procedure (steps) 24 failure to meet timing goals
the egg sorting machine (troubleshooting) 40
internal logic (illustration) 15 field programmable gate array, see FPGA
the egg sorting machine first ilicon (first round of protorypes) 35
(example) 13 floating licenses 40
Dessert (Moving On section, learning confusion over (troubleshooting) 40
more about developing ASICs) 37 defined (sidebar) 41
 Index | 51

for CAD tools 40 H

FPGAs
HDL (hardware description
class of ICs 11
language) 17, 37
defined (field programmable gate
as level of abstraction (in table) 19
array) 11
C (softwarwe programming language
vendors, Altera, Xilinx 38
as an HDL) 17
full custom class of ICs 4, 9
elements of, in the egg sorting
functional behavior
machine example 17
defined 16
Verilog 17
simulated 25, 28, 31
VHDL 17
functional test vectors
high-level block diagram 14
creating and modifying 25
How are ASICs made? (section) 6
in sign-off 32
used in simulation 25, 28, 31
used in testing 32
I
used to verify timing 28, 31 ICs, see integrated circuits
image credits, back of title page
G integrated circuits 3
classes of
gate array, see FPGA
ASICs 4, 10
gate count
choosing (table) 12
defined 18, 44
FPGAs 11
factor in ASIC vendor selection 20
full custom ICs 4, 9
iterating synthesis to reduce 27
development time 12
minimizing, goal of synthesis 26
ASICs 10
reported by the design compiler 27
FPGAs 11
gate propagation delays, see probagation
full custom 9
delays
die
gate-level netlist
photograph 8
back annotating interconnect
testing 8
loads 30
etching 6–7, ??–7
created by design compiler 18, 21,
like making a pizza 6
26
manufacturing (fabricating) 6, 33
defined 18
packages
gates
bugs 8
AND, OR, NOT, NAND, NOR,
DIP,PLCC,QFP,BGA 8
inverter 16
marking specifications (in
as level of abstraction (in table) 19
table) 32
made from transistors 16
partitioning example 14
Getting Started (section), what ASICs are
photographs 8
and how to develop them 5
Intel
Glossary 43
Pentium processor chip 3
52 | ASIC Basics

size of team to develop Pentium 3 none customized for FPGAs 11

interconnect 6 tooling (physcially creating) 19
created by etching 6 used in etching 7
defined 29 used in IC manufacturing 6
estimated during synthesis 28 using more than twenty 8
load 29 Mentor Graphics (CAD tool vendor) 38
loading, back annotating (in minimizing gate count
step) 31 goal of synthesis 26
inverter 16 Moving On (section), learning more
iterating the design, see iteration about developing ASICs 37
iterations
number of 35 N
objective 35 NAND gate 16
procedure 35 netlist
gate-level
L back annotating with
layers, see masks interconnect loads 30
laying out the chip, see layout created by design compiler 18,
layout 21, 26
as level of abstraction 19 defined 18
generating masks 29 equivalent to behavioral
overview 18 model 26
procedure (steps) 30 post-layout
levels of abstraction (table) 19 defined 31
licenses, see floating licenses simulating with 31
load, loading, see interconnect load NOR gate 16
logic design, see designing logic NOT gate, see inverter
logic simulator, see simulator NRE (non-recurring engineering
logic synthesisizer, see design compiler expense) payment schedule
(sidebar) 33
M
machine, egg sorting, see designing logic O
macros, defined 18 OR gate 16
manufacturing, see integrated circuits,
manufactuing P
margins, design 34 packages, see integrated circuits, packages
masks part cost, see cost
all cusomized for full custom IC 9 partitioning
customizing (in table) 12 as level of abstraction (in table) 19
generated by layout 29 defined 14
last few customized for ASICs 10 example (illustration) 14
 Index | 53

factors are cost, size, power, pin R

counts, capabilities of IC
refining a design to levels of
manufacturers 14
abstraction 19
payment schedule, NRE (sidebar) 33
relaxed timing, simulating with 28, 31
Pentium processor chip, Intel’s
revising a chip, see iteration
how many transsistors in 3
routing, the egg sorting machine, see
size of team to develop 3
designing logic
photoresist, used in etching 7
picture credits, back of title page
pin count, as factor in partitioning 14
S
pizza, like making ICs 4, 6 selecting an ASIC vendor 20
PLCC, plastic leaded chip carrier, see sign-off
integrated circuits, packages documents (table) 32
poor interoperability between CAD tools process 32
(troubleshooting) 40 silicon
post-layout netlist, see netlist, post-layout first (first round of protorypes) 35
power, as factor in partitioning 14 truning HDL into 18
procedures wafer
designing the logic 24 dicing (slicing up) 8
layinig out the chip 29 photograph 8
synthesizing the gates 26 used to manufacture ICs 6, 7
processes simulation
fabricating the prototypes 33 behavioral 25
iterating the design 35 functional 28, 31
signing off the design 32 overview 18
verifying the prototypes 34 performed by ASIC vendor 31
propagation delays screen shot 27
defined 16 timing 28, 29, 31
simulating with relaxed timing 28, simulator CAD tool 18, 21, 40
31 SimVision, Cadence simulation CAD
simulating with worst-case tool (screen shot) 27
timing 28, 31 size
prototype chips die, see die size
see also integrated circuits, factor in partitioning 14
manufacturing of a small pizza 6
verifying 34 of wafer, 300 mm 6
sorting, the egg sorting machine, see
Q designing logic
specifications
QFP, quad flat pack, see integrated circuits,
and design margins 34
packages
and verification 34
as level of abstraction (in table) 19
54 | ASIC Basics

as part of design process 24 using larger to speed up signals 30

changing to relax timing 40 transistors
package marking (in table) 32 as level of abstraction (in table) 19
started, Getting Started (section), what created by etching 6
ASICs are and how to develop them 5 gates made from 16
statistical timing 29 how many in a Pentium chip 3
Synopsys (CAD tool vendor) 38 hundreds of thousands in an
synthesis ASIC 4
as level of abstraction (in table) 19 in chip layout 18, 19
as part of development flow 24 wired into circuit (schematic) 10
interconnect estimated 28 troubleshooting
overview 18 bugs in CAD tools 40
procedure (steps) 26–28 confusion over CAD tool
synthesisizer, see design compiler licenses 40
synthesizing the gates, see systhesis failure to meet timing goals 40
high cost
T of CAD tools 40
tapeout poor interoperability between CAD
party 31 tools 40
sidebar 32 Troubleshooting (section) 39
teams of engineers
designing full custom ICs 9 U
to develop Intel Pentium 3 unit cost, see cost
test bed, for verification 34
test vectors, see functional test vectors V
testing vectors, test, see functional test vectors
die 8 vendors
using functional test vectors 32 ASIC
timing choosing 20
behavior, defined 16 Toshiba,VLSI Technology 38
closure, defined 40 CAD tools, Cadence, Mentor
empirical 29 Graphics, Synopsys 38
failure to meet goals FPGA, Altera, Xilinx 38
(troubleshooting) 40 verifying prototype ICs
relaxed 28, 31 process 34
statistical 29 test bed 34
worst-case 28, 31 Verilog hardware description
tooling masks, defined 19 language 17
tools, see CAD tools VHDL hardware description
transistor language 17
interconnect loads on 29
 Index | 55

W
wafer, see silicon, wafer
What does an ASIC engineer do?
(section) 13
wires, see interconnect
worst-case timing, simulating with 28, 31
AsIc
BasIcs
An Introduction to Developing
Application Specific Integrated Circuits