State Machines Lab

State Machines Lab (Part 4 of the Calculator Project)

Introduction
In this lab, you will create the CNTRL_FSM submodule as part of the Calculator project (Figure
18b-1). You will also perform RTL verification on the module.

Note: You can describe this functional block either as a multi-process or single-process FSM. In
either case, the outputs should be registered. Start with the multi-process version. If time permits,
you can complete code for the single-process FSM.

Figure 18b-1. Schematic for a Simple Calculator Circuit

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 You will write VHDL code to describe the state machine diagramed below (Figure 18b-2).

Figure 18b-2. Functional Diagram for CNTRL_FSM Logic

Objectives
After completing this lab, you will be able to:
 Write VHDL code to describe a synchronous state machine diagram
 Describe a state machine by using both a multi-process and single-process approach

Procedure
NOTE: Toolwire is the default platform for running labs. Use R:\ for all directory
references.

This lab comprises two primary steps: You will write code for the FSM and verify functionality by
using RTL simulation. If time permits, you will write and verify code for a single-process FSM.

For each procedure within a primary step, there are general instructions (indicated by the
symbol). These general instructions only provide a broad outline for performing the procedure.
Below these general instructions, you will find accompanying step-by-step directions and
illustrated figures that provide more detail for performing the procedure. If you feel confident
about completing a procedure, you can skip the step-by-step directions and move on to the next
general instruction.

Note: If you are not using Toolwire to perform this lab, all software programs, files, and projects
will be located on the C:\ drive instead of R:\.

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 Note: If you are unable to complete the lab at this time, you can download the lab files for this
module from the Xilinx FTP site at
ftp://ftp.xilinx.com/pub/documentation/education/lang11000-9-rev1-xlnx_lab_files.zip.

Writing Code for a Multi-Process FSM Step 1

For each procedure within a primary step, there are general instructions (indicated by
the symbol). These general instructions only provide a broad outline for
performing the procedure. Below these general instructions, you will find
accompanying step-by-step directions and illustrated figures that provide more detail
for performing the procedure. If you feel confident about completing a procedure,
you can skip the step-by-step directions and move on to the next general instruction.

General Flow for this Lab:

Step 1: Step 2: Step 3: Writing

Writing Code Verifying Code for a
for a Multi- Functionality Single-Process
FSM
process FSM
(Optional)

Open the existing My_Class_Labs project within the ISE™ software, located in
the R:\training\vhdl\labs directory.
 Select Start  Programs  Xilinx ISE 9.1i  Project Navigator to launch the Project
Navigator

By default, the ISE software should start with the last open project as the current project.

 If not, select File  Open Project  My_Class_Labs

!
Important: Unless otherwise noted, you must label your project and HDL source files as
instructed, or simulation may not work properly in the Toolwire environment.
!

Create the CNTRL_FSM entity.

 Select Project  New Source

 In the New Source dialog box, select VHDL Module, enter CNTRL_FSM in the File name
field, and click Next to open the table-based entity wizard

 Enter the port data for the intended module with the information in Figure 18b-1

 When you are finished, click Next and click Finish

After finishing the entity, you will be in the HDL editor.

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  Declare the CALC1_PAK design unit with the use clause

Note that the ports of the FSM utilize the user-defined data type DATA_FRAME, as described
in the MY_RECORD composite data type.

 Between the keyword architecture and begin statements, define an enumerated type called
STATE_TYPE, with the values as shown in Figure 18b-2

 Declare the signals CURR_STATE and NEXT_STATE for a multi-process FSM (or STATE for
a single process) of the type STATE_TYPE

Note that the RESET signal is modeled as active high.

 Make certain that within the S4_DONE state, the condition to remain in that state is explicitly
coded

Other points to consider:

 ADDR: The output signal ADDR needs to be incremented and tested within the
FSM, which necessitates creating an internal signal which can be updated within the
process and drive the output port within the clocked process—for example, ADDR_I.

However, you also want to avoid inferred latches in the circuit. A recommended VHDL
coding technique is to declare two internal signals that will mirror each other. One signal
(ADDR_Q, for example) is assigned within the clocked process, which keeps the logic
fully synchronous. Under normal operating conditions, it registers the value of the
internal signal ADDR_I.

That same synchronous signal drives both the physical output port in the clocked process
and the mirrored internal signal in the combinatorial process. An example of this
approached is shown in the solution in the Answers section.

To ensure that the FSM parks in the S4_DONE state at the correct point, pay careful
attention to when the ADDR_I signal is updated; that is, what its value is for a given
clock cycle.

 DATA_FRAME: You will need an input port of this type to drive the output
ports of the module with the individual components (sub-elements) of the DATA_FRAME
input vector.

 Create individual output assignment statements from this signal to the respective
output ports; that is, A_IN <= DATA_FRAME.A_IN ;

 Each of the other modules contains an EN signal. This FSM needs to assert the
MEM_EN, ALU_EN, and COMP_EN control signals at the appropriate intervals.

 After ADDR_I signal reaches 7 (“111”), the FSM should park in the S4_DONE
state until, and unless, a RESET occurs.

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 Verifying Functionality Step 2

General Flow for this Lab:

Step 1: Step 2: Step 3: Writing

Writing Code Verifying Code for a
for a Multi- Functionality Single-Process
FSM
process FSM
(Optional)

You can either build a testbench to verify the functionality of the FSM as a
standalone module, or you can combine one or more of the other submodules in
this level of hierarchy. In the next exercise, this will be the explicit requirement.

You can use the same testbench and input stimulus to verify either the multi-
process or single-process versions.
 Select Project  New Source

 In the New Source dialog box, select VHDL Test Bench and enter CNTRL_FSM_TB in the
File name field. Remember to include the CALC1_PAK file

Depending on whether or not you are using any of the other submodules at this stage, your
testbench and input stimulus should focus on the following:

 Does the FSM reset properly upon RESET?

 Does ADDR increment properly (once every four clock cycles)?

 Are the MEM_EN, ALU_EN and COMP_EN signals asserted at the proper time?

 When ADDR_I reaches its upper limit, does the FSM remain in the S4_DONE
state?

You can get started on the final exercise by using the same OPCODEs in your
testbench that will be loaded into the MEM submodule for the upcoming
SIMPLE_CALC exercise.

You recorded this in Table 16b-3 in the “Arithmetic Logic Unit” lab.
 Create a free-running input clock that operates at 50 MHz

 Toggle (assert) the RESET signal at time 10 ns, for a period of 15 ns

 Read content from ROM and output the content as DATA_FRAME

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 When you run the default ISE Simulator script, the lower-level signals (those
within the UUT) are not visible, which means that you cannot immediately
compare the internal state register to the output signal to ensure compliance. Fix
this by manually adding the lower-level signals to the waveform and restarting
simulation.
 In the Processes window, double-click Simulate Behavioral VHDL Model to run the default
script

Assuming that no errors are detected (if this is not the case, you must correct all errors before
proceeding), the script completes and you can view the simulation results. You are also in the
interactive tool mode.

 In the SIM Hierarchy VIEW window, select the lower-level component, which should be
labeled UUT

The window shows the signals within that module (at that level, within that region)

 Select the current-state signal, which holds the value of the current-state register

 Drag the current-state signal into the Waveform window. It should now be listed along with
the signals in the top level

From this point, you can restart and then rerun the simulation in interactive mode (Figure
18b-3). The literal values for CURR_STATE should be visible.

Manually Restart Run for Default

Simulation Time Length

Figure 18b-3. ISE Simulator Restart and Run Options

Writing Code for a Single-Process FSM Step 3

General Flow for this Lab:

Step 1: Step 2: Step 3: Writing

Writing Code Verifying Code for a
for a Multi- Functionality Single-Process
FSM
process FSM
(Optional)

If time permits, write and verify code for a single-process FSM.

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Conclusion
In this exercise, you created the controller for the Calculator project. To maintain consistency for
data types, you used the CALC1_PAK, which contains the user-defined MY_RECORD data type.

The operation of the FSM entity was straightforward. However, the steps that you took
demonstrate the basics that would be necessary for a FSM of any complexity.

Finally, you built a simple testbench to verify the functionality of the module. Verifying each
submodule before you attempt the broader simulation is recommended.

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A Answers

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.CALC1_PAK.all;

entity CNTRL_FSM is
port ( DATA_FRAME : in MY_RECORD;
CLK : in std_logic;
RESET : in std_logic;
A_IN : out std_logic_vector(3 downto 0);
B_IN : out std_logic_vector(3 downto 0);
C_IN : out std_logic;
OP_CODE : out std_logic_vector(3 downto 0);
EXP : out std_logic_vector(3 downto 0);
ADDR : out std_logic_vector ( 2 downto 0);
COMP_EN : out std_logic;
MEM_EN : out std_logic;
ALU_EN : out std_logic );
end entity CNTRL_FSM;

architecture RTL of CNTRL_FSM is

type CNTRL_STATE is ( S0_INIT, S1_FETCH, S2_ALU, S3_COMP, S4_DONE );

signal CURR_STATE, NEXT_STATE : CNTRL_STATE;

signal ADDR_I, ADDR_Q : std_logic_vector ( 2 downto 0 ) := ( others => ‘0’ );

begin

ADDR <= ADDR_Q; -- used to update output port from synchronous internal signal

SYNC : process ( CLK, RESET )

begin
if ( RESET = '1' ) then
CURR_STATE <= S0_INIT;
ADDR_Q <= ( others => '0' );
elsif rising_edge (CLK) then
CURR_STATE <= NEXT_STATE;
ADDR_Q <= ADDR_I; -- update ADDR_Q with the current value of ADDR_I
end if;
end process SYNC;

COMB : process ( CURR_STATE, DATA_FRAME, ADDR_Q )

begin
--default assignments
A_IN <= DATA_FRAME.A_IN;
B_IN <= DATA_FRAME.B_IN;
C_IN <= DATA_FRAME.C_IN;
OP_CODE <= DATA_FRAME.OP_CODE;
EXP <= DATA_FRAME.EXP;

ADDR_I <= ADDR_Q; -- use the registered ADDR_Q to keep ADDR fully synchronous

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 case CURR_STATE is

when S0_INIT =>

MEM_EN <= '0';
ALU_EN <= '0';
COMP_EN <= '0';

NEXT_STATE <= S1_FETCH;

when S1_FETCH =>

MEM_EN <= '1';
ALU_EN <= '0';
COMP_EN <= '0';

NEXT_STATE <= S2_ALU;

when S2_ALU =>

MEM_EN <= '0';
ALU_EN <= '1';
COMP_EN <= '0';

NEXT_STATE <= S3_COMP;

when S3_COMP =>

MEM_EN <= '0';
ALU_EN <= '0';
COMP_EN <= '1';

NEXT_STATE <= S4_DONE;

when S4_DONE =>

if ADDR_Q = "111" then
NEXT_STATE <= S4_DONE;
else
NEXT_STATE <= S1_FETCH ;
ADDR_I <= ADDR_Q + 1;
end if;
MEM_EN <= '0' ;
ALU_EN <= '0';
COMP_EN <= '0';

when others =>

NEXT_STATE <= S0_INIT;
MEM_EN <= '0' ;
ALU_EN <= '0';
COMP_EN <= '0';

end case;

end process COMB;

end RTL;

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 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.CALC1_PAK.all;ENTITY CNTRL_FSM_TB_vhd IS

END CNTRL_FSM_TB_vhd;

ARCHITECTURE behavior OF CNTRL_FSM_TB_vhd IS

COMPONENT CNTRL_FSM
PORT(
DATA_FRAME : IN MY_RECORD;
CLK : IN std_logic;
RESET : IN std_logic;
A_OP : OUT std_logic_vector(3 downto 0);
B_OP : OUT std_logic_vector(3 downto 0);
C_IN : OUT std_logic;
OP_CODE : OUT std_logic_vector(3 downto 0);
EXP : OUT std_logic_vector(3 downto 0);
MEM_EN : OUT std_logic;
ALU_EN : OUT std_logic ;
COMP_EN : OUT std_logic ;
ADDR : OUT std_logic_vector(2 downto 0) );
END COMPONENT;

SIGNAL DATA_FRAME : MY_RECORD := ("0000", "0000","0000",'0',"0000");

SIGNAL CLK : std_logic := '0';
SIGNAL RESET : std_logic := '0';
SIGNAL A_IN, B_IN : std_logic_vector(3 downto 0);
SIGNAL C_IN : std_logic;
SIGNAL OP_CODE : std_logic_vector(3 downto 0);
SIGNAL EXP : std_logic_vector(3 downto 0);
SIGNAL ALU_EN, MEM_EN, COMP_EN : std_logic;
SIGNAL ADDR : std_logic_vector(2 downto 0);
BEGIN
uut: CNTRL_FSM PORT MAP(
DATA_FRAME => DATA_FRAME,
CLK => CLK,
RESET => RESET,
A_IN => A_IN,
B_IN => B_IN,
C_IN => C_IN,
OP_CODE => OP_CODE,
EXP => EXP,
ALU_EN => ALU_EN, MEM_EN => MEM_EN, COMP_EN => COMP_EN ,
ADDR => ADDR );

CLK <= not CLK after 20 ns;

RESET <= '1' after 10 ns, '0' after 25 ns;

tb : PROCESS
BEGIN
DATA_FRAME <= ("1000", "0100","0000",'0',"0000");
wait for 100 ns;
DATA_FRAME <= ("1000", "0100","0101",'0',"0000");

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 wait for 100 ns;
DATA_FRAME <= ("1000", "0100","0100",'0',"0000");
wait; -- will wait forever
END PROCESS;

END TEST;

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