ISE Simulator and StateCAD Tool

Lab
ISE Simulator and StateCAD Tool Lab

Introduction
The ISE™ software tools include the ISE Simulator and StateCAD state diagram editor tools. This
lab covers the simulation and verification process after a design is completed and also
demonstrates the use of the ISE Simulator and StateCAD tools.

Objectives
After completing this lab, you will be able to:
 Create a testbench with the ISE Simulator waveform editor tool
 Simulate a design
 Revise a state machine with the StateCAD tool

Procedure
This lab comprises five primary steps: You will create a waveform file, view the HDL testbench,
simulate the design, fix errors in the StateCAD tool environment, and rerun the simulation.

For each procedure within a primary step, there are general instructions (indicated by the
symbol). These general instructions only provide a broad outline for performing the procedure.
Below these general instructions, you will find accompanying step-by-step directions and
illustrated figures that provide more detail for performing the procedure. If you feel confident
about completing a procedure, you can skip the step-by-step directions and move on to the next
general instruction.

Note: If you are unable to complete the lab at this time, you can download the original lab files for
this module from the Xilinx FTP site at
ftp://ftp.xilinx.com/pub/documentation/education/fpga16000-9-rev1-xlnx_lab_files.zip. These are
the original lab files and do not contain any work you may have previously completed.

ISE Simulator and StateCAD Tool Lab www.xilinx.com 10-3

1-877-XLX-CLAS
 Creating a Waveform File Step 1

General Flow for this Lab:

Step 1: Step 2: Step 3: Step 4: Fixing Step 5:

Errors in the
Creating a Viewing Simulating StateCAD
Rerunning
Waveform the HDL the Design Tool the
File Testbench Environment Simulation

Open the lab.ise project located in the C:\training\ise\labs\isim directory.

 To open the Project Navigator, select Start  Programs  Xilinx ISE 9.1  Project
Navigator

 In the Project Navigator, select File  Open Project

 Browse to the C:\training\ise\labs\isim directory

 Select lab.ise and click Open (Figure 10-1)

Figure 10-1. Open Project Dialog Box

Create a new testbench waveform file named top_tb.

 In the Processes for Source window, double-click Create New Source

ISE Simulator and StateCAD Tool Lab www.xilinx.com 10-4

1-877-XLX-CLAS
  In the New Source dialog box, select Test Bench Waveform and type top_tb in the File
Name field (Figure 10-2)

Figure 10-2. New Source Dialog Box

 Click Next

 Select top as the associated source

 Click Next and click Finish

The ISE™ Simulator waveform editor opens and displays the Initialize Timing dialog box.
Use the options in this dialog box to set up the basic timing relationships among the signals in
the design.

ISE Simulator and StateCAD Tool Lab www.xilinx.com 10-5

1-877-XLX-CLAS
 Set up the initial timing for signals. The clock signal for this design is clk and has
a period of 10 ns with a 50-percent duty cycle. All signals in the design are
synchronous to the rising edge of the clock. Set the input setup and output valid
times to 2 ns and the initial offset to 0 ns. Do not use the GSR signal. The
testbench will be 200-ns long.
 In the Initialize Timing dialog box, enter the following settings and click Finish (Figure
10-3)

 Clock Time High: 5 ns

 Clock Time Low: 5 ns

 Input Setup Time: 2 ns

 Output Valid Delay: 2 ns

 Offset: 0 ns

 GSR: not checked

 Initial Length of Testbench: 200 ns

Figure 10-3. Initialize Timing Dialog Box

ISE Simulator and StateCAD Tool Lab www.xilinx.com 10-6

1-877-XLX-CLAS
  When the waveform window opens in the Project Navigator, take some time to explore the
GUI (Figure 10-4)

Figure 10-4. Waveform Editor

The clock signal clk is drawn with a 10-ns period and 50-percent duty cycle as you described
in the Initialize Timing dialog box.

The inputs din, reset, and up_dn are displayed next. The blue regions show when signal
changes are expected, based on the Input Setup Time option in the Initialize Timing dialog
box. Clicking in a blue region toggles the input signal.

Expanding the dout bus shows the individual signals by default; bus values are displayed in
hexadecimal. Right-click the displayed value to change the radix.

Assert input reset at time 3 ns and deassert it at time 13 ns.

 Assert reset at time 3 ns by clicking inside the Blue cell near time 5 ns

 Deassert reset at time 13 ns by clicking inside the Blue cell near time 15 ns

Use the Pattern wizard to input the waveform for up_dn. Follow the pattern
described in detailed Step 3 of this section.
 Right-click up_dn near time 25 ns and select Set Value to open the Set Value dialog box
(Figure 10-5)

Figure 10-5. Set Value Dialog Box

 Click Pattern Wizard

ISE Simulator and StateCAD Tool Lab www.xilinx.com 10-7

1-877-XLX-CLAS
  Set the following controls for the Pattern Wizard (Figure 10-6)

 Pattern Type: Pulse

 Number of Cycles: 2

 Initial Value: 1

 Initial Delay: 1

 Pulse Value: 0

 Pulse Width: 4

Figure 10-6. Pattern Wizard Dialog Box

The pattern you have described is a series of two pulses. Each pulse starts with the signal
High for one clock cycle (Initial Value and Initial Delay) and then pulses Low for four clock
cycles (Pulse Value and Pulse Width).

 Click OK

 Verify that the pattern is reflected in the up_dn waveform

The signal should be High between times 23 ns and 33 ns; it should also be High between
times 73 ns and 83 ns; and it should be High from time 123 ns to the end of the testbench.

ISE Simulator and StateCAD Tool Lab www.xilinx.com 10-8

1-877-XLX-CLAS
 Click in the Blue regions to toggle the din input High and Low as shown in
Figure 10-7. This signal is an input to a state machine which enables the outputs
for one clock cycle when the pattern 1001 is detected on din.
 Click din near time 25 ns to assert the signal

 Click din near time 35 ns to deassert the signal

 Repeat Step 1 and Step 2 to create a waveform like the one shown in Figure 10-7

Figure 10-7. Final Waveforms

Save and close the waveform.

 Select File  Save

 Select File  Close

Viewing the HDL Testbench Step 2

General Flow for this Lab:

Step 1: Step 2: Step 3: Step 4: Fixing Step 5:
Errors in the Rerunning
Creating a Viewing the Simulating StateCAD Tool
Waveform HDL the Design Environment the
File Testbench Simulation

ISE Simulator and StateCAD Tool Lab www.xilinx.com 10-9

1-877-XLX-CLAS
 View the testbench in HDL format.
 In the Sources in Project window, select Behavioral Simulation from the drop-down dialog
box (Figure 10-8). Select the waveform file top_tb.tbw

Figure 10-8. Selecting the Testbench

 In the Processes for Source window, double-click View Generated Testbench as HDL
(Figure 10-9)

Figure 10-9. Viewing the Testbench

The testbench opens in the Project Navigator editing window. In this project, the testbench is
generated in VHDL.

!
If the file does not open, double-click View Behavioral Testbench as HDL again.
!

ISE Simulator and StateCAD Tool Lab www.xilinx.com 10-10

1-877-XLX-CLAS
  Look for the following components in the testbench:

a) Library declarations
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
…

b) Declaration of Unit Under Test

COMPONENT top
PORT (
CLK : In std_logic;
...

c) Test Signals Defined

SIGNAL clk: std_logic := ‘0’;
…

d) Instantiation of Unit Under Test

UUT : top
PORT MAP (
clk => clk,
…

e) Clock definition
PROCESS -- clock process for clk
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
…

f) Stimulus
BEGIN
-- ------------------ Current time: 3ns
WAIT for 3 ns;
reset <= ‘1’;
…

 Close the testbench file

Simulating the Design Step 3

General Flow for this Lab:

Step 1: Step 2: Step 3: Step 4: Fixing Step 5:

Errors in the
Creating a Viewing Simulating StateCAD
Rerunning
Waveform the HDL the Design Tool the
File Testbench Environment Simulation

ISE Simulator and StateCAD Tool Lab www.xilinx.com 10-11

1-877-XLX-CLAS
 Run the simulation for 200 ns.
 In the Sources in Project window, ensure that the testbench file top_tb.tbw is selected

 In the Processes for Source window, expand the Xilinx ISE Simulator icon, right-click
Simulate Behavioral Model, and select Properties

 Set the Simulation Run Time to 200 ns and click OK

If the Simulation Run Time is longer than the testbench, the testbench waveforms will be
repeated.

 Double-click Simulate Behavioral Model to start the ISE™ Simulator

 Zoom in to see the output waveforms in detail (Figure 10-10)

Figure 10-10. Simulation Results

The dout and dout_valid signals are toggling even when the pattern 1001 is not present on
din, probably caused by an incorrect output assignment in the detection state machine.

 Close the simulation window. Click Yes to confirm that you want to end the simulation

Fixing Errors in the StateCAD Tool Step 4

General Flow for this Lab:

Step 1: Step 2: Step 3: Step 4: Fixing Step 5:

Errors in the
Creating a Viewing Simulating StateCAD
Rerunning
Waveform the HDL the Design Tool the
File Testbench Environment Simulation

Launch the StateCAD tool, open DETECTOR.DIA, and change the GOT_01 state
so that OE = 1 during that state.
 To start the StateCAD tool, select Start  Programs  Xilinx ISE 9.1i  Accessories 
StateCAD

 Select File  Open. Browse to the C:\training\ise\labs\isim directory, select

DETECTOR.DIA, and click Open

ISE Simulator and StateCAD Tool Lab www.xilinx.com 10-12

1-877-XLX-CLAS
 The state diagram appears (Figure 10-11).

Figure 10-11. StateCAD State Machine Editor

 Double-click state GOT_10

 Change the line OE=’0’; to OE=’1’; (Figure 10-12)

Figure 10-12. Edit State Dialog Box

 Click OK

 Select Options  Compile to generate a new VHDL file

ISE Simulator and StateCAD Tool Lab www.xilinx.com 10-13

1-877-XLX-CLAS
  View the Results dialog box and click Close

A new window opens to display the generated code. Examine the code and close the window

 Select File  Exit. Click Yes to save the change you made to the state diagram

Rerunning the Simulation Step 5

General Flow for this Lab:

Step 1: Step 2: Step 3: Step 4: Fixing Step 5:

Errors in the
Creating a Viewing Simulating StateCAD
Rerunning
Waveform the HDL the Design Tool the
File Testbench Environment Simulation

Rerun the simulation and view the new waveform.

 In the Sources in Project window, ensure that the testbench file top_tb.tbw is selected

 In the Processes for Source window, double-click Simulate Behavioral Model to start the
ISE™ Simulator

 Zoom in to see the output waveforms in detail (Figure 10-13)

Figure 10-13. New Simulation Results

 Look at the dout and dout_valid signals. Confirm that they are only active for one clock cycle
after the pattern 1001 has appeared on the din signal

Conclusion
In this lab, you created a testbench for a design by using the ISE Simulator’s waveform editing
tool. You applied stimulus to signals via the Pattern Wizard. After the design was simulated in the
ISE simulator, you detected errors in the design; furthermore, you went to the source files to
correct the errors. You also saw how easy it is to update waveforms and regenerate simulation
waveforms.

ISE Simulator and StateCAD Tool Lab www.xilinx.com 10-14

1-877-XLX-CLAS