ECS Lab

ECS Lab

Introduction
This lab introduces you to the Xilinx ECS schematic capture tool. You will place and connect
components and name signals.

Objectives
After completing this lab, you will be able to:
 Create a new schematic sheet
 Add components and net names to a schematic sheet
 Modify and edit a symbol

Procedure
This lab comprises seven primary steps: You will launch ECS, add a title block, place symbols,
place a CORE Generator™ software component, add nets, add I/O markers, and check the
schematic for errors.

For each procedure within a primary step, there are general instructions (indicated by the
symbol). These general instructions only provide a broad outline for performing the procedure.
Below these general instructions, you will find accompanying step-by-step directions and
illustrated figures that provide more detail for performing the procedure. If you feel confident
about completing a procedure, you can skip the step-by-step directions and move on to the next
general instruction.

Note: If you are unable to complete the lab at this time, you can download the original lab files for
this module from the Xilinx FTP site at
ftp://ftp.xilinx.com/pub/documentation/education/fpga16000-9-rev1-xlnx_lab_files.zip. These are
the original lab files and do not contain any work you may have previously completed.

ECS Lab www.xilinx.com 7-3

1-877-XLX-CLAS
 Launching ECS Step 1

General Flow for this Lab:

Step 1: Step 2: Step 3: Step 4: Placing Step 5:

a CORE
Launching Adding a Placing Generator Adding
ECS Title Block Symbols Software Nets
Component

Step 6: Step 7:
Adding I/O Checking the
Markers Schematic
for Errors

Create a new project in the C:\training\ise\labs\ecs_lab directory named ecs_lab

that targets the XC4VLX15-12SF363 part. Select the XST design flow.
 To open the Project Navigator, select Start  Programs  Xilinx ISE 9.1  Project
Navigator

 In the Project Navigator, select File  New Project

The New Project Wizard starts and the New Project dialog box appears (Figure 7-1).

Figure 7-1. New Project Dialog Box

 Type ecs_lab in the Project Name field

Confirm that C:\training\ise\labs\ecs_lab appears in the Project Location field.

 Select Schematic from the Top-Level Module Type drop-down menu

ECS Lab www.xilinx.com 7-4

1-877-XLX-CLAS
  Click Next

The Device and Design Flow dialog box appears (Figure 7-2).

Figure 7-2. Device and Design Flow Dialog Box

 Choose the following device and click Next

 Family: Virtex4
 Device: XC4VLX15
 Package: SF363
 Speed Grade: –12

 Click Next twice to skip the Create a New Source and Add Existing Sources dialog boxes

 Click Finish

Create a new source of type Schematic named designA.

 In the Processes for Source window, double-click Create New Source

ECS Lab www.xilinx.com 7-5

1-877-XLX-CLAS
  In the New Source dialog box, select Schematic (Figure 7-3)

Figure 7-3. New Source Dialog Box

 Type designA in the File Name field and click Next

 Click Finish to launch ECS

Adding a Title Block Step 2

General Flow for this Lab:

Step 1: Step 2: Step 3: Step 4: Placing Step 5:

a CORE
Launching Adding a Placing Generator Adding
ECS Title Block Symbols Software Nets
Component

Step 6: Step 7:
Adding I/O Checking the
Markers Schematic
for Errors

Place a title block component in the lower-right corner of the schematic sheet.

ECS Lab www.xilinx.com 7-6

1-877-XLX-CLAS
  In the Symbols tab, confirm that the Category <- All Symbols -> is selected (Figure 7-4)

Figure 7-4. Symbols Tab

 In the Symbol Name Filter field, type t to find all components that start with the letter “t”

 In the Symbols box, select title and place the cursor in the editing window to see the title
block attached to the cursor

 Place the title block in the lower-right corner of the sheet (Figure 7-5)

Figure 7-5. Schematic Sheet

 Press Esc to exit from adding more title boxes

Edit the properties of the title box so that it displays your name and the title “My
Design.”
 Double-click the title box to open the Object Properties dialog box

ECS Lab www.xilinx.com 7-7

1-877-XLX-CLAS
  In the NameFieldText line, replace the Value column with your name (Figure 7-6)

Figure 7-6. Object Properties

 In the TitleFieldText line, type My Design in the Value column

 Click Apply and view the change in the schematic drawing. Use the Zoom buttons to examine
the title box more closely

 Click OK to close the Object Properties dialog box

Placing Symbols Step 3

General Flow for this Lab:

Step 1: Step 2: Step 3: Step 4: Placing Step 5:

a CORE
Launching Adding a Placing Generator Adding
ECS Title Block Symbols Software Nets
Component

Step 6: Step 7:
Adding I/O Checking the
Markers Schematic
for Errors

Place an FDCE component on the sheet and experiment with the Mirror and
Rotate buttons in the toolbar. Use the Zoom buttons as needed.
 In the Symbols tab, in the Categories box, select Flip_Flop

ECS Lab www.xilinx.com 7-8

1-877-XLX-CLAS
  Type fdce in the Symbol Name Filter field

As you enter each letter of the filter, fewer components will appear in the Symbols box. Only
two components will finally appear in the Symbols box.

 Select FDCE and place it in location B-3 (see the grid markings on the edge of the schematic
sheet)

 Press Esc to exit Symbol mode

 Select the FDCE component on the sheet

 In the toolbar, click the Mirror button (Figure 7-7)

Figure 7-7. Mirror Button

 Notice the symbol change. You can use the Zoom buttons (Figure 7-8) for a closer look

Figure 7-8. Zoom Buttons

 Click the Rotate button (to the left of the Mirror button). Note the results

 Move the component back to its original position and orientation

Note: Components can also be mirrored and rotated before they are placed on the sheet.

 Select File  Save

Placing a CORE Generator Software Component Step 4

General Flow for this Lab:

Step 1: Step 2: Step 3: Step 4: Placing Step 5:

a CORE
Launching Adding a Placing Generator Adding
ECS Title Block Symbols Software Nets
Component

Step 6: Step 7:
Adding I/O Checking the
Markers Schematic
for Errors

In the Project Navigator, use the CORE Generator™ software system to create a
4-bit loadable binary counter named counter_1.
 Use the menu command Project  New Source

ECS Lab www.xilinx.com 7-9

1-877-XLX-CLAS
  Select IP (COREGen & Architecture Wizard), type counter_1 in the File Name field, and
click Next (Figure 7-9)

Figure 7-9. New Source Dialog Box

 In the Select Core Type dialog box, expand Basic Elements and expand Counters. Select
Binary Counter v8.0 (Figure 7-10)

Figure 7-10. Select Core Dialog Box

 Click Next and click Finish

ECS Lab www.xilinx.com 7-10

1-877-XLX-CLAS
  In the Binary Counter dialog box, type 4 in the Output Width field (Figure 7-11). Click Next
twice.

Figure 7-11. Binary Counter Dialog Box (Page 1)

 Select the Load checkbox (Figure 7-12)

Figure 7-12. Binary Counter Dialog Box (Page 3)

 Click Finish to create the core

ECS Lab www.xilinx.com 7-11

1-877-XLX-CLAS
 Place the counter_1 core on the schematic sheet at area B-5.
 In the Symbols tab, in the Categories box, select <C:\training\ise\labs\ecs_lab>. If you
cannot find the C: directory, use the menu command Add  Symbol to update the Categories
list

 Select counter_1 and place the symbol at location B-5 (Figure 7-13)

Figure 7-13. Schematic Sheet

 Press Esc to exit Add Symbol mode

Adding Nets Step 5

General Flow for this Lab:

Step 1: Step 2: Step 3: Step 4: Placing Step 5:

a CORE
Launching Adding a Placing Generator Adding
ECS Title Block Symbols Software Nets
Component

Step 6: Step 7:
Adding I/O Checking the
Markers Schematic
for Errors

ECS Lab www.xilinx.com 7-12

1-877-XLX-CLAS
 Use the Add Wire button to draw the wires as shown in the diagram in Figure
7-14

 Click the Add Wire button

 Place the cursor over the pins on the components and click to begin and end the wires
(double-clicking creates a hanging end). Draw the wires as shown in the diagram in Figure
7-14. Note that it may be helpful to press Esc to finish a connection.

Note: When you attach a wire to a bus pin, such as the Q(3:0) pin of the counter, a bus is
drawn instead of a wire.

Try autorouting the clock signal: Extend a wire from the C pin on the FDCE symbol. Then,
left-click the CLK pin on the counter component and bring the cursor directly to the C wire.
Left-click and the wire automatically routes.

Figure 7-14. Component Connections

Use the Add Net Name function to name each signal as shown in the diagram in
Figure 7-16 on the following page.

 Click the Add Net Name button

ECS Lab www.xilinx.com 7-13

1-877-XLX-CLAS
  In the Options tab, type Clock in the Name field (Figure 7-15)

Figure 7-15. Entering Net Names

 Place the cursor at the end of the hanging wire to the clock input pin of the FDCE and
Counter_1 and click to add the name

 Repeat the process for Data, Enable, Clear, Load(3:0), and My_Out(3:0)

The schematic should now look like Figure 7-16.

Figure 7-16. Schematic with Net Names

ECS Lab www.xilinx.com 7-14

1-877-XLX-CLAS
 Adding I/O Markers Step 6

General Flow for this Lab:

Step 1: Step 2: Step 3: Step 4: Placing Step 5:

a CORE
Launching Adding a Placing Generator Adding
ECS Title Block Symbols Software Nets
Component

Step 6: Step 7:
Adding I/O Checking the
Markers Schematic
for Errors

Add I/O markers for the input and output signals.

 Select Add  I/O Marker or click the I/O Marker button

In the Options tab, “Add an automatic marker” is automatically selected.

 Draw a bounding box around the input net names to add I/O markers (Figure 7-17)

This adds input markers to the bounded signals.

Figure 7-17. Bounding Box Encompassing Net Names

 Repeat a bounding box for the Load(3:0) bus

 Do not create an I/O marker for the My_Out(3:0) bus. You will do this in the next step

ECS Lab www.xilinx.com 7-15

1-877-XLX-CLAS
 Checking the Schematic Step 7

General Flow for this Lab:

Step 1: Step 2: Step 3: Step 4: Placing Step 5:

a CORE
Launching Adding a Placing Generator Adding
ECS Title Block Symbols Software Nets
Component

Step 6: Step 7:
Adding I/O Checking the
Markers Schematic
for Errors

Perform a check on the schematic to ensure everything is connected correctly. Fix

any errors in the schematic and perform the consistency check until there are no
more errors. Warnings are OK.

 Click the Check Schematic button

The Message Window provides some useful warning information (Figure 7-18).

Figure 7-18. Schematic Check Errors Dialog Box

 Click the file name in the warning message to bring up the location of the error on the
schematic

The problem is that there is not an I/O marker on the My_Out bus. Correct the error by adding
a marker to the bus.

 Select Add  I/O Marker

 Draw a bounding box around the output bus My_Out to add the output marker

 Perform the schematic check again

There should be no errors this time.

 Select File  Save to save the schematic

ECS Lab www.xilinx.com 7-16

1-877-XLX-CLAS
Conclusion
In this lab, you performed the basic functions of creating a schematic design. You started the ECS
tool, created a component by using the CORE Generator™ software tool, added components to a
sheet, and connected these components. You also named the wires and added I/O markers to the
design. Finally, you were able to perform a successful schematic check to ensure everything was
connected correctly.

ECS Lab www.xilinx.com 7-17

1-877-XLX-CLAS