CDM Simulation Study of a System-in-Package

Vrashank Shukla and Elyse Rosenbaum

Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign
1308 W. Main St. Urbana, IL 61801 USA, tel.: 1-217-244-0578, e-mail: [email protected]

Abstract – This work presents a CDM circuit-level model for stacked die in a BGA package. Circuit simulation
is used to investigate the voltage stress on the die-to-die interface circuits. The power net connections are found
to impact the CDM reliability. An ESD protection scheme for the die-to-die interface circuits is proposed.

I. Introduction II. CDM Simulation Model for

Charged device model ESD events are
full-component events. Specifically, during a
Stacked BGA
field-induced CDM test (FICDM) [1], charge flows This work considers the response of a doubly-
through the pogo pin to the various conductive stacked die in a BGA package to FICDM testing. A
surfaces within the component under test, in order to capacitive model of this system was obtained using
support the potential difference between the grounded the CSURF 3-D capacitance modeling tool [7]. The
component and the field charge plate. To simulate most significant static charge storage capacitors are
such events, one must model all the charge storage shown in Figure 1. For quantitative modeling
sites and the corresponding discharge paths. purposes, the pogo pin length is set to 2.74 mm, the
Circuit-level models for CDM discharges to single- package thickness excluding the package balls is 1.4
die integrated circuits have been previously reported mm, and the package substrate thickness is 0.5 mm.
[2][3][4]; furthermore, CDM risk analysis for such The package size is 10mm x 10mm, Die1 size is 3
ICs has been performed [5]. The CDM issue for mm x 3 mm, and Die2 is 4 mm x 4 mm.
System-in-Package (SiP) designs was mentioned in
[6], but the reliability risk from a CDM discharge to
an integrated circuit in a stacked die package is still
largely unknown. Circuit simulation models for SiP
ICs have not yet appeared in the open literature. This
work presents a charge storage model for doubly-
stacked die in a ball grid array (BGA) package,
proposes a circuit simulation model for CDM events
in such an IC, and presents simulation results based
on the model.
The main focus of this paper will be on the CDM
reliability of die-to-die interface circuits. First, this
work explores whether a CDM protection circuit
should be placed on the driver die or the receiver die Figure 1 Charge storage model for a stacked die BGA
or both; it also considers what size protection devices
are needed. Next, the power net connections are Figure 2 shows a high-level schematic
considered. The power and ground nets of the two representation of the CDM model for this component.
dies may be connected together in the package Rtrace and Ltrace represent the impedance of a package
substrate or they may be isolated from one another; trace. Cint-die2-vss and Cint-die2-vdd represent the distributed
the power net connection will be shown to affect the capacitances that couple the power and ground busses
ESD robustness. of Die2 to the charge plate of the tester. Their values
are functions of the total interconnect area of the

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 Figure 2 Schematic representation of the CDM model of a doubly-stacked BGA

power and ground nets, the distance to the charge of the ground busses are connected together in the
plate, and the area of Die1, which partly shields Die2 package substrate. This work examines the CDM
from the charge plate. Similarly, Cint-die1-vss and reliability of interface circuits in which the driver is in
Cint-die1-vdd are the bus capacitances of Die1 with the VSS1 domain on Die1 and the receiver is in the
respect to the charge plate. The Die1 substrate is VSS2 domain on Die2. The driver and the receiver are
shielded from both the tester plates, so it is not connected directly through a single bondwire. In total,
included in the model. It is shielded from the ground there are 4 signal connections between Die1 and Die2;
plate due to the presence of the bigger die below it. It these are made through die-to-die interface circuits
is assumed to be shielded from the charge plate of the similar to the one shown in Figure 3. Each die has 18
tester by the metal interconnects on the die top-side. external I/O pads.
This is a reasonable assumption; in many designs, the The full simulation netlist stitches together the
metal coverage is high. The Die2 substrate is shielded models of Figures 1, 2 and 3. The netlist describes all
from the charge plate but is capacitively coupled to the components shown in the figures, including the
the ground plate of the CDM tester; therefore, as on-chip ESD protection at the signal pads, power and
indicated in the figure, the Die2 silicon substrate is ground bus resistances for each die, decoupling
included in the CDM simulation model. The substrate capacitors between the power and the ground busses
model used in this work is adopted from [8]. on each die, the driver and the receiver circuits, and
The details of the connections between Die1’s on- the bondwire impedances. The power clamps are
chip ESD protection network and that of Die2 are not active clamps [9]. The active clamps are triggered by
included in Figure 2. These connections may exist due an RC timer with time constant sufficient to detect the
to a shared ground net, a shared power net, or an I/O fast rising CDM event. Gate current models valid in
connection between the dies. Such connections are the high voltage regime were used for the thin oxide
either made directly or through a shared bondfinger transistors in the driver and the receiver circuits.
on the package substrate. Logic gates may become activated during a CDM
This paper presents CDM simulation results for a event, particularly if the power clamps turn on,
48-ball BGA that contains 2 dies in a stacked indicating a positive potential difference between
configuration, both belonging to a 90-nm bulk process VDD and VSS. The logic gate outputs may be driven
technology and each having 34 pads. Each die has a either high or low. The stress across the gate oxide of
total of 6 power pads split evenly between its two the receiver NMOS is generally worse when the
power domains. Similarly, each die has 6 ground driver output is high and thus, for the simulations
pads split evenly between its two power domains. All presented here, the driver input, Vpre-driver, was tied to

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the ground net. All of the simulation results presented busses. The die-to-die interface circuits do not lie on
here correspond to a pre-charge voltage of 300V. the main discharge path; nevertheless, simulations
Although Figure 3 was drawn for the case of a dual- show that a significant voltage stress may be induced
diode protection circuit at the receiver input, on the unprotected receiver gate oxides when a
simulations were conducted both with and without ground pin is zapped. This is shown in Figure 4 by the
ESD protection at the input of the receiver and at the curve labeled “Rx NMOS Vgs.” Vgs is a good measure
output of the driver. Furthermore, although Figure 3 of the stress applied to the gate oxide. An expression
was drawn for the particular case that the VDD1 and for the gate-to-source voltage of the receiver NMOS
VDD2 nets are shorted together in the package is given below, using the node names established in
substrate, simulations were also conducted for the Figure 3:
case of isolated power nets. V gs − nmos = VG − V S − N ≈ V 1 − V S − N (1)
The following sections present simulation results for
CDM zaps to one of two package balls: (i) a ball V 1 − VS − N = V power −clamp + (V 2 − VS − N ) (2)
belonging to the ground net, or (ii) a ball connected to V 2 −V S − N = (V 2 − VCGP ) − (VS − N − VCGP ) (3)
an I/O pad on Die2.

7 7
6 Rx NMOS Vgs 6
5 V2-Vs-n 5

Current (A)
Voltage (V)
4 Pogo Pin Current 4
3 3
2 2
1 1
0 0
-1 -1
0.5 1 1.5 2 2.5 3
Time (ns)
Figure 4. Transient plot of receiver NMOS Vgs and the discharge
current measured at the pogo pin. NMOS Vgs is a strong function
of the voltage drop across the bundles of bondwires connecting
the on-chip ground nets to the package; this is labeled V2-Vs-n.

Figure 4 shows that the quantity ሺܸʹ െ ܸௌିே ሻ is the

primary component of the voltage stress across the
Figure 3. Schematic of a die-to-die interface circuit and some receiver NMOS gate oxide. ሺܸʹ െ ܸௌିே ሻ may be
CDM-relevant parasitic elements. The driver is on Die1 and expressed as the difference between the voltage drop
receiver on Die2. The signal line is not connected to any package across the VSS1 net of Die1, ሺܸʹ െ ܸ஼ீ௉ ሻ, and the
ball. Only 1 representative bondwire connection is shown for the voltage drop across the VSS2 net of Die2,
power and ground connections; however, there are multiple pads
dedicated to power and ground. Schematic is shown for the case ሺܸௌିே െ ܸ஼ீ௉ ሻ. These two quantities are plotted in
of common power and ground connections. VSS1 and VSS2 Figure 5; they are comprised primarily of the ‫݅݀ ܮ‬ൗ݀‫ݐ‬
bondwires connect to a ground plane in the package. Similarly
VDD1 and VDD2 bondwires connect to common plane in the
voltage drops across the VSS1 and VSS2 bondwire
package. inductances.
The stress on the receiver PMOS gate oxide is
determined by the voltage drop across the bondwires
that connect the VDD1 and VDD2 power nets
III. Simulation Results together. Simulations show that both the current along
these paths and its time derivative are lower than
A. Zapping a Ground Ball those through the VSS bondwires, resulting in a
The package-level connections between VDD1 and somewhat reduced stress on the PMOS gate oxide.
VDD2 and between VSS1 and VSS2 provide
discharge paths for static charge. Therefore, the main
discharge paths lie along the ground and power

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 12 6
10 Vs-n - Vcgp 5 M1 Vgs

Voltage (V)
8
Voltage (V) 4
V2-Vcgp 3 M3 Vds
6
4 2
1 M3 Vgs
2
0 0
-2 -1
-4 -2
0.5 1 1.5 2 2.5 3
0.5 1 1.5 2 2.5
Time (ns) Time (ns)
Figure 5 Voltage drops across the bondwire inductance of the Figure 7 Plots of voltage stress across the receiver transistor M1
ground nets belonging to the driver die and the receiver die shown in Figure 6
2. Effect of Bondwire Inductance
1. Effect of Interface Circuit Topology
If the VSS2 bondwire inductance is held constant
The actual circuits at a die-to die-interface are and the VSS1 bondwire inductance increases, the
generally more complex than those shown in Figure 3. stress voltage at the interface circuit will increase
The simulations described in the previous section proportionally, as shown in Figure 8(a). In practice,
were repeated after redesigning the interface circuit to this means that increasing the length of the ground
consist of the analog driver and receiver shown in bondwires to the driver die will increase the stress
Figure 6. The simulation plots in Figure 7 confirm voltage at the receiver. It also means that the stress
that the stress on the receiver transistor can be voltage at the receiver can be reduced by connecting
significant, even for a more realistic circuit topology. more bondwires to ground in parallel. This can be
Therefore, in subsequent sections, simulation results achieved by having more ground pads, if the on-chip
will be presented only for the simple interface circuit bus resistance between the ground pads is low.
of Figure 3. In principle, the voltage stress at the receiver will be
minimized by forcing the potential difference
ܸʹ െ ܸௌିே to zero, that is, by balancing the voltage
drops across the ground paths in Die1 and Die2 (refer
to (2) and Figure 5). Eq. (2) might seem to suggest
that the voltage stress can be further reduced by
making ܸʹ െ ܸௌିே negative, that is, by making
ሺܸௌିே െ ܸ஼ீ௉ ሻ larger than ሺܸʹ െ ܸ஼ீ௉ ሻ, a condition
that can be achieved by sufficiently increasing
Lbw-VSS2. However, ܸʹ െ ܸௌିே changes polarity
between the rising and falling edges of the discharge.
Indeed, as shown in Figure 8(b), the voltage stress
across the receiver NMOS gate oxide reaches a
minimum when Lbw-VSS2 is made only slightly larger
Figure 6 Analog interface circuit between Die1 and Die2. Vbias1
than Lbw-VSS1. Unfortunately, ‫ܮ‬௕௪ି௏ௌௌଵ ൐  ‫ܮ‬௕௪ି௏ௌௌଶ is
and Vbias2 are provided by on-chip bias generation circuits (not
shown). CDM simulation is for a zap on a ground ball. The the usual case, due to the relative placement of the die
package connections are same as those shown in Figure 3. inside the package. In Figure 8(b), the minimum does
not occur when ‫ܮ‬௕௪ି௏ௌௌଵ ൌ  ‫ܮ‬௕௪ି௏ௌௌଶ because
unequal amounts of charge are stored on each die,
leading to different currents flowing through the
VSS1 and VSS2 bondwire inductors. Specifically,
more charge is stored on Die1 because it sits closer to
the charge plate.

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 8 discharge path and thus carry very little current. Once
Peak NMOS Vgs (V)
the diode is made adequately large, say 40-m
7 Lbw-VSS2=1nH
perimeter, significant additional reduction in the
6 voltage stress is not obtainable by further increasing
the diode size, but can be achieved by reducing the
5 voltage drop across the power clamp.
4

Peak NMOS Vgs (V)

1 2 3 4 5 7
Inductance per bondwire Lbw-VSS1 (nH)
(a) 6
Cdie2=3.4pF
6 5
Peak NMOS Vgs (V)

5
4 4
3
4 6 8 10 12
2 Lbw-VSS1=2nH Cdie1 (pF)
1 (a)
0
6

Peak NMOS Vgs (V)

0 1 2 3
Lbw-VSS2/Lbw-VSS1
(b) 4
Figure 8 Effect of bondwire inductance on the stress at the 2
receiver NMOS. There are 3 ground pads and 3 identical Cdie1 =5.1pF
bondwires for each ground net; the per bondwire inductances are
listed on the dataplots. (a) Inductance of the VSS1 bondwires is
0
varied. (b) Inductance of the VSS2 bondwires is varied. 0 1 2 3 4
Cdie2/Cdie1
3. Effect of Charge Storage Capacitance (b)
Figure 9 shows plots of the peak voltage stress Figure 9 Effect of charge storage capacitance on the stress at the
across the receiver NMOS gate oxide as a function of receiver NMOS
the total capacitance of either die with respect to the
charge plate. The total capacitance for each die is the There are two other options for ESD protection at a
sum of all the capacitances that couple it to the charge die-to-die interface: the protection circuit may be
plate, Cint-die1-vdd, Cint-die1-vss, Cbondpad and Cbondfinger. In placed on the driver die or protection circuits may be
the simulations, the values of these individual placed on both driver and receiver die. A transient
capacitors were changed and the resulting voltage plot of the receiver Vgs is given in Figure 11 for each
stress is plotted in Figure 9. The data of Figure 9(a) of the three different protection strategies. By
indicate that the stress increases as the total comparing the waveforms, one concludes that the
capacitance on the driver die (Cdie1) is increased. In stress is minimized when the protection devices are
contrast, increasing the total amount of capacitance on placed only on the receiver side. One might have
the receiver die (Cdie2) may reduce the stress, as expected that placing protection devices on both dies
shown in Figure 9(b). As before, the stress on the would provide the best results. However, augmenting
receiver NMOS is minimum when the voltage drops the receiver-side diodes with driver-side diodes
across the ground paths in Die1 and Die2 are increases the receiver Vgs because additional current
balanced. flows through the driver-side diodes into the signal
line and through the diode clamps at the receiver.
4. Placement and Size of the CDM A most interesting observation arising from Figure
Protection Circuit 11 is that placing protection devices only on the driver
The stress across the receiver transistors’ oxides can side is wholly ineffective. In this case, the stress
be drastically reduced by placing ESD voltage clamps across the receiver is still determined by the voltage
at the receiver input. This conclusion is reached based drops across the bondwires of the ground and the
upon the data in Figure 10. Small receiver-side diodes power nets.
suffice, because these devices lie off the main

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 8 B. Zapping a Signal Ball
Peak |Vgs| (V) 6 Isolated Power Figure 12 presents a CDM model of the die-to-die
interface circuit that is relevant to the case of a zap
Shared Power
4 being applied to a signal ball connected to an external
I/O on Die2. This is the worst case stress condition for
2 a Die1 to Die2 interface. The current from Die1 flows
through the VSS1 bondwires and the VSS2 bondwires
0 into the zapped signal ball. The amount of voltage
0 40 80 120 160 200 stress is determined by the sum of voltage drops
ESD diode perimeter (μm) across the ground nets of the two dies, not by the
Figure 10 Stress on the receiver NMOS gate oxide for the case of
difference. This is evidenced by the plus sign in Eq.
a shared power net and the case of isolated power nets. ESD (6).
diodes at the receiver reduce the stress in both cases. The voltage
stress is plotted vs. the perimeter of each diode in the protection
circuit. V gs − nmos = VG − V S − N ≈ V 1 − V S − N (4)
V 1 − VS − N = V power −clamp + (V 2 − VS − N ) (5)
6
Receiver Vgs (V)

No Prot-Prot V 2 −V S − N = (V 2 − VCGP ) + (VS − N − VCGP ) (6)

4 Prot-Prot

2 Prot-No Prot Figure 13 provides a comparison of the voltage

stress resulting from a signal pin zap with that
0 resulting from a VSS pin zap. The plots confirm that
the voltage stress is higher when the signal pin is
-2 zapped, regardless of whether ESD protection is
employed at the receiver. Furthermore, for both stress
0.5 1 1.5 2 2.5 3 cases, receiver-side protection devices can mitigate
Time (ns) the stress.
Figure 11 Transient plots of receiver NMOS Vgs in 3 cases: For a signal pin zap, the ratio of the bondwire
(i) No protection on the driver side, protection on the receiver side inductances and the ratio of die capacitance, as
(No Prot-Prot) (ii) Protection on both the driver and the receiver described in sections A.2 and A.3 are unimportant,
side (Prot-Prot) (iii) Protection on the driver side, no protection on only the individual values determine the stress
the receiver side (Prot-No Prot)
magnitude. However, the results presented in sections
A.1 and A.4 are relevant to this stress mode.
5. Effect of the Power Net Connection
Alternatively, the power nets VDD1 and VDD2 may
be routed to package balls that are isolated at the
package level. This case was simulated. Note that the
ground nets VSS1 and VSS2 are assumed to be
connected in the package, as in the previous case. The
resulting stress on the receiver NMOS is given by the
curve in Figure 10 labeled ‘Isolated Power.’ A
comparison of the two datasets in Figure 10 indicates
that the stress is greater in the isolated power net case.
The shared power net connection provides a parallel
path for the CDM discharge current leading to a lower
current through the ground bondwires. In the case of
isolated power nets, all the current flows through the
ground path, leading to a higher voltage stress.

Figure 12 Schematic of the die-to-die interface circuit showing a

CDM zap on a signal ball belonging to die2

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 10 parasitics and substrate resistance on the CDM
failure levels,” Microelectronics Reliability, vol.
Peak NMOS |Vgs| (V)
8
Signal Pin Zap 43, pp. 1569-1575, 2003.
6
[3] M. Etherton, “Charged device model (CDM) ESD
VSS Pin Zap
4 in ICs,” PhD dissertation, Eidgenössische
2 Technische Hochschule Zurich, 2006.
[4] J. Lee, Y. Huh, J. Chen, P. Bendix and S. M.
0
Kang, “Chip level simulation for CDM failures in
40 0
80 120 160 200 multi-power ICs,” in Proceedings of the
Perimeter of each diode in the dual diode
EOS/ESD Symposium, 2000, pp. 456-464.
protection circuit (μm)
Figure 13 Stress on the receiver NMOS gate oxide is worse when [5] E. R. Worley, “Distributed gate ESD network
an external signal pin on die2 is zapped architecture for inter-power domain signals,” in
Proceedings of the EOS/ESD Symposium, 2004,
IV. Conclusions pp. 238-247.
Circuit-level simulations were used to formulate [6] H. Gossner, K. Domanski, S. Druen, K. Esmark,
predictions about the stress induced at the die-to-die P. Pessl, C. Russ, C. Stadler, W. Zangl, “SoC –
interface circuits in a stacked die BGA during CDM A Real Challenge for ESD Protection?”, in
events. The results of this study will direct the design Proceedings of the EOS/ESD Symposium, 2005,
of SiP CDM test vehicles. The simulation results pp. 245-254.
indicate the following. (i) Bondwire inductances cause [7] T.T. Lu, et al., IEEE Trans. On Microwave Theory
large gate oxide stress at the receiver at a die-to-die Tech., vol.52, pp.10-19, Jan 2004
interface. (ii) Small voltage clamps placed only at the [8] V. Shukla, N. Jack and E. Rosenbaum, “Predictive
receiver input reduce the stress. Increasing the size of Simulation of CDM Events to Study Effects of
the clamp devices does not improve reliability but will Package, Substrate Resistivity and Placement of
increase capacitive loading. (iii) A shared power ESD Protection Circuits on Reliability of
connection at the package level provides overall Integrated Circuits”, in Proceedings of the IEEE
enhancement of ESD reliability International Reliability Physics Symposium,
Although die-to-die interface circuits may be 2010, pp. 485-493.
considered analogous to power domain crossing [9] C. Torres, J. Miller, M. Stockinger, M. Akers, M.
circuits in (single-die) SoC [4], the reliability hazard Khazhinsky and J. Weldon, “Modular, portable
is much greater in SiP due to the bondwire and easily simulated ESD protection networks for
inductances that link the ground nets. In a SoC, the advanced CMOS technologies,” in Proceedings of
ground nets are connected by the Si substrate and, the EOS/ESD Symposium, 2001, pp. 82-95.
usually, anti-parallel diodes. These provide a lower
impedance discharge path.

Acknowledgments
This work is partially supported by the National
Science Foundation (grant NSF ECCS 0725406).
Vrashank Shukla is supported by a grant from the
Semiconductor Research Corporation. Elyse
Rosenbaum acknowledges a Micron Professorship
Award.

References
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