VIET NAM NATIONAL UNIVERSITY HO CHI MINH CITY – UNIVERSITY OF

TECHNOLOGY
FACULTY OF ELECTRICAL AND ELECTRONICS ENGINEERING
DEPARTMENT OF ELECTRONICS
--oOo—

INTRODUCTION TO COMPUTING
LABORATORY MANUAL
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

LAB 2: IMPLEMENTATION OF BASIC

LOGIC GATES AND FUNCTIONAL ICs
ON FPGA
Student’s names: Group 02 Class: TT04
Student ID: Date:

A. PRELAB
In Lab 2, the project use the LEDR, LEDG, and SW as peripherals. Below are the basic
headers code of these peripherals when students synthesize a project on Intel Quartus.
(Note: Import file DE2_pin_list/assignment).

Note, the top-level file of the project must be named the name of the header file, for
example "lab2tn1_wrapper", with the module "lab2tn1" being the module containing the
code describing the design of experiment 1.

𝑓(𝑥, 𝑦, 𝑧) = x̅𝑦𝑧 as experiment 1 of lab 2, we have the following SystemVerilog code:

Ex: The experiment of writing hardware design in SystemVerilog language for the function

Figure 2.1: Implementation of 𝑓(𝑥, 𝑦, 𝑧) = 𝑥̅𝑦𝑧 – module “lab2tn1”

Below is top level “lab2tn1_wrapper” that implement 𝑓(𝑥, 𝑦, 𝑧) = x̅𝑦𝑧:

 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

Figure 2.2: Implementation of 𝑓(𝑥, 𝑦, 𝑧) = 𝑥̅𝑦𝑧 – module

“lab2tn1_wrapper” Next, students perform the simulation, and load the Kit as

instructed at Lab 0.
For the experiments that require the use of IC 74LS151/74LS138, students write the code
describing this IC and call that module as above.
PREPARATION 1
Objective: Implementation of Boolean function 𝑓(𝑥, 𝑦, 𝑧) = 𝑥̅𝑦𝑧 + ̅𝑥𝑦̅̅𝑧 + 𝑥𝑦 on FPGA
DE2.
Procedure:
● Construct the truth table of 𝑓(𝑥, 𝑦, 𝑧) = 𝑥̅𝑦𝑧 + ̅𝑥𝑦̅̅𝑧 + 𝑥𝑦
● Write the SystemVerilog code that describe 𝑓(𝑥, 𝑦, 𝑧) = 𝑥̅𝑦𝑧 + ̅𝑥𝑦̅̅𝑧 + 𝑥𝑦s
instructed in lab 0 with the following pin assignment:
○ Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0
respectively.
○ Pin f assigned to LEDG0.
● Compile and simulate the project. The output waveform have to show all possible input
combinations. Capture the output waveform.
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

SystemVerilog code
Truth table

x y z f

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

Waveform:

PREPARATION 2
X Y Z F Fsim FKit
0 0 0 1 1 1
0 0 1 1 1 1
0 1 0 0 0 0
0 1 1 1 1 1
1 0 0 1 1 1
1 0 1 0 0 0
1 1 0 0 0 0
1 1 1 1 1 1
Objectives: Write SystemVerilog code to describe the truth table in Table 2.1.

𝑭(𝒙, 𝒚, 𝒛) = 𝒙̅𝒚̅ + 𝒚𝒛 + 𝒚̅𝒛̅

Table 2.1

Procedure:
● Write the SystemVerilog code that describe the digital circuit in Figure 2.3 with
the following pin assignment:
○ Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0
respectively.
○ Pin f assigned to LEDG0.
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

● Compile and simulate the project. The output waveform have to show all possible
input combinations. Capture the output waveform.
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

SystemVerilog code
Truth table

x y z F

0 0 0 1

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

Waveform:

PREPARATION 3
Objective: Write SystemVerilog code to describe the digital circuit in Figure 2.3.

Figure 2.3
Procedure:
● Write the SystemVerilog code that describe the digital circuit in Figure 2.3 with
the following pin assignment:
○ Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0
respectively.
○ Pin f assigned to LEDG0.
● Compile and simulate the project. The output waveform have to show all possible
input combinations. Capture the output waveform.
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

SystemVerilog code
Truth table

x y z F

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 0
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

Waveform:

PREPARATION 4

function 𝑓(𝑥, 𝑦, 𝑧) = ∑(1,2,4,7) using that multiplexer.

Objective: Write SystemVerilog code to describe IC Multiplexer 74LS151. Implement

Procedure:
● Write SystemVerilog code describe IC multiplexer 74LS151 operation.

𝑓(𝑥, 𝑦, 𝑧) = ∑(1,2,4,7):
● Using above multiplexer, write SytemVerilog code implementing Boolean function

○ Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0

respectively
○ Pin f assigned to LEDG0
○ Call IC 74LS151 as a submodule.
● Compile and simulate the project. The output waveform have to show all possible
input combinations. Capture the output waveform.
Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

Truth table
SystemVerilog code

x y z F

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

Waveform:

PREPARATION 5

function 𝑓(𝑥, 𝑦, 𝑧) = ∑(0,2,5,7) using that decoder.

Objective: Write SystemVerilog code to describe IC Decoder 74LS138. Implement

Procedure:
● Write SystemVerilog code describe IC decoder 74LS138 operation.

𝑓(𝑥, 𝑦, 𝑧) = ∑(0,2,5,7):
● Using above decoder, write SytemVerilog code implementing Boolean function

○ Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0

respectively
○ Pin f assigned to LEDG0
○ Call IC 74LS138 as a submodule.
● Compile and simulate the project. The output waveform have to show all possible
input combinations. Capture the output waveform.
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

Truth table
SystemVerilog code

x y z F

0 0 0 1

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

Waveform:
Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

B. LAB MANUAL:

I. OBJECTIVES:

- Understand how to use FPGA kits, programming software .

- Understand how to design a basic functional ICs on FPGA
- Understand the process of describing hardware on FPGAs.

II. LAB PREPARATION:

- To prepare well for the test, students MUST read Appendix 1 first and complete
the steps of Sample lab in Appendix 2, and submit it with Prelab 2 before entering
class.
- Students must complete and submit Prelab 2 before entering class.
- Students read the appendix and the Kit DE2 Manual to understand how to use the
DE2 Kit, wiring, peripherals, and how to use Quartus software to simulate and
synthesize circuits. Students refer to the documentation to understand how to write
hardware designs in the SystemVerilog language.

III. LAB INSTRUCTIONS:

EXPERIMENT 1
Objectives: Implementation of a function math 𝑓(𝑥, 𝑦, 𝑧) = 𝑥̅𝑦𝑧 + ̅𝑥𝑦̅̅𝑧 + 𝑥𝑦 on
DE 2 kit.
Procedure:
x y z f fSim fKit
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 2.2

➢ Apply all possible combinations to the inputs and take note the outputs in the f
column of Table 2.2.
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

➢ Draw the logic diagram of F:

➢ Write the SystemVerilog describe the operation of 𝑓(𝑥, 𝑦, 𝑧) = 𝑥̅𝑦𝑧 + ̅𝑥𝑦̅̅𝑧

+ 𝑥𝑦 with the pin assignment as follows:
o Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0
respectively. o Pin f assigned to LEDG0.

➢ Synthesize the SystemVerilog design and take note the output in the fsim column in
Table 2.2.

(Insert a photo demonstrating simulation results)

 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

➢ Students view the result of the circuit (Tool → Netlist Viewer → RTL Viewer). Is
this result similar to the logic gate diagram drawn above? Exlain.

(RTL viewer result)

➢ Download the code to DE2 Kit. Does the design perform exactly as required? Take
note the results in f Kit column of Table 2.2
(Project demonstration on DE2 kit)
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

EXPERIMENT 2
Objectives: Implementation of a boolean function given in the truth table on DE 2 kit.
X Y Z F Fsim FKit

0 0 0 1

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1
Table 2.3
Procedure:
➢ Write the Boolean expression of f (x, y, z):

➢ Draw the logic diagram of f:

 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

➢ Write the SystemVerilog describe the operation of 𝑓(𝑥, 𝑦, 𝑧) with the pin
assignment as follows:
o Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0
respectively. o Pin f assigned to LEDG0.

➢ Synthesize the SystemVerilog design and take note the output in the fsim column in
Table 2.3.
(Insert a photo demonstrating simulation results)
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

➢ Students view the result of the circuit (Tool → Netlist Viewer → RTL Viewer). Is
this result similar to the logic gate diagram drawn above? Exlain.
(RTL viewer result)

➢ Download the code to DE2 Kit. Does the design perform exactly as required? Take
note the results in f Kit column of Table 2.3.
(Project demonstration on DE2 kit)

EXPERIMENT 3
Objectives: Implementation of a boolean function given in the following schematic.
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

X Y Z Fsim FKit
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Figure 2.4 Table 2.4

Procedure:

➢ Write the SystemVerilog describe the operation of 𝑓(𝑥, 𝑦, 𝑧) with the pin
assignment as follows:
o Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0
respectively. o Pin f assigned to LEDG0.
➢ Synthesize the SystemVerilog design and take note the output in the fsim column in
Table 2.4.
(Insert a photo demonstrating simulation results)

➢ Students view the result of the circuit (Tool → Netlist Viewer → RTL Viewer). Is
this result similar to the logic gate diagram drawn above? Exlain.
(RTL viewer result)
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

➢ Download the code to DE2 Kit. Does the design perform exactly as required? Take
note the results in f Kit column of Table 2.4.
(Project demonstration on DE2 kit)

EXPERIMENT 4
x y z f fsim fKit
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

1 0 1
1 1 0
1 1 1
Objectives: Write SystemVerilog code to describe IC Multiplexer 74LS151.
Implement function 𝑓(𝑥, 𝑦, 𝑧) = ∑(1,2,4,7) using that multiplexer.

Table 2.5

Procedure:
➢ Draw the circuit that implement f(x,y,z) using 74LS151.

➢ Write SystemVerilog code describe IC multiplexer 74LS151 operation.

𝑓(𝑥, 𝑦, 𝑧) = ∑(1,2,4,7):
➢ Using above multiplexer, write SytemVerilog code implementing Boolean function

o Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2,

LEDR1, LEDR0 respectively
o Pin f assigned to LEDG0 o Call IC 74LS151 as a

submodule. ➢ Synthesize the SystemVerilog design

and take note the output in the fsim column in

Table 2.5. (Insert a photo demonstrating simulation results)

 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

➢ Students view the result of the circuit (Tool → Netlist Viewer → RTL Viewer). Is
this result similar to the logic gate diagram drawn above? Exlain.
(RTL viewer result)

➢ Download the code to DE2 Kit. Does the design perform exactly as required? Take
note the results in f Kit column of Table 2.5.
(Project demonstration on DE2 kit)
 Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA

EXPERIMENT 5
x y z f fsim fKit
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Objectives: Write SystemVerilog code to describe IC Decoder 74LS138.
Implement function 𝑓(𝑥, 𝑦, 𝑧) = ∑(0,2,5,7) using that decoder.

Table 2.6

Procedure:
➢ Draw the circuit that implement f(x,y,z) using 74LS138.
Lab 2: Implementation of Boolean function with logic gates and functional
on ICs
FPGA
 Appendix 2: Sample lab.

➢ Write SystemVerilog code describe IC decoder 74LS138 operation.

function 𝑓(𝑥, 𝑦, 𝑧) = ∑(0,2,5,7):

➢ Using above multiplexer, write SytemVerilog code implementing Boolean

o Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2,

LEDR1, LEDR0 respectively
o Pin f assigned to LEDG0 o Call IC 74LS138 as a

submodule.
➢ Synthesize the SystemVerilog design and take note the output in the fsim column in

Table 2.5. (Insert a photo demonstrating simulation results)

➢ Students view the result of the circuit (Tool → Netlist Viewer → RTL Viewer). Is
this result similar to the logic gate diagram drawn above? Exlain.
(RTL viewer result)
 Appendix 2: Sample lab.

➢ Download the code to DE2 Kit. Does the design perform exactly as required? Take
note the results in f Kit column of Table 2.5.
(Project demonstration on DE2 kit)