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FPGA Implementation of OTFS Modulation for 6G Communication Systems

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FPGA Implementation of OTFS Modulation for 6G
Communication Systems
Murat Isik† , Malvin Nkomo, Anup Das, Kapil R. Dandekar

Abstract—Sixth-generation (6G) communication systems are in OFDM modulation. This is advantageous as the DD do-
poised to accommodate high data-rate wireless communication main representation of any rapidly-varying TF channel is
services in highly dynamic channels, with applications including both slowly varying and sparse in nature [6]. Consequently,
high-speed trains, unmanned aerial vehicles, and intelligent trans-
portation systems. Orthogonal frequency-division multiplexing modulating in the DD domain allows the received signal to
(OFDM) modulation suffers from performance degradation in interact with a DD channel that exhibits both sparsity and
such high-mobility applications due to high Doppler spread in slow variability. This interaction improves the performance
the channel. The recently proposed Orthogonal Time Frequency in terms of throughput and error rate, compared to a signal
Space (OTFS) modulation scheme outperforms OFDM in terms modulated in the TF domain that must deal with a rapidly
of supporting a higher transmitter (Tx) and receiver (Rx)
user velocity. Additionally, the highly-dynamic time-frequency changing TF channel. OTFS modulation has shown significant
(TF) channel has little effect on OTFS modulated signals, improvement in performance compared to OFDM modulation
which enables the realization of low-complexity pre-processing in high-Doppler scenarios where the user velocity was as high
architectures for implementing massive-multiple input multiple as 500 km/h in the 4 GHz band [5]. Considering mmWave
outputs (MIMO) based OTFS systems. However, while OTFS communication, OTFS outperformed OFDM in the 28 GHz
has received attention in the literature from a theory and
simulation perspective, there has been comparatively little work band at a user velocity of 40km/h [7], [8]. However, these
on real-time FPGA implementation of OTFS waveforms. Thus, results were obtained using software simulation alone.
in this paper, we first present a mathematical overview of OTFS
modulation and then describe an FPGA implementation of OTFS The ability of Field Programmable Gate Arrays (FPGAs)
implementation on hardware. Power, area, and timing analysis to implement complex digital signal processing algorithms
of the implemented design on a Zynq UltraScale+ RFSoC FPGA in real-time is making them increasingly popular in wireless
are provided for benchmarking purposes. communication systems. FPGAs are superior to traditional
digital signal processors (DSPs) in wireless communication
I. I NTRODUCTION applications due to their high parallelism, flexibility, power
Multipath propagation channels are doubly selective due to efficiency, and speed. A complex modulation scheme like
time dispersion (frequency selectivity) and Doppler shift (time OFDM requires real-time processing of large amounts of
selectivity) [1]. Both of these phenomena are due to the highly data. The high parallelism and low latency of FPGAs make
varying nature of the time-frequency (TF) channel. Fourth- them ideal for processing OFDM signals. Several processing
generation (4G) and fifth-generation (5G) communication sys- blocks are required for OFDM, including the fast-Fourier
tems address the time-dispersive nature of the channel using transform (FFT), inverse fast-Fourier transform (IFFT), modu-
orthogonal frequency division multiplexing (OFDM), which lation, demodulation, and channel estimation. Various wireless
mitigates inter-symbol interference (ISI) through the use of a communication systems can be easily prototyped by modifying
cyclic prefix and longer symbol duration [2], [3]. However, a IP cores used by FPGAs to implement these processing blocks.
high-velocity communication scenario produces high Doppler FPGAs provide real-time processing of data, which is essential
shifts, which destroys the orthogonality of the sub-carriers for wireless communication systems to provide reliable and
generated by the OFDM modulator, thus causing inter-carrier efficient communication [9]–[12]. All of these characteristics
interference (ICI) [4]. While OFDM cannot mitigate the effects also make FPGAs ideal for prototyping OTFS systems prior
of high Doppler shifts, the recently proposed orthogonal time to standardization.
frequency space (OTFS) modulation scheme is highly effective We propose that FPGA implementation would be a powerful
in these environments due to its delay-doppler characteris- solution for evaluating wireless communication modulation
tic[5]. schemes such as OTFS. The high parallelism, high flexibil-
OTFS modulation multiplexes the information in the Delay- ity, low power consumption, and high processing speed of
Doppler (DD) domain in contrast to the TF domain used FPGAs make them an ideal platform for the processing of
† Corresponding
large amounts of data required by wireless communication
Author.
All authors are with the Department of Electrical and Computer Engineer- systems. The use of customizable IP cores in FPGA-based
ing, Drexel University. This research is supported by the National Science implementations of OTFS provides a high degree of flexibility
Foundation under Grants CNS-1828236 and CNS-1816387. Any opinion, and allows the designer to optimize the design for specific
findings, and conclusion or recommendations expressed in this paper are those
of the author(s) and do not necessarily reflect the reviews of the National system requirements, and to prototype different variations of
Science Foundation. the waveform to help inform the design of future 6G standards.
 II. R ELATED W ORKS
ISFFT and
Information Constellation Heisenberg
trasmit
bits Mapping transform
This section summarizes recent literature on OTFS modula- windowing

tion. Hadani et al. [7] have analyzed the performance of OTFS

delay-Doppler
modulation in millimeter wave systems under the influence channel

of phase noise, Doppler spread, and delay spread defined by

Receive
various cellular band standards. Emanuele et al. [13] analyzed Information Constellation
windowing
Wigner
bits De-mapping transform
and SFFT
the diversity of OTFS over two-path channels. The results TF Domain

show that OTFS has a lower bit-error rate (BER) than OFDM DD Domain

in a number of varying case scenarios. Chockalingam et al. Fig. 1. Block diagram of an OTFS transceiver system
[14] described a low-complexity detection scheme according
to Markov chain Monte Carlo (MCMC) sampling techniques p
and a Pseudo-Noise (PN) graph sequence-based channel esti- m Data embedded ΩDD
in DD plane
mate technique for the DD domain. N
There is comparatively little research on real-time FPGA ΣTF

frequency
hardware implementations of OTFS waveforms. [15], [16] M

delay
2D SFFT
have performed the Software-defined radio (SDR) implemen-
tation of an OTFS modem. [15] studied the performance of 2D ISFFT
OTFS and OFDM modulation systems in real indoor wireless Δf Δ
channel scenarios. [16] presents the performance of an OTFS N n
T time M q
system, where the received signal extracted from a 60GHz Δτ
doppler
millimeter wave carrier frequency is passed through a Linear Fig. 2. TF and DD plane
Minimum Mean Square Error (LMMSE) equalizer.
In a study by [17], a novel VLSI architecture for OTFS
modulation was proposed for high-speed vehicular communi- present OTFS implementation on an FPGA board.
cation scenarios. The authors presented a report on resource
III. OTFS M ODULATION
utilization for implementation of OTFS on an FPGA board,
as well as a demonstration of the input-output relationship OTFS modulation can be implemented as an extension to the
of an OTFS signal on a single input, single output channel existing OFDM modulation framework for 4G communication
under additive white gaussian noise conditions. A CORDIC systems [6]. An OTFS transceiver system starts with the con-
processor was used for non-linear function generation (sin(θ), stellation mapping of the information bits on a discretized DD
cos(θ), etc) for designing the transmitter and receiver. This plane. The data symbols in the DD domain are then converted
design was implemented on a Xilinx Zynq-7 FPGA board, to the TF domain symbols using the two-dimensional (2D)
thus demonstrating a power-efficient approach. Our paper Inverse Symplectic Finite Fourier transform (ISFFT) at the
uniquely provides a detailed performance analysis, including transmitter side. This is followed by the Heisenberg transform,
power, area, and timing, which were previously unexplored in which converts the TF symbols to a time-domain signal.
hardware implementations of OTFS, thus contributing to the This signal is then pulse-shaped with a suitable window and
advancement of practical applications for 6G communications is sent over the channel. The transmitted OTFS frame also
systems. includes additional pilot symbols for channel estimation. In
More recently [18], a low-complexity implementation of the receiver, the received time-domain signal is converted back
an OTFS transmitter was proposed using a fully parallel and to the symbols in the DD domain with the help of the Wigner
pipelined hardware architecture. FFTs and IFFTs were parallel transform, followed by an SFFT operation on the received
and depth pipelined on an FPGA to accelerate OTFS execu- signal. Fig. 1 provides a block diagram of the OTFS system.
tion, resulting in high accuracy and performance. The authors The mathematical representations of the above process are
also proposed an optimized OTFS transmitter architecture with shown below:
a modified Booth multiplier and memory, which needed fewer • Discretized DD and TF grids are represented as:
hardware resources while providing higher performance. The
ΩDD = {(p∆ν, q∆τ ), p = 0, ..., N −1; q = 0, ..., M −1}
OTFS hardware architecture achieved a bandwidth of 196.67
Tbps at 139.64 MHz maximum operating frequency, thus mak- ΣT F = {(nT, m∆f ), n = 0, ..., N −1; m = 0, ..., M −1}
ing it suitable for future 5G and 6G wireless communications
standards. Furthermore, the optimized hardware architecture where,  
1 1
reduced the LUTs on the Virtex-7 FPGA board by around ∆ν = , ∆τ =
20% compared to a conventional OTFS transmitter. NT M ∆f
To the best of our knowledge, and contrary to the previous The discretized grids are shown in Fig. 2.
works on OTFS which mostly focused on theoretical explana- • The input bit stream is converted to its respective infor-
tion and software simulation, this paper is one of the first to mation symbols in the IQ plane and then mapped to the
 2D DD grid ΩDD . The resultant data frame is represented
by x[p, q], having a dimension of N × M . x[p, q] resides Heisenberg
transform
in the DD domain.
• Next, the ISFFT operation in conjunction with a transmit
PRN QAM Array
windowing function maps the data frame in the DD ISFFT
Generator Modulator Reshaping
domain to its equivalent TF domain ΣT F , represented
by Xρ [n, m]: QAM
Output Top Module SFFT
N −1 M −1 Demodulator
1 np mq
FPGA
xρ [p, q]ej2π( )
X X
Xρ [n, m] = √ N − M

NM p=0 q=0
Wigner
X[n, m] = Wtx [n, m] · Xρ [n, m] transform

where, Wtx [n, m] is the square summable transmit win- Fig. 3. Top Hardware Architecture
dowing function.
• In the final step, the TF data frame is converted to a
continuous time waveform for transmission using the
Heisenberg transform:
N
X −1 M
X −1
s(t) = X[n, m]ej2πm∆f (t−nT ) gtx (t − nT )
n=0 m=0 Fig. 4. LFSR Structure
where gtx is the transmit pulse.

IV. FPGA I MPLEMENTATION The LFSR is initialized with all 1’s, and the output bit is
generated by XORing the first, third, fourth, and sixth bits
The architecture design implements the various processes in of the shift register. The generated bit is output and the shift
parallel, thus consuming less processing time. Xilinx Intellec- register is updated for each clock cycle.
tual Property (IP) cores and custom modules are used in the The code also includes control logic to set the number of
implementation that is shown in Figure 3. Modules are defined random bits to be generated based on the desired modulation
using VHDL based on the AXI Interface. The modules in the order. The number of bits is computed as follows:
design use 12-bit data configuration for the real and imaginary
• For M = 4, 8192 bits are generated (4096 × 2)
parts. A Xilinx FFT core is used to improve the efficiency
• For M = 8, 12288 bits are generated (4096 × 3)
and speed of the FFT and IFFT blocks used inside the ISFFT
• For M = 16, 16384 bits are generated (4096 × 4)
module, which has a maximum instantaneous frequency of 250
• For M = 32, 20480 bits are generated (4096 × 5)
MHz and can operate up to 50 frames/sec. This architecture
has six parts, described in the following sub-sections: After generating the required number of random bits, the
control logic sets the generator to idle mode. The generated
• Random-Bit Generator
random bits were analyzed for their auto-correlation function,
• QAM Modulator
which is depicted in Fig. 5. This figure illustrates the degree of
• Array reshaping
correlation between consecutive bits. A lower auto-correlation
• ISFFT and Heisenberg
implies a sequence with characteristics that resemble ran-
• Wigner and SFFT
domness. It is worth noting, however, that while the 16-
• QAM Demodulator
bit LFSR-generated sequence meets the requirements of this
A. Random-Bit Generator study, its predictability characteristics may vary depending on
the application context.
The generation of random bits is a fundamental requirement The generated random bit sequence is evaluated in both
for testing various communication and information processing MATLAB and VHDL environments. The auto-correlation
systems. In this regard, a simple and efficient technique for analysis of the 16-bit LFSR generated bit sequence demon-
generating pseudo-random binary sequences (PRBS) is the use strates that it closely resembles white noise, indicating that
of a linear feedback shift register (LFSR). In this current work, the generated sequence is statistically random. Moreover, a
a 16-bit LFSR is utilized to generate a 8192 bit long PRBS VHDL testbench is designed to compare the performance
sequence. The feedback loop for the LFSR is implemented of the PRBS generator implemented in VHDL with that of
using a simple configuration, as shown in Fig. 4. The LFSR the PRBS generated in MATLAB. It is observed that the
is configured as a 16-bit shift register, and the feedback generated pseudo-random bit sequences in both environments
polynomial is defined as follows: are virtually identical.
LFSR has been widely adopted for generating pseudoran-
f (x) = 1 + x11 + x13 + x14 + x16 (1) dom bit sequences due to its simplicity and efficiency [19],
 constellation’s complex symbols are represented by floating-
point numbers, with the real and imaginary parts represented
as separate values, and floating-point values are converted to
fixed-point notation, with a 10-bit resolution, thus resulting
in 12-bit signed numbers with 2’s complement signed 2.10
format. For instance, the floating-point value for 971/1024 is
represented as 0.948 in decimal notation.

C. Inverse Symplectic Finite Fourier transform (ISFFT) and

Heisenberg Transform
In this module, a 64 × 64 matrix containing 4096 complex
numbers are fed into an IFFT block and then is followed by a
transpose operation. If the transpose operation is omitted, the
system resembles the classic OFDM scenario. To complete the
Fig. 5. Autocorrelation.
ISFFT operation, this data stream is finally fed into an FFT
block.
[20]. We have chosen a 16 LFSR-based PRBS generator to The obtained IFFT results are stored in a Xilinx Block
create statistically random bit sequences in this work. These Random Access Memory (BRAM) with a capacity of 64 ×
sequences are essential for a wide range of practical applica- 64 = 4096 values. The first column of the 64 × 64 IFFT result
tions, such as in communication and information processing is stored consecutively at addresses 0 to 63, the second column
systems. This choice is supported by the inherent properties of at addresses 64 to 127, and so on. To obtain the transpose
LFSRs, which provide good statistical properties and imple- of the IFFT output, the saved data from the BRAM is then
mentation efficiency [21]. Our VHDL implementation of the processed to feed the output of the module to the transposed
generator has demonstrated reliability and performance consis- matrix. Specifically, the first column of the transposed IFFT
tent with expectations, further validating its utility. However, matrix corresponds to the values stored at addresses 0, 64,
we acknowledge that different scenarios might warrant the use 128,.., 4096-64, and the second column corresponds to the
of other methods. For instance, Xilinx offers various on-chip values stored at addresses 1, 65, 129,..., 4096-63, and so on.
random bit generators that could be leveraged depending on A snippet of the main portion of the VHDL code is shown in
the specific requirements of the system [22]. Therefore, while Alg. 1.
the 16 LFSR-based PRBS generator serves our purposes in
this study, we recognize the existence and potential suitability Algorithm 1 VHDL code for recording data from the Xilinx
of other well-established solutions in diverse scenarios. IFFT IP core.
when RECORD_IFFT_DATA =>
B. QAM Modulator and Array Reshaping RecState <= RECORD_IFFT_DATA;
A 4-quadrature amplitude modulation (4-QAM) scheme is addrb <= (others => ’0’);
implemented using VHDL. The input to the 4-QAM modula- if(m_axis_data_tvalid = ’1’) then
tion consists of 20480 bits, which are used to generate 4096 wea <= "1";
complex numbers. The generated complex numbers are then dina <= m_axis_data_tdata(42 downto 27)&
reshaped into a 64 × 64-sized array for further processing. It m_axis_data_tdata(18 downto 3);
has been observed that the 4096 complex numbers produced addra <= std_logic_vector(unsigned(addra)
by the VHDL implementation are identical to those produced ,→ +1);
by MATLAB’s built-in (qammod) function when tested using if (unsigned(addra) = 4094) then
a testbench. The proposed implementation supports multiple RecState <= OUTPUT_OTFS_DATA_0;
modulation schemes, including 4-QAM, 8-QAM, 16-QAM, end if;
and 32-QAM. The length of the input bits into the QAM end if;
modulator is defined by the modulation scheme. If the modula-
tion order is N , the input data is generated using the formula
4096 × log2 (N ). The symbol values are defined as per the Due to the limitations of the Xilinx FFT IP core, it is not
look-up tables (LUTs) used for the QAM modulation. The possible to feed the entire matrix into the FFT core. To address
QAM modulator generates the output by directly accessing this limitation, we propose using the Feed_FFT_Data state,
the LUTs and assigning the values to the real and imaginary where the columns of the matrix are fed to the FFT IP core one
parts of the modulation output. by one. The incoming data is fed to the FFT IP core operating
The constellations generated by MATLAB satisfy the unit at 100 M Hz, and the resulting FFT data is stored in Xilinx
average power property, whereby the sum of the squares BRAM. A snippet of the main portion of the VHDL code is
of the magnitudes of its complex symbols equals one. The shown in Alg. 2.
Algorithm 2 VHDL code for feeding data to the Xilinx FFT amounts to the SFFT of the transposed matrix Y. Finally, we
IP core. divide the IFFT output by the square root of the number of
when FEED_FFT_DATA => symbols divided by the number of subcarriers to obtain the
state <= FEED_FFT_DATA; demodulated OTFS signal. By using the IFFT Xilinx IP core,
if(QAMDataValid = ’1’) then we can efficiently delegate computationally intensive tasks,
s_axis_data_tvalid <= ’1’; such as FFT and IFFT calculations, to dedicated hardware,
s_axis_data_tdata <= std_logic_vector( thus improving both the performance and power efficiency of
,→ resize(signed(QAMDataIm),16)) & the design.
std_logic_vector(resize(signed(QAMDataRe)
,→ ,16)); E. QAM Demodulator
DataCount <= std_logic_vector(unsigned( In the final stage of the OTFS design, the received signal
,→ DataCount) + 1); must be demapped from the complex symbols back to the
if (DataCount(5 downto 0) = "111111") then original information bits. This is achieved by identifying the
s_axis_data_tlast <= ’1’; closest constellation point to the received symbol and then
end if; demapping it back to the corresponding bit sequence. The
if (unsigned(DataCount) = 4095) then demapping process takes into account the fixed-point notation
State <= IDLE; used earlier and converts the complex symbols back to the
end if; floating-point representation.
end if;
V. P ERFORMANCE A NALYSIS
A summary of the resource utilization report for the Zynq
UltraScale+ XCZU28DR FPGA can be found in Table I. It
D. Wigner Transform and Symplectic Finite Fourier transform contains a variety of resources including LUTs, LUTRAMs,
(SFFT) FFs, IOs, and BUFGs. The “Utilization" column shows how
The Wigner transform is an essential component in the many resources were used in the design, while the “Available"
OTFS demodulation process. At the receiver, the Wigner column shows how many resources are available in the FPGA.
Transform and SFFT are applied to demodulate the signal A percentage of utilization is also computed for reference.
back to the DD domain. Our approach involves breaking Based on the table, the utilization percentage for LUT is
down the Wigner transform into distinct operations, such as 0.40%, LUTRAM is 0.27%, FF is 0.41%, IO is 39.19%, and
complex multiplication, summation, and Fourier transforma- DSP is 0.94%. There is enough capacity for more clock buffers
tions. This enables us to focus on optimizing each opera- based on the lower utilization rate for BUFG.
tion independently before integrating them into the complete
Table I. Resource utilization summary
transformation. By designing customized IP cores for these Zynq UltraScale+ XCZU28DR
operations, we were able to optimize the performance of the Resource Utilization Available % Utilization
Wigner transform on the FPGA. The Wigner Transform is then LUT 1708 425280 0.40
LUTRAM 586 213600 0.27
performed by computing the FFT of the reshaped matrix and FF 3446 850560 0.41
dividing it by the square root of the total number of subcarriers. IO 136 347 39.19
After generating the FFT IP core, we complete the Wigner DSP 40 4272 0.94
transform process by performing complex multiplication and
conjugation of the input signals before feeding them into Table II provides an overview of the system’s capabilities
the FFT IP core, thus utilizing available Xilinx IP cores. and performance characteristics, and Fig. 6 lists the size and
Finally, the design is synthesized and implemented on the dimension of the output streams from each block. A 32-
hardware, and the results are then verified through simulations QAM modulation scheme was used for the final design. OTFS
in MATLAB and on-hardware tests. The accuracy of the modulation uses these four symbols (from 32-QAM’s mapping
results is also compared with that obtained from MATLAB table) to map information from the DD-domain to the TF-
simulation results. domain. Two bits of information are contained in each symbol.
The SFFT is an essential component in the OTFS mod- Multiplying the number of symbols by the number of bits
ulation technique. The algorithm begins by reshaping the per symbol results in 20480 bits, which denotes the total
input array into a matrix with dimensions corresponding to number of bits from the LFSR. The FFT blocks sampling
the number of subcarriers and the number of symbols. To rate is listed as 61.44 MHz. The system’s performance can
implement the SFFT component, the output from the Wigner be improved by using a higher sampling rate. This system
Transform is transposed the inverse FFT of the transposed consumes 1.45 Watt of power. There is a latency of 12.17 µs
matrix is computed. The result is normalized by division by listed for the system. This latency is quite negligible for
the square root of the number of symbols times the number any real-time implications. This design lists a throughput of
of subcarriers. We use the IFFT Xilinx IP core to calculate 503.31 Gbits/sec. The throughput of a wireless channel is the
the IFFT of the FFT of the transposed matrix Y, which speed at which data can be transmitted. This metric takes
into account the system’s power consumption and throughput await as we transition from controlled environments to real-
and provides a measure of how efficiently the system could world deployments. Addressing these challenges, which could
transmit data wirelessly. In this case, the system is able to range from interference management to integration complex-
transmit 155.38 Gigabits of data per second per watt of ities, will be instrumental in the broader adoption of OTFS.
power consumed. In comparison to recent OTFS transmitter Future work includes the integration of an RF frontend on a
implemented by [18], which achieved a bandwidth of 196.67 NI Ettus USRP X410, which leverages the same FPGA used
Tbps at a maximum operating frequency of 139.64 MHz, our in this paper, to enable over-the-air (OTA) transmission and
design has demonstrated a throughput of 503.31 Gbits/sec at a reception for studying the effectiveness of OTFS in realistic
400 MHz operation frequency. Moreover, our system’s power wireless scenarios.
consumption of 1.45 W is significantly lower than the average
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 Fig. 7. Simulation result of the system

Fig. 8. Error difference between VHDL and MATLAB implementa- Fig. 9. Error difference between VHDL and MATLAB implementa-
tion of the modulated signal. tion of the demodulated signal.

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