CSE Lec2
CSE Lec2
Lecture 2: System-on-Chip
Technology & Methodology
1
Outline
• The demand for more powerful products and the huge capacity
of today’ s silicon technology have moved System-on-Chip (SoC)
designs from leading edge to mainstream design practice.
q Energy dissipation
Reduce radiated power
More power efficient radio
Energy efficient protocols and routing algorithms
Better trade-off between communication and local computing
q Size
Higher integration (System-on-Chip or SoC)
q Cost
Standard Digital CMOS Technology
Evolution of Microelectronics: the SoC Paradigm
System on a Chip
System on a board
Evolutionary Problems
Emerging new technologies:
– Greater complexity
– Increased performance
– Higher density
– Lower power dissipation
Key Challenges
– Improve productivity
– HW/SW codesign
– Integration of analog & RF IPs
– Improved DFT
Evolutionary techniques:
- IP (Intellectual Property) based design
- Platform-based design
Migration from ASICs to SoCs
v standard cell
v full custom
Migration from ASICs to SoCs
In the mid-1990s, ASIC technology evolved from a chip-set
philosophy to an embedded-cores-based system-on-a-chip concept.
1. ASIC vendor design: This refers to the design in which all the
components in the chip are designed as well as fabricated by
an ASIC vendor.
2. Integrated design: This refers to the design by an ASIC vendor
in which all components are not designed by that vendor. It
implies the use of cores obtained from some other source
such as a core/IP vendor or a foundry.
3. Desktop design: This refers to the design by a fabless
company that uses cores which for the most part have been
obtained from other source such as IP companies, EDA
companies, design services companies, or a foundry.
SoC Design Challenges
Soft
core
Resusability
portability
flexibility
Firm
core
Hard
core
The design process is the set of design tasks that transform an abstract
specification model into an architectural model.
SoC Co-design Flow
Design Proces
A canonical or generic
form of an SoC design
Type of of specifications:
v Formal specifications – the desired characteristics of the design are
defined independently of any implementation.
v Executable specifications – are typically an abstract model for the
hardware and/or software being specified, and currently more useful for
describing functional behavior in most design situations.
The System Design
Process
Determining the optimal architecture
(cost and performance) involves a
set of complex decisions, such as:
• What goes in software and what
goes in hardware
• What processor(s) to use, and how
many
• What bus architecture is required
to achieve the required system
performance
• What memory architecture to use
to reach an appropriate balance
between power, area, and speed.
Fabrication
DVT Prep
DVT
6 12 12 4 14 ?? 5 8 Time in Weeks
Memory DSP
tested as a part of the system
I/O pads
I/O pads
array core
Therefore,
resource sharing
becomes an issue,
communication between
IPs becomes very
complicated.
Sonics’ SiliconBackplane Used in SOC Design Architecture
The CPU, DMA, and the DSP engine all share the same bus (the CPU or
the system bus). Also, there are dedicated data links, a lot of control wires
between blocks, and peripheral buses between subsystems
Þ there is interdependency between blocks and a lot of wires in the chip.
Therefore, verification, test, and physical design all become difficult to fulfill.
A solution to this system integration is to use an intelligent, on-chip
interconnect that unifies all the traffic into a single entity.
An example of this is Sonics’ SMART Interconnect SiliconBackplane
MicroNetwork.
The architecture
includes:
v IP creation – ASIPs,
interconnect and algorithm
Q&A
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