5.

2 Current–Voltage Characteristics 247

NMOS PMOS

S G D D G S
Gate
oxide Polysilicon
SiO2 Thick SiO2 (isolation) SiO2

n! n! p! p!

n well

p-type body

Figure 5.10 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a
separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is
used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to
the n well; the latter functions as the body terminal for the p-channel device.

5.2 Current–Voltage Characteristics

Building on the physical foundation established in the previous section for the operation of
the enhancement MOS transistor, in this section we present its complete current–voltage
characteristics. These characteristics can be measured at dc or at low frequencies and thus
are called static characteristics. The dynamic effects that limit the operation of the MOSFET
at high frequencies and high switching speeds will be discussed in Chapter 9.

5.2.1 Circuit Symbol

Figure 5.11(a) shows the circuit symbol for the n-channel enhancement-type MOSFET.
Observe that the spacing between the two vertical lines that represent the gate and the chan-
nel indicates the fact that the gate electrode is insulated from the body of the device. The
polarity of the p-type substrate (body) and the n channel is indicated by the arrowhead on the

D D D

G B G B G

S S S
(a) (b) (c)

Figure 5.11 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit sym-
bol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity
(i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when
the effect of the body on device operation is unimportant.
248 Chapter 5 MOS Field-Effect Transistors (MOSFETs)

line representing the body (B). This arrowhead also indicates the polarity of the transistor,
namely, that it is an n-channel device.
Although the MOSFET is a symmetrical device, it is often useful in circuit design to des-
ignate one terminal as the source and the other as the drain (without having to write S and D
beside the terminals). This objective is achieved in the modified circuit symbol shown in
Fig. 5.11(b). Here an arrowhead is placed on the source terminal, thus distinguishing it from
the drain terminal. The arrowhead points in the normal direction of current flow and thus
indicates the polarity of the device (i.e., n channel). Observe that in the modified symbol,
there is no need to show the arrowhead on the body line. Although the circuit symbol of
Fig. 5.11(b) clearly distinguishes the source from the drain, in practice it is the polarity of the
voltage impressed across the device that determines source and drain; the drain is always
positive relative to the source in an n-channel FET.
In applications where the source is connected to the body of the device, a further simplifica-
tion of the circuit symbol is possible, as indicated in Fig. 5.11(c). This symbol is also used in appli-
cations when the effect of the body on circuit operation is not important, as will be seen later.

5.2.2 The iD–vDS Characteristics

Table 5.1 provides a compilation of the conditions and the formulas for the operation of the
NMOS transistor in each of the three possible regions: the cutoff region, the triode region,
and the saturation region. The first two are useful if the MOSFET is to be utilized as a switch.
On the other hand, if the MOSFET is to be used to design an amplifier, it must be operated in
the saturation region. The rationale for these choices will be addressed in Section 5.4.
At the top of Table 5.1 we show a circuit consisting of an NMOS transistor and two dc
supplies providing v GS and v DS . This conceptual circuit can be used to measure the iD– v DS
characteristic curves of the NMOS transistor. Each curve is measured by setting v GS to a
desired constant value, varying v DS , and measuring the corresponding i D . Two of these char-
acteristic curves are shown in the accompanying diagram: one for v GS < V tn and the other for
v GS = V tn + v OV . (Note that we now use V tn to denote the threshold voltage of the NMOS
transistor, to distinguish it from that of the PMOS transistor, denoted V tp.)
As Table 5.1 shows, the boundary between the triode region and the saturation region is
determined by whether v DS is less or greater than the overdrive voltage v OV at which the
transistor is operating. An equivalent way to check for the region of operation is to examine
the relative values of the drain and gate voltages. To operate in the triode region, the gate volt-
age must exceed the drain voltage by at least V tn volts, which ensures that the channel remains
continuous (not pinched off). On the other hand, to operate in saturation, the channel must be
pinched off at the drain end; pinch-off is achieved here by keeping v D higher than v G – V tn ,
that is, not allowing v D to fall below v G by more than V tn volts. The graphical construction of
Fig. 5.12 should serve to remind the reader of these conditions.
A set of i D – v DS characteristics for the NMOS transistor is shown in Fig. 5.13. Observe
that each graph is obtained by setting v GS above V tn by a specific value of overdrive voltage,
denoted V OV1, V OV2, V OV3, and V OV4. This in turn is the value of v DS at which the corresponding
graph saturates, and the value of the resulting saturation current is directly determined by the
2 2
value of v OV, namely, -12 k′nV OV1, -12 k′nV OV2, . . . The reader is advised to commit to memory both
the structure of these graphs and the coordinates of the saturation points.
Finally, observe that the boundary between the triode and the saturation regions, that is,
the locus of the saturation points, is a parabolic curve described by
1 W 2
i D = --- k′n ⎛ -----⎞ v DS
2 ⎝ L⎠
 5.2 Current–Voltage Characteristics 249

Table 5.1 Regions of Operation of the Enhancement NMOS Transistor

iD
Triode Saturation
− + vDS < vOV vDS ≥ vOV
vGD iD
+ k ( ) v 2OV
1 " W
2 n L
+ vDS
vGS = Vtn + vOV
vGS
− − Cut-off
vGS < Vtn
Slope =
gDS = r1
DS 0
= kn" ( W v vOV vDS
L ) OV

v GS < V tn : no channel; transistor in cut-off; i D = 0

v GS = V tn + v OV : a channel is induced; transistor operates in the triode region or the saturation region depend-
ing on whether the channel is continuous or pinched-off at the drain end;

Triode Region Saturation Region

Continuous channel, obtained by: Pinched-off channel, obtained by:
v GD > V tn v GD # V tn
or equivalently: or equivalently:
v DS < v OV v DS $ v OV
Then, Then
i D = k n′ ⎛ -----⎞ ( v GS – V tn ) v DS – --- v DS i D = --- k n′ ⎛ -----⎞ ( v GS – V tn )
W 1 2 1 W 2
⎝ L⎠ 2 2 ⎝ L⎠

or equivalently, or equivalently,
i D = k n′ ⎛ -----⎞ ⎛ v OV – --- v DS⎞ v DS i D = --- k n′ ⎛ -----⎞ v OV
W 1 1 W 2
⎝ L⎠ ⎝ 2 ⎠ 2 ⎝ L⎠

Overdrive
voltage

VOV

Figure 5.12 The relative levels of the terminal voltages of the enhancement NMOS transistor for opera-
tion in the triode region and in the saturation region.
250 Chapter 5 MOS Field-Effect Transistors (MOSFETs)

iD vDS % vOV
Triode vDS ! vOV
region Saturation region
1
2
kn" ( WL ) VO2V4 vGS = V t + VOV4

vDS = vOV
2
iD = 12 kn ( WL ) vDS

1
2
kn" ( WL ) VO2V3 vGS = Vt + VOV3

1
2
kn" ( WL ) VO2V2 vGS = V t + VOV2

1
2
kn" ( WL ) VO2V1 vGS = V t + VOV1
0 VOV1 VOV2 VOV3 VOV4 vDS
vGS % Vt (Cutoff)
Figure 5.13 The iD– v DS characteristics for an enhancement-type NMOS transistor.

5.2.3 The iD– vGS Characteristic

When the MOSFET is used to design an amplifier, it is operated in the saturation region. As
Fig. 5.13 indicates, in saturation the drain current is constant determined by v GS (or v OV )
and is independent of v DS . That is, the MOSFET operates as a constant-current source
where the value of the current is determined by v GS . In effect, then, the MOSFET operates
as a voltage-controlled current source with the control relationship described by

1 W
i D = --- k′n ⎛ -----⎞ ( v GS – V tn )
2
(5.21)
2 ⎝ L⎠

or in terms of v OV ,
1 W 2
i D = --- k′n ⎛ ----- ⎞ v OV (5.22)
2 ⎝L ⎠

This is the relationship that underlies the application of the MOSFET as an amplifier. That it
is nonlinear should be of concern to those interested in designing linear amplifiers. Never-
theless, later in this chapter, we will see how one can obtain linear amplification from this
nonlinear control or transfer characteristic.
Figure 5.14 shows the iD– v GS characteristic of an NMOS transistor operating in satura-
tion. Note that if we are interested in a plot of i D versus v OV , we simply shift the origin to the
point v GS = V tn .
The view of the MOSFET in the saturation region as a voltage-controlled current source
is illustrated by the equivalent-circuit representation shown in Fig. 5.15. For reasons that will
become apparent shortly, the circuit in Fig. 5.15 is known as a large-signal equivalent cir-
cuit. Note that the current source is ideal, with an infinite output resistance representing the
independence, in saturation, of i D from v DS . This, of course, has been assumed in the
idealized model of device operation utilized thus far. We are about to rectify an important
shortcoming of this model. First, however, we present an example.
 5.2 Current–Voltage Characteristics 251

iD

vDS ! vGS – Vtn

0 Vtn vGS

0 vOV
Figure 5.14 The iD–vGS characteristic of an NMOS transistor operating in the saturation region. The iD–vOV
characteristic can be obtained by simply re-labelling the horizontal axis; that is, shifting the origin to the
point vGS = Vtn.

RD
'
Y
'
X k" tn
'
RG Z

tn
RS tn

&5 V Figure 5.15 Large-signal equivalent-circuit model

of an n-channel MOSFET operating in the saturation

Example 5.2

Consider an NMOS transistor fabricated in a 0.18-µm process with L = 0.18 µm and W = 2 µm. The pro-
cess technology is specified to have C ox = 8.6 fF/µm2, µn = 450 cm2/ V ⋅ s, and V tn = 0.5 V.
(a) Find V GS and V DS that result in the MOSFET operating at the edge of saturation with I D = 100 µA.
(b) If V GS is kept constant, find V DS that results in I D = 50 µA.
(c) To investigate the use of the MOSFET as a linear amplifier, let it be operating in saturation with
V DS = 0.3 V. Find the change in i D resulting from v GS changing from 0.7 V by +0.01 V and by – 0.01 V.
252 Chapter 5 MOS Field-Effect Transistors (MOSFETs)

Solution
First we determine the process transconductance parameter k′n

k′n = µ n C ox
–4 – 15 12
= 450 × 10 × 8.6 × 10 × 10 A/V2

= 387 µA/V2

and the transistor transconductance parameter k n ,

W
k n = k′n ⎛ -----⎞
⎝ L⎠
2
= 387 ⎛⎝ ----------⎞⎠ = 4.3 mA/V2
0.18
(a) With the transistor operating in saturation,
1 2
I D = --- k n V OV
2
Thus,
1 3 2
100 = --- × 4.3 × 10 × V OV
2
which results in
V OV = 0.22 V
Thus,
V GS = V tn + V OV = 0.5 + 0.22 = 0.72 V
and since operation is at the edge of saturation,

V DS = V OV = 0.22 V

(b) With V GS kept constant at 0.72 V and I D reduced from the value obtained at the edge of saturation,
the MOSFET will now be operating in the triode region, thus
1 2
I D = k n V OV V DS – --- V DS
2
3 1 2
50 = 4.3 × 10 0.22V DS – --- V DS
2
which can be rearranged to the form
2
V DS – 0.44V DS + 0.023 = 0

This quadratic equation has two solutions

V DS = 0.06 V and V DS = 0.39 V

The second answer is greater than V OV and thus is physically meaningless, since we know that the transis-
tor is operating in the triode region. Thus we have

V DS = 0.06 V
 5.2 Current–Voltage Characteristics 253

Example 5.2 continued

(c) For v GS = 0.7 V, V OV = 0.2 V, and since V DS = 0.3 V, the transistor is operating in saturation and
1 2
I D = --- k n V OV
2
1
= --- × 4300 × 0.04
2
= 86 µA

Now for v GS = 0.710 V, v OV = 0.21 V and

1 2
i D = --- × 4300 × 0.21 = 94.8 µA
2
and for v GS = 0.690 V, v OV = 0.19 V, and
1 2
i D = --- × 4300 × 0.19 = 77.6 µA
2
Thus, with ∆V GS = +0.01 V, ∆i D = 8.8 µA; and for ∆V GS = – 0.01 V, ∆i D = – 8.4 µA.
We conclude that the two changes are almost equal, an indication of almost-linear operation when the
changes in v GS are kept small. This is just a preview of the “small-signal operation” of the MOSFET stud-
ied in Sections 5.4 and 5.5.

EXERCISES

5.4 An NMOS transistor is operating at the edge of saturation with an overdrive voltage V OV and a drain
current I D . If V OV is doubled, and we must maintain operation at the edge of saturation, what should
V DS be changed to? What value of drain current results?
Ans. 2 V OV ; 4 I D
5.5 An n-channel MOSFET operating with V OV = 0.5 V exhibits a linear resistance r DS = 1 kΩ when
v DS is very small. What is the value of the device transconductance parameter kn? What is the value
of the current I D obtained when v DS is increased to 0.5 V? and to 1 V?
Ans. 2 mA/V2; 0.25 mA; 0.25 mA

5.2.4 Finite Output Resistance in Saturation

Equation (5.21) and the corresponding large-signal equivalent circuit in Fig. 5.15, as well as
the graphs in Fig. 5.13, indicate that in saturation, iD is independent of vDS. Thus, a change
∆vDS in the drain-to-source voltage causes a zero change in iD, which implies that the incre-
mental resistance looking into the drain of a saturated MOSFET is infinite. This, however,
is an idealization based on the premise that once the channel is pinched off at the drain end,
further increases in vDS have no effect on the channel’s shape. But, in practice, increasing vDS
beyond vOV does affect the channel somewhat. Specifically, as vDS is increased, the channel
pinch-off point is moved slightly away from the drain, toward the source. This is illustrated
in Fig. 5.16, from which we note that the voltage across the channel remains constant at vOV ,
and the additional voltage applied to the drain appears as a voltage drop across the narrow
depletion region between the end of the channel and the drain region. This voltage acceler-
ates the electrons that reach the drain end of the channel and sweeps them across the deple-
tion region into the drain. Note, however, that (with depletion-layer widening) the channel
254 Chapter 5 MOS Field-Effect Transistors (MOSFETs)

Source Channel Drain

& vOV ! & ! vDS & vOV

L & !L !L

Figure 5.16 Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the
drain, thus reducing the effective channel length (by ∆L).

length is in effect reduced, from L to L – ∆L , a phenomenon known as channel-length

modulation. Now, since iD is inversely proportional to the channel length (Eq. 5.21), iD
increases with vDS.
This effect can be accounted for in the expression for i D by including a factor
1 + λ ( v DS – v OV ) or, for simplicity, ( 1 + λ v DS ),
1 W
i D = --- k ′n ⎛ -----⎞ ( v GS – V tn ) ( 1 + λ v DS )
2
(5.23)
2 ⎝ L⎠
–1
Here λ is a device parameter having the units of reciprocal volts ( V ). The value of λ depends
both on the process technology used to fabricate the device and on the channel length L that the
circuit designer selects. Specifically, the value of λ is much larger for newer submicron technol-
ogies than for older technologies. This makes intuitive sense: Newer technologies have very
short channels, and are thus much greatly impacted by the channel-length modulation effect.
Also, for a given process technology, λ is inversely proportional to L.
A typical set of iD–vDS characteristics showing the effect of channel-length modulation is
displayed in Fig. 5.17. The observed linear dependence of iD on vDS in the saturation region is
represented in Eq. (5.23) by the factor (1 + λ vDS). From Fig. 5.17 we observe that when the
straight-line iD–vDS characteristics are extrapolated, they intercept the vDS axis at the point,
vDS = −VA, where VA is a positive voltage. Equation (5.23), however, indicates that iD = 0
at v DS = – 1 ⁄ λ . It follows that
1
V A = ---
λ
and thus VA is a device parameter with the dimensions of V. For a given process, VA is pro-
portional to the channel length L that the designer selects for a MOSFET. We can isolate the
dependence of VA on L by expressing it as

V A = V A′ L
where V A′ is entirely process-technology dependent with the dimensions of volts per micron.
Typically, V A′ falls in the range of 5 V/µm to 50 V/µm. The voltage VA is usually referred to as the
Early voltage, after J. M. Early, who discovered a similar phenomenon for the BJT (Chapter 6).
Equation (5.23) indicates that when channel-length modulation is taken into account,
the saturation values of iD depend on vDS. Thus, for a given vGS, a change ∆ vDS yields a
corresponding change ∆iD in the drain current iD. It follows that the output resistance of the current
source representing iD in saturation is no longer infinite. Defining the output resistance ro as7

7
In this book we use ro to denote the output resistance in saturation, and rDS to denote the drain-to-source
resistance in the triode region, for small vDS.
 5.2 Current–Voltage Characteristics 255

iD

Triode Saturation

VOV
1
Slope (
ro

&VA ( &1/ ) 0 vDS

Figure 5.17 Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the pro-
cess technology and, for a given process, is proportional to the channel length L.

!
vGS " tn

&

Figure 5.18 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating
the output resistance ro. The output resistance models the linear dependence of iD on vDS and is given by
Eq. (5.23).
∂ iD –1
r o ≡ ----------
- (5.24)
∂ v DS v GS constant

and using Eq. (5.23) results in

k n′ W –1
- ----- ( V – V tn ) 2
r o = λ ----- (5.25)
2 L GS
which can be written as
1
r o = -------- (5.26)
λ ID
or, equivalently,
V
r o = -----A- (5.27)
ID
where ID is the drain current without channel-length modulation taken into account; that is,
1 W 2
I D = --- k n′ ------ ( V GS – V tn ) (5.27′)
2 L
256 Chapter 5 MOS Field-Effect Transistors (MOSFETs)

Thus the output resistance is inversely proportional to the drain current. Finally, we
show in Fig. 5.18 the large-signal, equivalent-circuit model incorporating ro.

EXERCISE

5.6 An NMOS transistor is fabricated in a 0.4-µm process having µnCox = 200 µA/V2 and V′A = 50 V/µm
of channel length. If L = 0.8 µm and W = 16 µm, find VA and λ. Find the value of ID that results when
the device is operated with an overdrive voltage VOV = 0.5 V and VDS = 1 V. Also, find the value of ro
at this operating point. If VDS is increased by 2 V, what is the corresponding change in ID?
Ans. 40 V; 0.025 V−1; 0.51 mA; 80 kΩ; 0.025 mA

5.2.5 Characteristics of the p-Channel MOSFET

The circuit symbol for the p-channel enhancement-type MOSFET is shown in Fig. 5.19(a).
Figure 5.19(b) shows a modified circuit symbol in which an arrowhead pointing in the nor-
mal direction of current flow is included on the source terminal. For the case where the
source is connected to the substrate, the simplified symbol of Fig. 5.19(c) is usually used.

S S

G B G B

D D
(c)
(a) (b)

Figure 5.19 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol with
an arrowhead on the source lead. (c) Simplified circuit symbol for the case where the source is connected
to the body.
The regions of operation of the PMOS transistor and the corresponding conditions
and expression for i D are shown in Table 5.2. Observe that the equations are written in a
way that emphasizes physical intuition and avoids the confusion of negative signs. Thus
while V tp is by convention negative, we use V tp , and the voltages v SG and v SD are posi-
tive. Also, in all of our circuit diagrams we will always draw p-channel devices with their
sources on top so that current flows from top to bottom. Finally, we note that PMOS
devices also suffer from the channel-length modulation effect. This can be taken into
account by including a factor ( 1 + λ v SD ) in the saturation-region expression for i D as
follows
1 W
i D = --- k p′ ⎛ -----⎞ ( v SG – V tp ) ( 1 + λ v SD )
2
(5.28)
2 ⎝ L⎠
 257

or equivalently
1 W v SD ⎞
i D = --- k p′ ⎛ -----⎞ ( v SG – V tp ) ⎛⎝ 1 + --------
2
- (5.29)
2 ⎝ L⎠ VA ⎠

where λ and V A (the Early voltage for the PMOS transistor) are by convention negative
quantities, hence we use λ and V A .
Finally, we should note that for a given CMOS fabrication process λ n and λ p are gener-
ally not equal, and similarly for V An and V Ap .
To recap, to turn a PMOS transistor on, the gate voltage has to be made lower than that
of the source by at least V tp . To operate in the triode region, the drain voltage has to exceed
that of the gate by at least V tp ; otherwise, the PMOS operates in saturation. Finally, Fig. 5.20
provides a pictorial representation of these operating conditions.

Table 5.2 Regions of Operation of the Enhancement PMOS Transistor

+ iD Triode Saturation
+ vSD < |vOV| vSD ≥ |vOV|
vSG
− vSD ( ) v 2OV
1 " W
k
2 p L
−
vDG iD vSG = |Vtp| + |vOV|
−
+ Cut-off
vSG < |Vtp|
Slope =
gDS = r1 0
DS |v OV| v SD
= k p" ( W |v |
L ) OV

v SG < V tp : no channel; transistor in cut-off; i D = 0

v SG = V tp + v OV : a channel is induced; transistor operates in the triode region or in the saturation region
depending on whether the channel is continuous or pinched-off at the drain end;

Triode Region Saturation Region

Continuous channel, obtained by: Pinched-off channel, obtained by:
v DG > V tp v DG # V tp
or equivalently: or equivalently
v SD < v OV v SD $ v OV
Then, Then

i D = k p′ ⎛ -----⎞ ( v SG – V tp ) v SD – --- v SD i D = --- k p′ ⎛⎝ -----⎞⎠ ( v SG – V tp )

W 1 2 1 W 2
⎝ L⎠ 2 2 L

or equivalently or equivalently

= k p′ ⎛ -----⎞ ⎛ v OV – --- v SD⎞ v SD i D = --- k p′ ⎛ -----⎞ v 2OV

W 1 1 W
iD
⎝ L⎠ ⎝ 2 ⎠ 2 ⎝ L⎠
258 Chapter 5 MOS Field-Effect Transistors (MOSFETs)

Voltage
S
Vtp
Threshold Triode VOV
D
Vtp
G
Figure 5.20 The relative levels of the terminal
Overdrive Saturation
voltages of the enhancement-type PMOS transis-
voltage tor for operation in the triode region and in the
saturation region.

EXERCISE

2
5.7 The PMOS transistor shown in Fig. E5.7 has V tp = – 1 V, k′p = 60 µA/ V , and W ⁄ L = 10.
(a) Find the range of VG for which the transistor conducts.
(b) In terms of VG, find the range of VD for which the transistor operates in the triode region.
(c) In terms of VG, find the range of VD for which the transistor operates in saturation.
(d) Neglecting channel-length modulation (i.e., assuming λ = 0), find the values of VOV and VG
and the corresponding range of VD to operate the transistor in the saturation mode with ID = 75 µA.
(e) If λ = −0.02 V−1, find the value of ro corresponding to the overdrive voltage determined in (d).
(f) For λ = −0.02 V−1 and for the value of VOV determined in (d), find ID at VD = +3 V and at VD = 0 V;
hence, calculate the value of the apparent output resistance in saturation. Compare to the value found
in (e).

!5 V

VG

ID

VD Figure E5.7

Ans. (a) V G ≤ +4 V; (b) V D ≥ V G + 1; (c) V D ≤ V G + 1; (d) 0.5 V, 3.5 V, ≤ 4.5 V; (e) 0.67 MΩ;
(f) 78 µA, 82.5 µA, 0.67 MΩ (same)

5.3 MOSFET Circuits at DC

Having studied the current–voltage characteristics of MOSFETs, we now consider circuits
in which only dc voltages and currents are of concern. Specifically, we shall present a series
of design and analysis examples of MOSFET circuits at dc. The objective is to instill in the
reader a familiarity with the device and the ability to perform MOSFET circuit analysis both
rapidly and effectively.
In the following examples, to keep matters simple and thus focus attention on the essence
of MOSFET circuit operation, we will generally neglect channel-length modulation; that is,
we will assume λ = 0. We will find it convenient to work in terms of the overdrive voltage;
VOV = VGS − Vtn for NMOS and V OV = V SG – V tp for PMOS.