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Assignment 10

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19 views4 pages

Assignment 10

Uploaded by

floydmustang1
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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FACULTY OF ENGINEERING AND THE BUILT ENVIROMENT DEPARTMENT OF

ELECTRICAL ENGINEERING TECHNOLOGY

Surname and initials: Madiope, T

Student number: 221158199

Module name: Digital Systems 2B

Module code: DIGELB2

Assignment 10: . Counter using VHDL

Lecturer: Dr. Johan Venter


Table of Contents
Description of practical .............................................................................................................. 2

Software code............................................................................................................................. 2

Stimulus ..................................................................................................................................... 3

Discussion of code ..................................................................................................................... 3

Table of Figures
Figure 1: Counter Stimulus ........................................................................................................ 3

1
Description of practical
Design and implement a counter.

The counter is programmed to a pushbutton which counts the number of times the button had
been pushed. When the pushbutton is held, the counter must not increment the number of
counts. It should only increment when the pushbutton is released and pushed in again.

There must be three separate counters implemented. Three different dipswitches must select
the specific counter and the FPGA must remember each count. A separate switch must be used
to reset the counter. Only one reset switch may be used for all three counters.

Software code
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Counter is
port(clk : in std_logic;
rst : in std_logic;
btn, btn1, btn2 : in std_logic;
cnt, cnt1, cnt2 : out std_logic_vector (7 downto 0)
);
end Counter;

architecture beh of Counter is


signal button_state : std_logic := '0';
signal button_state1 : std_logic := '0';
signal button_state2 : std_logic := '0';
signal cnter : std_logic_vector (7 downto 0) := "00000000";
signal cnter1 : std_logic_vector (7 downto 0) := "00000000";
signal cnter2 : std_logic_vector (7 downto 0) := "00000000";

begin
process(clk)
begin
if rising_edge(clk) then
if btn = '1' then
if button_state = '0' then
button_state <= '1';
cnter <= cnter + 1;
end if;
else
button_state <= '0';
end if;
if btn1 = '1' then
if button_state1 = '0' then
button_state1 <= '1';

2
cnter1 <= cnter1 + 1;
end if;

if button_state2 = '0' then


button_state2 <= '1';
cnter2 <= cnter2 + 1;
end if;
else
button_state2 <= '0';
end if;
if rst = '1' then
cnter <= "00000000";
cnter1 <= "00000000";
cnter2 <= "00000000";
end if;
end if;
end process;
cnt <= cnter;
cnt1 <= cnter1;
cnt2 <= cnter2;
end beh;

Stimulus

Figure 1: Counter Stimulus

Discussion of code
As the pushbutton/dipswitch is “ON” the count will increment. The count increments by one
only once the button/switch is pushed down then being let go of. So, when the button is held
down, the count does not continuously increase, instead it stays at the number it was on when
it was pushed down. When the reset switch is on, it resets all the counts to zero. When holding
down the reset switch and one of the counts is pressed, the number of buttons pushed would
still be zero.

The clock is necessary to keep the inputs in check. When the clock goes high, it checks if the
buttons’ state is either low or high.

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