King Khalid University

College of Computer Science

Digital Logic Design

Lab Manual
CPE-122

Instructor
Saleh M Alghamdi
2024 - 1445
Contents

1 SR Latch Tutorial - Understanding and Implementation 2

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 What is an SR Latch? . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Working Principles of an SR Latch . . . . . . . . . . . . . . . 2
1.4 Implementing an SR Latch . . . . . . . . . . . . . . . . . . . . 4
1.4.1 NOR Gate Implementation . . . . . . . . . . . . . . . 4
1.4.2 NAND Gate Implementation . . . . . . . . . . . . . . . 5
1.5 Applications of SR Latch . . . . . . . . . . . . . . . . . . . . . 7
1.6 The indeterminate state . . . . . . . . . . . . . . . . . . . . . 7
1.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 SR Latch Tutorial - Understanding and Implementation 9

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 What is an SR Latch? . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Working Principles of an SR Latch . . . . . . . . . . . . . . . 9
2.4 Implementing an SR Latch . . . . . . . . . . . . . . . . . . . . 11
2.4.1 NOR Gate Implementation . . . . . . . . . . . . . . . 11
2.4.2 NAND Gate Implementation . . . . . . . . . . . . . . . 12
2.5 Applications of SR Latch . . . . . . . . . . . . . . . . . . . . . 14
2.6 The indeterminate state . . . . . . . . . . . . . . . . . . . . . 14
2.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Appendix 16
3.1 Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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Experiment 1

SR Latch Tutorial - Understanding

and Implementation

1.1 Introduction
The SR latch, also known as the Set-Reset latch, is a fundamental component
in digital electronics. It is a simple bistable circuit that can store one bit of
information. In this lab tutorial, we will delve into the working principles of
an SR latch and learn how to implement it using basic logic gates.

1.2 What is an SR Latch?

An SR latch is a basic memory element that can hold a single bit of information.
It has two inputs: the Set (S) input and the Reset (R) input. The outputs of
the SR latch are the Q (output) and the Q’ (complement of the output).

1.3 Working Principles of an SR Latch

The SR latch operates based on feedback and cross-coupling of two NOR or
NAND gates. It can be built using either NOR or NAND gates. The state of
the latch depends on the input values and the previous state.
In an SR latch, when the Set input (S) is activated, the output (Q) sets to
logic high (1). Conversely, when the Reset input (R) is activated, the output
(Q) resets to logic low (0). The state of the latch remains unchanged if both
inputs are deactivated (S = R = 0).
The SR latch operates based on the concept of feedback and cross-coupling
between its internal gates. It can be implemented using either NOR gates or

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NAND gates, but for the purpose of this explanation, we will focus on the
NOR gate implementation.
In an SR latch, there are two NOR gates connected in a cross-coupled
configuration. One NOR gate’s output is connected to one of the inputs of
the other NOR gate, and vice versa. This forms a positive feedback loop,
which is crucial for the latch’s behavior.
Let’s examine the latch’s behavior in different scenarios:

Set (S) Input Activation:

When the Set (S) input is activated (S = 1), it drives one input of the first
NOR gate to logic low (0). As a result, the output of the first NOR gate goes
to logic high (1). This high output value is then fed back to the second NOR
gate’s input.
The positive feedback comes into play here. The high output of the first
NOR gate forces its input at the second NOR gate to logic low (0). As a
result, the output of the second NOR gate remains logic high (1). This high
output value is then fed back to the first NOR gate’s input, reinforcing the
latch’s state.
Therefore, when the Set input is activated, the latch is "set" or "latched"
in the state where the output (Q) is logic high (1).

Reset (R) Input Activation:

When the Reset (R) input is activated (R = 1), it drives one input of the
second NOR gate to logic low (0). Consequently, the output of the second
NOR gate goes to logic high (1). This high output value is then fed back to
the first NOR gate’s input.
Again, the positive feedback loop comes into play. The high output of the
second NOR gate forces its input at the first NOR gate to logic low (0). As
a result, the output of the first NOR gate remains logic high (1). This high
output value is then fed back to the second NOR gate’s input, reinforcing the
latch’s state.
Therefore, when the Reset input is activated, the latch is "reset" or
"latched" in the state where the output (Q) is logic low (0).

No Input Activation:
When neither the Set (S) nor the Reset (R) inputs are activated (S = R = 0),
no changes occur in the latch’s state. The outputs of the NOR gates remain
in their previous states, maintaining the latch’s stability.

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 It’s essential to note that the indeterminate state (S = R = 1) is to be
avoided, as mentioned earlier. In this state, both outputs of the NOR gates
become logic low (0), which creates a feedback loop that can cause oscillation
and unpredictable behavior.

Truth Table of an SR Latch:

The following truth table summarizes the behavior of an SR latch:

S R Q Q′
0 0 Q Q′
0 1 0 1
1 0 1 0
1 1 X X

Note: The "X" represents an indeterminate state, which should be avoided

in practice.

1.4 Implementing an SR Latch

There are two common ways to implement an SR latch: using NOR gates or
NAND gates. Here, we will explain both implementations.

1.4.1 NOR Gate Implementation

The NOR gate implementation of an SR latch requires two NOR gates. Follow
the steps below to implement it:
Step 1: Connect the output of one NOR gate to one of the inputs of the other
NOR gate.

Step 2: Connect the Set (S) input to one of the inputs of the first NOR gate.

Step 3: Connect the Reset (R) input to one of the inputs of the second NOR
gate.

Step 4: Connect the output of the second NOR gate to the other input of the
first NOR gate.

Step 5: The output of the first NOR gate is the Q output, and the output of
the second NOR gate is the Q’ output.

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 Figure 1.1: SR Latch using NOR Gates

LAB TASK 1
• Simulate the SR latch using the NOR gate in the Electronic Workbench
Simulation software. (See Appendix A).

• Implement the SR latch using the NOR gate. Use IC 7402 and the KL
300 Digital Logic trainer. (Follow the steps in Appendix A).

• Reflect your findings including the truth table and any other observations
on your lab report.

1.4.2 NAND Gate Implementation

The NAND gate implementation of an SR latch also requires two NAND
gates. Follow the steps below to implement it:

• Step 1: Connect the output of one NAND gate to one of the inputs of
the other NAND gate.

• Step 2: Connect the Set (S) input to one of the inputs of the second
NAND gate.

• Step 3: Connect the Reset (R) input to one of the inputs of the first
NAND gate.

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 • Step 4: Connect the output of the first NAND gate to the other input
of the second NAND gate.

• Step 5: The output of the second NAND gate is the Q output, and the
output of the first NAND gate is the Q’ output.

Figure 1.2: SR Latch using NAND Gates

LAB TASK 2
• Simulate the SR latch using the NAND gate in the Electronic Workbench
Simulation software. (See Appendix A).

• Implement the SR latch using the NAND gate. Use IC 7400 and the
KL 300 Digital Logic trainer. (Follow the steps in Appendix A).

• Reflect your findings including the truth table and any other observations
on your lab report.

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1.5 Applications of SR Latch
SR latches are widely used in digital systems and have various applications,
including:

• Memory elements in computer systems and registers.

• Control circuits and flip-flops.

• Sequential logic circuits.

• Synchronization and signal detection circuits

1.6 The indeterminate state

The indeterminate state, represented by "X" in the truth table of an SR
latch, occurs when both the Set (S) and Reset (R) inputs are activated
simultaneously (S = R = 1). This state is also known as the forbidden or
invalid state.
When both inputs are active, the outputs of the SR latch become unpre-
dictable. The latch can oscillate between its two stable states, leading to
undefined behavior. This can cause issues in digital circuits, as it introduces
uncertainty and can disrupt the overall system’s functionality.
The indeterminate state should be avoided in practice because it can lead
to data instability and inconsistent output values. In most applications, it
is crucial to ensure that the inputs of an SR latch are not both activated
simultaneously.
To prevent the indeterminate state, the following measures can be taken:

LAB TASK 3
• Examine the indeterminate state and write down your observations in
your Lab report.

1.7 Summary
In this lab tutorial, we explored the SR latch, a fundamental circuit in digital
electronics. We discussed its working principles, truth table, and two common
implementations using NOR and NAND gates. We also examined the timing
diagram and highlighted some applications of SR latches. Understanding the
SR latch is crucial for building more complex digital circuits and systems.

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Remember to exercise caution when working with digital circuits, and always
follow proper circuit design and safety guidelines.I hope this tutorial on the
SR latch was helpful! If you have any further questions, feel free to ask.

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Experiment 3

Appendix

3.1 Figure

Figure 3.1: Caption

Figure 3.2: Caption

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Stage 1:
• Connect Pin 1 to the LED.
• Connect Pin 4 to the LED.

Figure 3.3: Caption

Stage 2:
• Connect Switch 1 (Set) to Pin 2
• Connect Switch 2 (Reset) to Pin 5

Figure 3.4: Caption

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Stage 3:
• Connect Pin 14 to the VCC.
• Connect pin 7 to the GND.

Figure 3.5: Caption

Stage 4:
• Connect pin 6 to 1
• Connect pin 3 to 4

Figure 3.6: Caption

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