Lab Series Introduction

To those familiar with conventional Nyquist-rate analogue-to-digital converter (ADC) and

digital-to-analogue converter (DAC) design, Delta-Sigma modulation (DSM) can appear a
somewhat inscrutable data conversion technique when first encountered. It is our
experience that a quick way for beginners to really get a feel for how DS modulators work
and how the relevant theory applies in practice is by hands-on experimenting with real
modulators as they learn. This is the purpose of this course’s laboratories; to use hands-on
experimenting to hopefully make the points covered of the lecture materials clearer and
more meaningful by letting you see them in action. The first 5 laboratories focus on
system-level simulation of some simple modulators to help students make the important
leaps from encountering new theory in the lectures to actually understanding the
significance of these lecture materials in practice. The next 5 laboratories look at high-level
circuit design of discrete-time analogue modulators implemented as switched-capacitor
circuits. Ideally, by the end of the lectures and laboratories course you should feel able to
confidently design real DSMs.

This first laboratory introduces Matlab and Simulink as very useful tools for system-level
modelling and predicting the performance of DSMs. These two tools are widely-available
and widely-used in industry and academia for system modelling and simulation.

System-level modelling and simulation play critical roles in the early stages of a Delta
Sigma modulator design, be it a DSM-based ADC, DAC or even a purely digital design,
such as a divider in a fractional-N PLL.

A first task when designing any new, complex system is often to build one or more
mathematical models of the system which can be used to predict and explore the system
behaviour, optimize aspects of its behaviour and/or compare competing designs. Only
once a satisfactory system-level design is achieved are detailed implementation issues
considered – this is the “Top-Down” design approach. For linear systems, exact
mathematical analysis to aid their design is often possible; predicting system stability and
noise being commonly-encountered and well-established examples.

Unfortunately, DSMs contain a quantiser and are thus nonlinear feedback systems. As is
common for nonlinear systems, exact mathematical analysis of DSMs is often very difficult
or even impossible, and to date there is no complete theoretical analysis for arbitrary
DSMs that can be used to accurately and unquestionably predict if a proposed modulator
design will fully meet its performance targets, and do so with no undesirable side-effects.

Nevertheless, some useful analytical results have been achieved which can be used to
guide a design of a DSM, and you will encounter some of these is the course lectures:

• In a few specific cases exact mathematical analysis may be possible.

• By making simplifying assumptions some general mathematical analyses become
possible, but violating these assumptions can result in the real modulator behaving very
differently than predicted (such as having a much reduced stable input signal range or
even total loop instability).
• Additionally, some analyses yield only upper or lower performance bounds, beyond
which it may be possible to push some designs to achieve higher performance without
disastrous results. In this sense they are more like warning guidelines when constructing a
new design rather than giving absolute design limits.
• Finally, some commonly-used results are just accepted rules-of-thumb based more
on extensive experience than theoretical consideration!

The consequence of the various approximations and limitations invoked either to get
mathematically tractable results or simply because experience suggests they are good
rules-of-thumb, is that extensive system-level simulation is essential to check whether a
given modulator will indeed perform to specification when designed using existing theory -
and without unwelcome surprises such as modulator instability under certain conditions.

It should be noted that even when designing and simulating at the system level, DSM
models commonly include (usually simplified) models of some real circuit implementation
effects which can have a strong influence on the behaviour of the modulator. For any
modulator these can include:

• Finite signal-swing headroom effects such as soft saturation and hard clipping;
saturating integrators or quantisers can badly degrade overall modulator performance, and
even cause irrecoverable modulator loop oscillation in some high-order modulators.

Additionally, for an analogue modulator loop (i.e. a DSM-based ADC) these may further
include:

• Finite gain and bandwidth of the circuits used to realize the integrators.
• Nonlinearity of the modulator circuits.
• Effects of systematic or random (“mismatch”) component deviations; consequences
of these include signal path gain errors (some modulators are very sensitive to this) and
highly-troublesome nonlinearity in the feedback DAC path of modulators with multi-bit
quantisers (the topic of lab 4).

The reason why such effects are often included - even if only in approximate form - at the
system-level simulation stage is that circuit-level simulation is not an effective tool for
investigating their effects. System-level simulations usually run at least thousands of times
faster than circuit-level simulation using tools such as HSPICE™ or Spectre™
(seconds/minutes versus hours/days). Given that many hundreds or thousands of
simulations may be required to convince a designer that their DSM design will behave as
expected for likely inputs (no SQNR degradation, oscillations, signal distortion, in-band
spurious tones etc.), it is unreasonable in terms of simulation time requirements to use
only circuit simulators for examining the consequences of real circuit effects. Including
approximations of circuit effects in the system-level model can however allow their likely
effects to be studied under a wide range of modulator operating conditions and hence
hugely increases the likelihood that any problems they cause will be found, and found
early in the design process.

Please maintain a good laboratory notebook as you work through the lab exercises
for this course. You will be asked to note and comment on various aspects of
modulator behaviour and will be asked often to refer back to previous results -
sometimes those obtained during a prior lab session - when comparing different
modulators. Your laboratory notebook will not be assessed, but failure to keep good
notes will make your laboratory work unnecessarily difficult by requiring you to re-
run previous exercises when comparing results.
 Sigma-Delta Data Converters
Laboratory Session 1
1.0 Objectives

In this laboratory, you will examine the properties of the first order sigma-delta modulator
(called “MOD1” using the terminology of the course text [1]) using Matlab and Simulink:

 You will be able to observe the time domain waveforms of the modulators in
response to both DC and sine wave inputs.
 You will observe noise shaping in the frequency domain via Fast Fourier
Transforms (FFTs), thereby confirming first-hand a fundamental operating principle
of DSMs, and see how noise shaping can result in high resolution conversion in
oversampled systems.
 A number of effects will be studied such as idle tones, dead zones and saturation.
You will observe the effects of dither and finite gain on the MOD1 modulator
characteristics.

The material in this laboratory is intended to aid students in understanding the material in
chapter 1 and 2 of [1].

1.1 Setup

You are strongly advised to consult the course textbook [1] while you are following the
laboratory; “Understanding Delta Sigma Modulators” by R. Shreier and G. Temes, which is
available online at:
http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5264508.

Login to Learn on http://myed.ed.ac.uk and download the file “SDsimulink.tar.gz” from the
folder “Latest Database” into your home directory.

Unzip this file by typing “gunzip SDsimulink.tar.gz”.

Untar the resulting file by typing “tar xvf SDsimulink.tar”.

You will see a new directory “EdUni”. Change directory into this location by typing “cd
EdUni”.

In this directory there are general utility routines:

sweep_testbench.mdl

In the directory “LAB1” there are a number of Simulink files that will be used in this
exercise:

dc_to_mod1.mdl
mod1.mdl
mod1_delint.mdl
quantiser1.mdl
quantiser2.mdl
quantiser3.mdl
sin_to_mod1.mdl
As well as a second directory “ELEE11080_ROUTINES” containing the following Matlab
command files:

baseband_power.m
baseband_sqnr.m
calc_quant_gain.m
init_vars.m
init_vars3.m
integ_stats.m
Qout_SNDR.m
Qout_SNDR_ac.m
sweep_dc_bbpwr.m
sweep_dc_dc.m
sweep_sin_ampl_sqnr.m

In the top-level directory “EdUni”, start Matlab by typing “matlab” in the shell window.

In Matlab, right click on the directory name “ELEE11080_ROUTINES” in the Current

Folder pane on the left. Select the option “Add to Path > Selected Folders and
SubFolders”. Do the same for the directory “LAB1”.

Type “init_vars” into the Matlab Command Window. This routine sets the default values for
common variables used in the various forthcoming exercises.

You are now ready to begin the lab.

1.2 MOD1: A First Order Modulator Simulink Model

The first modulator we will study is the very simplest DSM, a first order modulator loop with
single bit quantisation. The convention for this course will be to refer to a modulator with
loop order N as a type “MODN” modulator; the modulator we are about to study is thus
“MOD1”.

Right click on “dc_to_mod1.mdl” in “LAB1” and select “Open F4”. You should now see the
modulator schematic shown in Figure 1.
Fig. 1 dc_to_mod1.mdl schematic

This consists of the following main elements:

1. A non-delaying discrete-time integrator composed of a 1/z unit delay element in

feedback to an adder. A gain block precedes the delay element, and can represent
any finite integrator gain at dc, e.g. caused by the finite gain of an amplifier used to
implement a real analogue integrator, using the parameter modctrl.igain1 (the
default is +Inf, giving an ideal integrator with infinite gain at dc). A saturation block
represents the clipping effect of, e.g., finite power supply voltages or digital word
lengths in real modulators. The saturation range is set to +/-modctrl.isat1 and the
default range is +/-Inf which does not clip the signal. The integrator is the core
block responsible for noise shaping in the modulator.

2. A single-bit midrise quantiser. A quantiser element with step size of two has been
employed. This quantiser has output states +1 and -1 as show in Figure 2.

Digital output code, D

+1

0
D=
{ -1
+1
if A >= 0
if A < 0
Analogue input, A

-1

Fig. 2 The 1-bit quantiser transfer function

As this quantiser has only 2 output states, which can be encoded using a single
binary digit, it is often called a single bit, or 1-bit, quantiser. Here we use “-1” and
“+1” instead of the usual “0” and “1” as our binary codes simply so that the output is
then centred on zero.
 Notes: The default Matlab quantiser is midtread type with a step size of 2, so to
implement Figure 2 the input signal is shifted up by +1 before the quantiser and
down by -1 after to implement midrise behaviour. Consult [1] pages 21-24 if you are
unsure what these terms mean. Note too that the Matlab quantiser has infinite input
and output range and will give output codes “-5”, “+3”, “+101” etc. for suitably large
analogue inputs; the saturation block is needed to limit the output range to the
desired “-1” to “+1”.

3. A delaying feedback loop from the quantiser output to the input, where the two
signals are subtracted and the error signal LOOPERR is applied to the integrator.
The delay in the feedback represents the time to quantise, sample and feed back
the integrator output – usually a single clock cycle.

Note that for an analogue modulator the feedback path requires a DAC because the
quantiser output is a digital code but the modulator input is analogue. Here the
quantiser outputs -1 and +1 map directly to the desired analogue feedback levels -1
and +1 so no D/A conversion is needed at the system modelling level. Had we used
a quantiser with output codes “0” and “1” then a conversion to “-1” and “+1”
analogue levels respectively would be needed in the feedback path to support an
analogue input signal range -1 to +1.

4. A filter at the output of the modulator, the output of which recovers the low
frequency average of modulator digital output stream. A real analogue-input
modulator (ADC) is followed by a digital filter (with decimation to reduce the sample
rate) to remove out-of-band signals and create the digital output (a digital-input
modulator (DAC) is followed by an analogue post-filter to create the analogue
output). Here we use an analogue filter simply for simulation simplicity.

In addition to the main functional elements in the modulator there are a number of input
and output blocks:
1. A dc input parameterised by the variable “input_dc”,
2. A dither source input, generating white noise between +1 and -1. This is scaled by a
gain block (modctrl.dgain1) and summed at the input of the quantiser.
3. A time scope which allows various internal signals in the modulator loop to be
visualized.
4. A spectrum scope performing an FFT of the modulator output.

Notes:

The default sampling frequency, Fs, is chosen as 1 MHz. The default oversampling ratio,
OSR, is 64. The signal band of interest extends to Fs/(2.OSR), and is thus from 0 Hz
to 7812.5 Hz. All other frequencies are “out-of-band” and would be removed by the
decimation filter following the modulator.

1.3 Time Domain Operation for DC Input

We will now examine how the first order modulator sigma-delta ADC behaves with the
simplest possible input, a DC input level. You may wish to consult section 2.6 of the
course text during this exercise.
Set the DC input level to 0 by typing “input_dc = 0” into the Matlab command window or by
right clicking on the input_dc entry in the workspace pane.

Run the simulation by selecting “Simulation > Start” or pressing <ctrl>T in the Simulink
window.

You will see an FFT of the modulator output appear in a “Spectrum Scope” window. This
shows the output spectrum for frequencies from dc to Fs/2.

Right-click the FFT plot area and select autoscale to see the entire trace.

Double click on the time scope to observe the waveforms at the nodes in the modulator.
You may wish to autoscale the waveforms (the binoculars icon will scale them all).

Click on the magnifying glass icon with “Zoom X-axis” in to let you zoom into a few cycles
of the LOOPERR, INT1OUT and QUANTOUT waveforms.

Note any periodicity in the modulator behaviour and any strong frequency tones in the
FFT.

Repeat this for the following values of input_dc: 0.5, 0.75, 0.875, and 0.9375.

1. Observe and explain the time scope waveforms and the FFT tone frequencies and
amplitudes for each dc value. Can you predict the tone frequencies for a given
input_dc?
2. Note in each case, the lowpass filter output QUANTLPF and compare its settled
value to the input_dc setting (The Y magnifying glass may help here). Is the
modulator a good dc ADC; that is, does the filtered output dc level accurately
represent the analogue dc input (once any initial settling transient has passed)?
3. Is the output spectrum first-order noise-shaped? If not then why not?

Now, set input_dc to “–pi/10” and re-run the simulation. Repeat for input_dc set to
+0.4367.

1. Observe and comment on the shape of the FFT plots. Is there noise shaping
evident? Are there strong tones? Why do you get the results you do? What is so
different about the dc input –/10 and the previous inputs ½, ¾. etc.?

Set input_dc to +0.98 and re-run the simulation.

1. Observe and explain the time scope waveforms and FFT frequencies.

Set input_dc to +1.02 and re-run the simulation.

1. Observe and explain the time scope waveforms, in particular the integrator output.
What sort of input signal sizes can this modulator handle? Why?

1.4 Tonal Behaviour for Swept DC Input

The previous exercise highlighted the highly tonal behaviour of basic MOD1 for rational dc
inputs and the simple relationship between the input level and resulting tone frequencies.
We will now study the signal-band tonal behaviour of MOD1 across a swept range of input
dc levels. By signal-band we mean here only that energy in the output spectrum which lies
between dc and Fs/(2.OSR); remember that a modulator is an oversampled converter and
only a portion of its output spectrum (as defined by the OSR) is of interest. Any “out-of-
band” noise and/or tones outside the signal-band will be removed by a post-filter. You
may wish to consult section 2.6 of the [1] during this exercise, particularly noting the
discussion of figure 2.22.

Close “dc_to_mod1.mdl”.

Type target_modulator=‘mod1’ into the Matlab Command Window.

Run the routine “sweep_dc_bbpwr”.

The sweep_testbench.mdl Simulink model window will appear (and may or may not then
close automatically – Matlab seems quite unpredictable in this regard as new software
versions are released!) and the simulation will start.

Warning: The simulation analyses the signal-band noise power for 1000 dc levels may
take over five minutes to complete!

A plot of total baseband noise power in dBW will be generated for input amplitudes from 0
to 1, the maximum allowed input.

1. Observe the noise power at the dc levels studied in section 1.3.

2. Note which input levels have high tonal noise power and explain this. Why is the
signal-band power small for simple rational inputs such as 0, 1/2, 1/3, 1 etc. (note
the notches in the noise features at these levels). Compare the plot to that in Fig.
2.22 (OSR=64) of [1] and note the comments at the foot of page 44.

Leave the baseband noise power window open.

Now add some random noise dither by setting modctrl.dgain1=0.2 in the Matlab Command
Window.
Re-run the simulation to get another baseband noise power window.
(Refer to Figure 1 to double-check exactly where dither is being applied.)

1. What has happened to the tones and average power levels? (It is sufficient to
compare visually results with and without dither here, numerical answers are not
required.)
2. Why does dither cause this? Is adding dither a good idea then? Is so then how
much should you add? Can you add too much? Must the dither be white, or will,
e.g., Gaussian noise work? Don’t spend too long thinking about this; it is a good
topic to discuss with the teaching staff but somewhat beyond the scope of this
course.

1.5 DC Input with Finite Integrator Gain

We will now study the effect of finite integrator gain on the time domain waveforms and dc
transfer function of MOD1. You may wish to refer to section 2.8 of the course text during
this exercise.

Close all windows generated in Section 1.4 and open “dc_to_mod1.mdl” again.
Simulations so far have assumed an idea integrator with infinite integrator gain at dc; this
is trivially easy to achieve in digital modulators, but in analogue modulators the integrator
gain at dc will be finite owing to things like finite amplifier gains, leakage currents
discharging integration capacitors, etc.

Remove the dither by setting modctrl.dgain1=0.0.

Now introduce a finite dc gain error in the modulator by setting modctrl.igain1=50. Recall
that an ideal integrator’s gain tends to infinity for input frequencies tending towards dc.
Now the gain will level-off for low-frequency inputs and the integrator looks like a low-pass
filter with dc gain 50.

Try a few dc levels: input_dc = 0.4367, 0.1, 0.01 and 0.005.

1. Note the difference between the output filter QUANTLPF and the input_dc value,
and observe the LOOPERR, INT1OUT and QUANTOUT waveforms. Is the
modulator still an accurate dc ADC, i.e. do the input and output dc levels match? If
not then why not?
2. Comment in particular on the MOD1 output with inputs 0.01 and 0.005. What is
happening here?
3. Comment also on any tone frequencies (you are not expected to check them by
hand-calculation here), just note if they have changed compared to the infinite gain
case.

Close the dc_to_mod1.mdl window and now perform a dc sweep for a subset of the input
range (-0.1 to +0.1) by running “sweep_dc_dc”.

Now type modctrl.igain1=inf and rerun “sweep_dc_dc” to get an ideal integrator transfer
function for comparison.

1. Compare the dc sweep results for an ideal integrator and one with finite dc gain 50.
Which is the best ADC (i.e. which gives output = input most accurately)?
2. Note the dead zone behaviour when modctrl.igain1= 50 (c.f. figure 2.24 in [1]).
These are the flat regions where the modulator output is the same for all modulator
inputs within the zone. It is strongest about input 0, but small additional dead zones
can be noted around other rational inputs. Is this behaviour desirable or
undesirable? Why?
3. Measure the width of the main dead zone around input_dc = 0 and relate this to the
integrator gain - compare it to that predicted on page 53 of the course text for A=50.
Do you get a good match with theory?

See page 51-53 and Fig. 2.24 of [1] for more information about dead zones.

1.6 Sine Wave Input

We will now examine the behaviour of MOD1 in response to a sine wave input.

The parameter sinfreq (default: 4882.8125 Hz – note that with the default number of
significant digits Matlab will show this as 4882.8 Hz) and sinamp (default 0.707) set the
frequency and amplitude of the input sine wave.
(Note this frequency has been chosen such that an integer multiple (40) of complete
periods of the sinusoid are present within the 213 = 8192 samples acquired by the FFT
routine and also so that the sine wave frequency falls exactly into one of the PSD bins.

Such measures are generally very necessary to avoid effects like spectral leakage (even if
windowing is being used - we highly recommend you read appendix A of [1]) or waveform
truncation from corrupting the simulation results. Satisfying the dual needs of a complete
number of waveform cycles in a power-of-2 sample window length in addition to the signal
being in an exact FFT bin can limit the number of input frequencies that can be simulated
well. Please bear this in mind throughout all labs; careless frequency choices can
easily generate plots dominated by FFT artefacts instead of modulator behaviour,
especially at the high signal-to-noise ratios we will be interested in!)

Close the Simulink windows from the previous section.

Open “sin_to_mod1.mdl” and ensure modctrl.igain1=Inf (typing “init_vars” again will reset
all variables to suitable values). This schematic is identical to dc_to_mod1 but with a
discrete time sampled sinewave source replacing the dc input source.

Run the simulation.

You will see an FFT of the modulator output showing a large input tone and a rising
quantisation noise spectrum (difficult to see easily here due to the large number of
spurious tones).

Type “Qout_SNDR” to see the plot with log axes (you may be able to select a log X-axis in
the spectrum scope, but this is unfortunately not possible with some versions the Simulink
Spectrum Scope, e.g. those supplied with Matlab versions earlier than R2014) and the
value of the baseband signal to noise+distortion ratio (SNDR) for an oversampling factor of
64.

Double click on the time scope to observe the waveforms at the nodes in the modulator.

Zoom into a few cycles of the LOOPERR, INT1OUT and QUANTOUT waveforms.

1. Note the amplitudes of the LOOPERR and INT1OUT waveforms.

2. Can you see the sinewave captured in the modulator output QUANTOUT in the
varying density of 1s and -1s in its output sequence? Does the digital output stream
look like it encodes the input sinewave accurately?
3. Is the modulator a good analogue to digital converter? That is, is the output
sinewave after the low-pass filter a good copy of the input sine wave (ignore any
phase shift between the input and output, as this is predominantly caused by the
low-pass filter)? Note the effective number of bits reported earlier by Qout_SNDR
and comment on how this compares with the number of bits in the modulator
internal quantiser.

Type “sinfreq = sinfreq/8” to reduce the input frequency and re-run the experiment.

1. Note the changes in the waveforms, FFT and SNDR.

2. Measure the slope of the quantisation noise spectrum; is this what you expect for
first-order noise shaping?
Repeat the exercise for sinfreq=4882.8125 Hz and sinamp = 0.95 and 1.05

1. Note the amplitudes of LOOPERR and INT1OUT and compare with those obtained
when sinamp was 0.707 (keep these results as they will be required in lab 2).
Comment on the SNDR difference for input amplitudes 0.95 and 1.05. Does MOD1
recover readily from overload caused by the peaks of the sinamp = 1.05 signal?

1.7 Sine Wave Amplitude Sweep

We will now study the signal to quantisation noise of MOD1 in response to a range of sine
wave amplitudes.

Close “sin_to_mod1.mdl” and any plot windows and set sinfreq=4882.8125 Hz if it is not
already so.

Run the routine “sweep_sin_ampl_sqnr”.

The sweep_testbench.mdl window will appear; you can ignore it if it does not automatically
disappear. You will see a plot of signal to quantisation noise ratio (SQNR) versus sine
wave input amplitude in decibels (dBs), where 0 dB corresponds to amplitude = 1.

1. Note the peak value of SQNR and compare this to the theoretical SQNR from the
formula:
 2L
SQNR  6.02.N  1.76  (20 L  10) log 10 (OSR )  10 log 10 (
)
2L  1
where the modulator order L=1, the oversampling ratio OSR=64, and number of bits
N=1. Do you get a reasonable match?
2. Why isn’t the peak SQNR achieved for maximum signal (0 dB)? What has
happened at 0 dB?

What SNR do you observe below an input level of -35 dB of full-scale (FS)? You will find
there is no signal here, so the SNR = 0 (because S=0). This is not a dead-zone, but an
artefact of MOD1’s (awful!) tendency to tonal behaviour. This behaviour is very input
dependent; for example, re-running the sweep with sinfreq = 610.3516 Hz gives a much
“better behaved” result. Try it. One way we have seen to disrupt tones and limit cycles
from forming is to inject a (pseudo)random dither in to the loop.

Now try adding a small amount of dither.

Set sinfreq = 4882.8125 Hz and modctrl.dgain1=0.2 in the Matlab Command Window and
re-run the simulation.

1. How has behaviour below -35 dB input altered? Does the modulator look “better
behaved” (no flat regions or wild swings in the SQNR versus amplitude plot) with
dither? Why?
2. What is the peak SQNR value? Compare to that predicted by the above formula.
Again, comment on any drop in SQNR as the input amplitude rises from -1 dB to 0
dB.

Set modctrl.dgain1 = 0.8 and re-run the simulation.

 1. Does the SNDR versus amplitude curve look to have improved further by adding
even more dither?
2. What is the peak SQNR now? What has adding more dither done to the peak
SQNR? What then could be one downside to adding large amounts of dither to help
disrupt the loop tendency towards tonal behaviour?

Reset the dither level to modctrl.dgain1=0.0.

Set the finite integrator gain with modctrl.igain1=10.

3. How has the SQNR graph changed? Is the modulator ever likely to be a good
noise-shaping ADC with an integrator gain of only 10? Would you expect it to be?

1.8 Learning review

This lab has examined some key, basic properties of DSMs by studying specifically the
behaviour of the basic modulator MOD1. Hopefully being able to experiment with a
modulator in simulation and seeing effects like noise-shaping, dc tone generation, dead-
zones and the effects of dither etc. in action will aid your understanding of the various
significant basic principles underlying all DSM operation covered in the course lectures.

You may also have noted that despite being the obvious start point for modulator study,
MOD1 is actually quite a dreadful modulator; being highly prone to:

1. dc limit cycles (tonal spectrum with no noise-shaping),

2. idle tones with sine wave or irrational dc input (noise shaping evident, but with
strong tonal behaviour also present),
3. wide dead zones unless the integrator dc gain is very high.

Consequently MOD1 is not widely used on its own. Applying dither helps greatly, but in
practice with real modulators having limited integrator output swing etc., dither tends to
overload single-bit MOD1s, causing further problems. Offering only first-order noise
shaping, MOD1 is also limited in achievable SQNR for realistic oversampling ratios (to
achieve 16 bits ENOB for audio signals to 20 kHz would require the MOD1 to be clocked
at 100 MHz).

For the above reasons, MOD1, especially with 1-bit quantisation, is not commonly seen,
even for the least demanding applications (MOD1 does appear often as part of certain
cascaded modulators called MASH and SMASH converters to be examined in later labs).

The next labs will introduce higher-order modulators that behave much more like ideal
delta-sigma modulators (and so will hopefully be a much better aid than MOD1 to gaining
a better insight into and understanding of modulator behaviour), give far better SQNR at
moderate oversampling ratios, and that are thus much more commonly used.

1.9 Additional material

If you have finished the lab with time to spare, or using some time afterwards, you may
wish to become familiar with the important topic of “effective gain” of a 1-bit quantiser,
covered in section 2.1.1 of [1]. See also section 3.3.1.
Variation of effective quantiser gain with input signal level – especially for modulators
using 1-bit quantisation – is the source of many instability or “real NTF ≠ intended NTF
with degraded performance consequences” problems in practice.

Some test-benches with 1, 2 and 3-bit midrise quantisers with output range [-1:1] are
provided in LAB1:

quantiser1bit.mdl
quantiser2bit.mdl
quantiser3bit.mdl

Additionally, the ELEE11080_ROUTINES script

calc_quant_gain.m

has been provided. To use these, first open and run one of the quantiser test benches and
then type “calc_quant_gain” to compute the effective quantiser gain. You may wish to
examine the calc_quant_gain.m script and compare with section 2.1.1 of [1]. The sine
wave input is best for visually studying the quantiser operation by clicking on the signal
scope. The white noise source is better for estimating the gain.

You should alter the peak values of the sine or white noise quantiser input signal (by
clicking on the relevant signal source block and editing appropriately) and note the
effective gain. You may wish to plot a graph of gain versus input amplitude from, say, 0.25
to 1.5 in 0.25 steps using the white noise source for the 1-bit and 3-bit quantiser and
compare them. Which has the better-defined gain? Why? (Hint, sketch the quantiser
transfer functions: which uses more than 2 points to define the gain of a corresponding
linearised quantiser model? When does input overload start for each?)

References:
[1] Schreier, Temes: Understanding Delta-Sigma Data Converters, Wiley-Blackwell 2004.