Digital Systems Lab Manual
Digital Systems Lab Manual
CSE 2205
Lab Manual
1.1 Objectives:
7 Ground 14 +Vcc
7 Ground 14 +Vcc
7 Ground 14 +Vcc
1 Input 2 Output
3 Input 4 Output
5 Input 6 Output
13 Input 12 Output
11 Input 10 Output
9 Input 8 Output
7 Ground 14 +Vcc
7 Ground 14 +Vcc
7 Ground 14 +Vcc
PIN
PIN no. Function Function
no.
7 Ground 14 +Vcc
PIN
PIN no. Function Function
no.
7 Ground 14 +Vcc
PIN description
PIN
PIN no. Function Function
no.
8, 9 2Q, 2 Q 5 CLR
PIN description
Output Output
2,6 3,5
( Q A, Q B) QA, QB
CLKA, Reset
12,9 13,10
CLKB (RA,RB)
Input
1,8 7 GND
(JA,JB)
Input
4,11 14 Vcc
(KA,KB)
2.1 Objectives:
2.3.2.4 The selected component can be located on the left side window of the design diagram.
2.3.2.5 To put the component to the design sheet, just left click the component and put it
to the sheet.
2.3.2.6 To move the components, simply right click on the component (the component
will be red-lighted), and left click and drag the component to the desired location.
2.3.2.7 Selection of power and ground terminals: For power terminal and ground, the
component is NOT selected from the library. Select the “terminals mode” icon at
the left- side toolbar. Select POWER and GROUND terminals.
Having drawn the schematic, you choose the type of circuit analysis you require (transient,
frequency, noise, etc.) by placing a Graph of the appropriate type on the schematic. You can
place as many graphs as you want and can even have several graphs of the same type if you
wish. Graph types supported include: Analogue, Digital and Mixed transient graphs as well as
Frequency, Transfer, Noise, Distortion, Fourier, AC Sweep and DC Sweep and Audio graphs.
Set voltage probe or current probe to the circuit node or branch in which you want to see the
graphs. Then drag the probe to graph box or right click the graph box to add probe parameter by
“Add Traces” option. Finally right click the graph box and select “Simulate Graph” option.
Step3: Play and observe the output logic for different combination of input logic.
3.1 Objectives:
1. To examine the operation of fundamental logic gates AND, OR, NOT, NAND, NOR,
XOR and determine their logical properties.
2. To derive the truth tables of logic gates and verify their logic equations.
3.5.2 Use the data switches for input and LEDs for output.
3.5.4 Observe the outputs for different input configurations and fill in the data table.
3.5.6 Verify the truth tables and output equations obtained for different logic gates.
0 0
0 1
1 0
1 1
Output
Equations
You are responsible for documenting your work and your report must include (at minimum) the
following:
3.7.1 Cover sheet (Showing your Name, ID, Semester, Section, Exp. Name, Course
Title, Course Code at least)
3.7.2 Objectives of the experiment.
3.7.3 List of Components.
3.7.4 Draw proper circuit diagrams and figures.
3.7.5 List the output of the circuit and include it with your report.
3.7.6 The circuit is working properly or not. If not, where did you think the errors lie?
3.7.7 Simulate the circuit in PROTEUS and attach simulation result in lab report.
3.7.8 Answer the following questions:
3.7.8.1 How you can construct NAND and NOR gates using the basic logic gates AND,
OR, NOT?
3.7.8.2 Why NAND and NOR gates are called universal gate?
3.7.8.3 Construct AND, OR and NOT gate by using NAND gate only. Also, construct
these gates by using NOR gate only.
4.1 Objectives:
2. To derive the truth tables of logic gates and verify their logic equations.
D1
A
Y
B
D2
D1
A
Y
B
D2
R= 1KΩ
5V
+Vcc
R2= 1KΩ
Y
R1= 1KΩ
A Q
4.4.1 Place the components of the circuit shown in figure 4.1 on the trainer board and link
the connections correctly.
4.4.2 Use the data switches for input and LEDs for output.
4.4.4 Observe the outputs for different input configurations and fill in the data table.
4.4.7 Verify the truth tables and output equations obtained for different logic gates.
0 0
0 1
1 0
1 1
Output Equations
You are responsible for documenting your work and your report must include (at minimum) the
following:
4.6.1 Cover sheet (Showing your Name, ID, Year, Semester, Exp. Name, Course
Title, Course Code at least)
4.6.2 Objectives of the experiment.
4.6.3 List of Components.
4.6.4 Draw proper circuit diagrams and figures.
4.6.5 Discuss the function of every component that you have used to make the circuit.
4.6.6 List the output of the circuit and include it with your report.
4.6.7 The circuit is working properly or not. If not, where did you think the errors lie?
4.6.8 Simulate the circuit in PROTEUS and attach simulation result in lab report.
4.6.9 Answer the following questions :
4.6.9.1 Draw the circuit diagram of a NOR gate using diodes, transistors and resistors.
4.6.9.2 Draw the circuit diagram of a NAND gate using diodes, transistors and resistors.
5.1 Objectives:
1. To implement the given Boolean function and develop the truth table.
2. To simplify the function and develop the truth table and verify it.
5.4.1 Place the components of the circuit shown in figure 5.1 on the trainer board and link
the connections correctly.
5.4.2 Use the data switches for input and LEDs for output.
5.4.4 Observe the outputs for different input configurations and fill up the truth table.
X Y Z F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Output Equations
You are responsible for documenting your work and your report must include (at minimum) the
following:
5.6.1 Cover sheet (Showing your Name, ID, Semester, Year, Exp. Name, Course
Title, Course Code at least)
5.6.2 Objectives of the experiment.
5.6.3 List of Components.
5.6.4 Draw proper circuit diagrams and figures.
5.6.5 List the output of the circuit and include it with your report.
5.6.6 The circuit is working properly or not. If not, where did you think the errors lie?
5.6.7 Simulate the circuit in PROTEUS and attach simulation result in lab report.
5.6.8 Answer the following questions:
5.6.8.1 Draw the logic diagram for given Boolean function.
5.6.8.2 Discuss some important postulates of Boolean algebra.
6.1 Objectives:
1. To implement a Half-adder.
S=X Y and C = XY
X
S=X Y Z
Y
C = Z(X Y) + XY
Figure 6.2: Implementation of a Full-adder with two half adder and an OR gate.
6.4.1 Place the components of the circuit shown in figure 6.1 on the trainer
board and link the connections correctly.
6.4.2 Use the data switches for input and LEDs for output.
6.4.4 Observe the outputs for different input configurations and fill up the truth table.
6.4.6 Verify the obtained truth tables with output Boolean functions.
X Y S C
0 0
0 1
1 0
1 1
Output Equations
X Y Z S C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Output Equations
You are responsible for documenting your work and your report must include (at minimum) the
following:
6.6.1 Cover sheet (Showing your Name, ID, Semester, Section, Exp. Name, Course
Title, Course Code at least)
6.6.2 Objectives of the experiment.
6.6.3 List of Components.
6.6.4 Draw proper circuit diagrams and figures.
6.6.5 List the output of the circuit and include it with your report.
6.6.6 The circuit is working properly or not. If not, where did you think the errors lie?
6.6.7 Simulate the circuit in PROTEUS and attach simulation result in lab report.
6.6.8 Answer the following questions :
6.6.8.1 What do you mean by combinational circuit? Write down the procedure to
design a combinational circuit.
6.6.8.2 Mention some application of combinational circuit.
7.1 Objectives:
7.4.1 Place the components of the circuit shown in figure 8.1 on the trainer
board and link the connections correctly.
7.4.2 Use the data switches for input and LEDs for output.
7.4.4 Observe the outputs for different input configurations and fill up the truth table.
You are responsible for documenting your work and your report must include (at minimum) the
following:
7.6.1 Cover sheet (Showing your Name, ID, Semester, Section, Exp. Name, Course Title,
Course Code at least)
7.6.2 Objectives of the experiment.
7.6.3 List of Components.
7.6.4 Draw proper circuit diagrams and figures.
7.6.5 List the output of the circuit and include it with your report.
7.6.6 The circuit is working properly or not. If not, where did you think the errors lie?
7.6.7 Simulate the circuits in PROTEUS and attach simulation result in lab report.
7.6.8 Answer the following questions :