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Lab1 COA

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29 views4 pages

Lab1 COA

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maazhoney2243
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© © All Rights Reserved
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SE-212L Computer Organization & Architecture SSUET/QR/114

LAB # 1

OBJECTIVE:
To Understand and explore Visible Virtual Machine (VVM).

Lab Task:
 Write Detailed report on VVM.

1. Introduction to Visible Virtual Machine (VVM):


The Visible Virtual Machine (VVM) is a lightweight software-based simulator that models a
basic computer architecture, inspired by the Little Man Computer (LMC) developed by Stuart
Madnick in 1965. VVM provides an interactive environment for students to experiment with
core concepts of computer organization, including memory operations, instruction cycles, and
data flow between registers. Through VVM, learners gain practical exposure to how a
computer’s internal components work together to execute instructions. The simulator is designed
for educational purposes and simplifies hardware complexity by using decimal arithmetic
instead of binary, making it an effective tool for beginners in computer science and engineering.

2. Key Features of VVM:


The design of VVM focuses on clarity, flexibility, and interactivity to facilitate an intuitive
learning experience. Its key features include:
 Software-Based Virtual Machine:
VVM simulates hardware components through software, allowing users to interact with
elements such as registers, RAM, and the program counter in real time.
 Decimal-Based Data Handling:
All data, addresses, and operations use decimal integers, avoiding the cognitive burden
of binary or hexadecimal formats.
 Graphical User Interface (GUI):
The VVM environment offers a Windows-style program editor with syntax validation,
error reporting, and real-time updates to hardware components during program execution.
 Execution Control and Debugging:
VVM allows fine-grained control over program execution, offering options to run code
step-by-step, pause and resume, or adjust the execution speed. This ensures users can
observe how each instruction impacts registers and memory.

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SE-212L Computer Organization & Architecture SSUET/QR/114

3. Architecture of the VVM System:


The VVM system emulates essential hardware components to provide a realistic environment for
learning the instruction cycle and memory operations.
a) Accumulator Register (ACC):
 The ACC serves as a temporary buffer for arithmetic and logic operations. It also holds
intermediate results when data is transferred between memory and I/O.
 The valid range for values in the accumulator is -999 to +999. Operations producing
results outside this range trigger a data overflow error.
b) Instruction Register (IR):
 The IR stores the current instruction to be executed, divided into two parts:
1. Opcode: Specifies the operation to perform.
2. Operand: Represents the memory address or data associated with the operation.
c) Program Counter (PC):
 The PC holds the address of the next instruction in the sequence.
 If the program counter increments beyond the 99th address, it results in a program
counter overflow error, typically caused by a missing HALT instruction.
d) Random Access Memory (RAM):
 VVM provides 100 memory locations (addressed from 00 to 99), each capable of
holding a three-digit integer in the range of ±999.
 RAM stores both program instructions and data, enabling users to write self-contained
programs.
e) I/O Log:
 The I/O log serves as the system console, displaying events such as program input,
output, and error messages. This log provides insights into the program's runtime
behavior and helps users troubleshoot issues effectively.

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SE-212L Computer Organization & Architecture SSUET/QR/114

4. Instruction Cycle:
The VVM operates using a Fetch-Decode-Execute cycle, simulating the behavior of real
processors.
1. Fetch:
The PC retrieves the next instruction from memory.
2. Decode:
The IR interprets the opcode and determines the corresponding operation.
3. Execute:
The system performs the operation, updating relevant components (e.g., ACC, PC, or
RAM). If the instruction modifies the PC, the control flow may jump to a new address.

5. Error Handling in VVM:


VVM provides robust error handling by halting execution when specific system violations occur.
Common errors include:
 Data Overflow:
When the result of an operation exceeds ±999, the system halts with an overflow error.
 Undefined Instruction:
An invalid opcode in the IR triggers a system error, often caused by incorrect branching
logic or missing halt instructions.
 Program Counter Overflow:
If the PC value exceeds 99, the program crashes, typically due to an infinite loop or
missing halt operation.

6. Sample Program in VVM:


Below is a simple program that takes user input, stores it in the accumulator, and prints the value.
VVM Assembly Code:
arduino
Copy code
INP // Take input from the user
OUT // Display the inputted value
HLT // Stop the program

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SE-212L Computer Organization & Architecture SSUET/QR/114

Equivalent Machine Code:


arduino
Copy code
901 // Input instruction
902 // Output instruction
000 // Halt instruction
Explanation:
 INP (901): Prompts the user for an input, which is stored in the Accumulator.
 OUT (902): Prints the value in the Accumulator.
 HLT (000): Halts the program to prevent program counter overflow.

7. Benefits of VVM for Learning:


 Clear Visualization of Program Execution:
VVM displays the real-time state of registers, memory, and program flow, helping
students develop an intuitive understanding of computer architecture.
 Simplified Data Handling:
The use of decimal data makes VVM accessible to learners without requiring prior
knowledge of binary or hexadecimal systems.
 Error Detection and Debugging:
VVM identifies and halts on common programming errors (e.g., overflow and
instruction faults), encouraging users to debug their code systematically.

8. Conclusion:
The Visible Virtual Machine (VVM) provides an ideal platform for students to explore core
concepts of computer organization. Its user-friendly interface, simplified arithmetic, and real-
time feedback make it a powerful tool for teaching the basics of instruction cycles, memory
management, and branching logic. By abstracting some complexities of hardware, VVM
enables learners to focus on understanding how low-level operations are executed, preparing
them for more advanced studies in computer architecture.This technical report satisfies the
requirements of Lab 1 by offering a detailed overview of VVM’s components, operation, and
significance as a learning tool. If further customization or additional examples are required, feel
free to ask.

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