CD4093BC Quad 2-Input NAND Schmitt Trigger

October 1987
Revised January 1999

CD4093BC
Quad 2-Input NAND Schmitt Trigger
General Description ■ Equal source and sink currents
■ No limit on input rise and fall time
The CD4093B consists of four Schmitt-trigger circuits.
Each circuit functions as a 2-input NAND gate with Schmitt- ■ Standard B-series output drive
trigger action on both inputs. The gate switches at different ■ Hysteresis voltage (any input) TA = 25°C
points for positive and negative-going signals. The differ-
ence between the positive (VT+) and the negative voltage Typical VDD = 5.0V VH = 1.5V
VDD = 10V VH = 2.2V
(VT−) is defined as hysteresis voltage (VH).
VDD = 15V VH = 2.7V
All outputs have equal source and sink currents and con-
form to standard B-series output drive (see Static Electrical Guaranteed VH = 0.1 VDD
Characteristics).
Applications
Features • Wave and pulse shapers
■ Wide supply voltage range: 3.0V to 15V • High-noise-environment systems
■ Schmitt-trigger on each input • Monostable multivibrators
with no external components • Astable multivibrators
■ Noise immunity greater than 50% • NAND logic

Ordering Code:
Order Number Package Number Package Description
CD4093BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
CD4093BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram
Pin Assignments for SOIC and DIP

Top View

© 1999 Fairchild Semiconductor Corporation DS005982.prf www.fairchildsemi.com

CD4093BC
Absolute Maximum Ratings(Note 1) Recommended Operating
(Note 2) Conditions (Note 2)
DC Supply Voltage (VDD) −0.5 to +18 VDC DC Supply Voltage (VDD) 3 to 15 VDC
Input Voltage (VIN) −0.5 to VDD +0.5 VDC Input Voltage (VIN) 0 to VDD VDC
Storage Temperature Range (TS) −65°C to +150°C Operating Temperature Range (TA) −40°C to +85°C
Power Dissipation (PD) Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed; they are not meant to imply that
Dual-In-Line 700 mW the devices should be operated at these limits. The table of “Recom-
Small Outline 500 mW mended Operating Conditions” and “Electrical Characteristics” provides
conditions for actual device operation.
Lead Temperature (TL)
Note 2: VSS = 0V unless otherwise specified.
(Soldering, 10 seconds) 260°C

DC Electrical Characteristics (Note 2)

−40°C +25°C +85°C
Symbol Parameter Conditions Units
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD = 5V 1.0 1.0 7.5 µA
Current VDD = 10V 2.0 2.0 15.0 µA
VDD = 15V 4.0 4.0 30.0 µA
VOL LOW Level VIN = VDD, |IO| < 1 µA
Output Voltage VDD = 5V 0.05 0 0.05 0.05 V
VDD = 10V 0.05 0 0.05 0.05 V
VDD = 15V 0.05 0 0.05 0.05 V
VOH HIGH Level VIN = VSS, |IO| < 1 µA
Output Voltage VDD = 5V 4.95 4.95 5 4.95 V
VDD = 10V 9.95 9.95 10 9.95 V
VDD = 15V 14.95 14.95 15 14.95 V
VT− Negative-Going Threshold |IO| < 1 µA
Voltage (Any Input) VDD = 5V, VO = 4.5V 1.3 2.25 1.5 1.8 2.25 1.5 2.3 V
VDD = 10V, VO = 9V 2.85 4.5 3.0 4.1 4.5 3.0 4.65 V
VDD = 15V, VO = 13.5V 4.35 6.75 4.5 6.3 6.75 4.5 6.9 V
VT+ Positive-Going Threshold |IO| < 1 µA
Voltage (Any Input) VDD = 5V, VO = 0.5V 2.75 3.6 2.75 3.3 3.5 2.65 3.5 V
VDD = 10V, VO = 1V 5.5 7.15 5.5 6.2 7.0 5.35 7.0 V
VDD = 15V, VO = 1.5V 8.25 10.65 8.25 9.0 10.5 8.1 10.5 V
VH Hysteresis (VT+ − VT−) VDD = 5V 0.5 2.35 0.5 1.5 2.0 0.35 2.0 V
(Any Input) VDD = 10V 1.0 4.3 1.0 2.2 4.0 0.70 4.0 V
VDD = 15V 1.5 6.3 1.5 2.7 6.0 1.20 6.0 V
IOL LOW Level Output VIN = VDD
Current (Note 3) VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA
VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA
VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA
IOH HIGH Level Output VIN = VSS
Current (Note 3) VDD = 5V, VO = 4.6V −0.52 0.44 −0.88 −0.36 mA
VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA
VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 mA
IIN Input Current VDD = 15V, VIN = 0V −0.3 −10−5 −0.3 −1.0 µA
VDD = 15V, VIN = 15V 0.3 10−5 0.3 1.0 µA
Note 3: IOH and IOL are tested one output at a time.

www.fairchildsemi.com 2
 CD4093BC
AC Electrical Characteristics (Note 4)
TA = 25°C, CL = 50 pF, RL = 200k, Input tr, tf = 20 ns, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units

tPHL, tPLH Propagation Delay Time VDD = 5V 300 450 ns

VDD = 10V 120 210 ns
VDD = 15V 80 160 ns
tTHL, tTLH Transition Time VDD = 5V 90 145 ns
VDD = 10V 50 75 ns
VDD = 15V 40 60 ns
CIN Input Capacitance (Any Input) 5.0 7.5 pF
CPD Power Dissipation Capacitance (Per Gate) 24 pF
Note 4: AC Parameters are guaranteed by DC correlated testing.

3 www.fairchildsemi.com
CD4093BC
Typical Applications

Gated Oscillator

Assume t1 + t2 >> tPHL + tPLH then:

t0 = RC ln [VDD/VT−]
t1 = RC ln [(VDD − VT−)/(VDD − VT+)]

t2 = RC ln [VT+/VT−]

Gated One-Shot
(a) Negative-Edge Triggered

(b) Positive-Edge Triggered

www.fairchildsemi.com 4
 CD4093BC
Typical Performance Characteristics

Typical Transfer Guaranteed Trigger Threshold

Characteristics Voltage vs VDD

Guaranteed Hysteresis vs VDD Guaranteed Hysteresis vs VDD

Input and Output Characteristics

VNML = VIH(MIN) − VOL ≅ VIH(MIN) = V T+(MIN)

VNMH = VOH − VIL(MAX) ≅ VDD − VIL(MAX) = VDD − VT−(MAX)

5 www.fairchildsemi.com
CD4093BC
AC Test Circuits and Switching Time Waveforms

www.fairchildsemi.com 6
 CD4093BC
Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
Package Number M14A

7 www.fairchildsemi.com
CD4093BC Quad 2-Input NAND Schmitt Trigger
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N14A

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.